K7P403622B-HC20 Samsung, K7P403622B-HC20 Datasheet
K7P403622B-HC20
Specifications of K7P403622B-HC20
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K7P403622B-HC20 Summary of contents
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... K7P403622B K7P401822B Document Title 128Kx36 & 256Kx18 Synchronous Pipelined SRAM Revision History Rev. No. History Rev. 0.0 - Initial Document. Rev. 0.1 - Update Pin Discription. (M2=VDDQ -> M2=VDD) - Add AC characteristics. (250Mhz, 166Mhz) Rev. 0.2 - Update DC CHARACTERISTICS x36 : I : TBD -> 370, I DD25 x18 : I : TBD -> 360, I DD25 Rev. 1.0 - Final Version Rev ...
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... DD V DDQ 128Kx36 & 256Kx18 SRAM Maximum Part Number Frequency K7P403622B-HC25 250MHz K7P403622B-HC20 200MHz K7P403622B-HC16 166MHz K7P401822B-HC25 250MHz K7P401822B-HC20 200MHz K7P401822B-HC16 166MHz Memory Array Dec. 128Kx36 256Kx18 Data Out S/A Array MUX0 ...
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... K7P403622B K7P401822B PACKAGE PIN CONFIGURATIONS K7P403622B(128Kx36 DDQ DQc 8 E DQc DDQ G DQc 3 H DQc DDQ K DQd 1 L DQd DDQ N DQd 6 P DQd DDQ K7P401822B(256Kx18 DDQ DQb DDQ ...
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... FUNCTION DESCRIPTION The K7P403622B and K7P401822B are 4,718,592 bit Synchronous Pipeline Mode SRAM devices. They are organized as 131,072 words by 36 bits for K7P403622B and 262,144 words by 18 bits for K7P401822B, fabricated using Samsung's advanced CMOS technology. Single differential PECL level K clocks or Single ended or differential LVTTL clocks are used to initiate read/write operation and all internal operations are self-timed ...
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... K7P403622B K7P401822B TRUTH TABLE ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ NOTE : K & K are complementary ABSOLUTE MAXIMUM RATINGS ...
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... K7P403622B K7P401822B PIN CAPACITANCE Parameter Input Capacitance Data Output Capacitance NOTE : Periodically sampled and not 100% tested.(T DC CHARACTERISTICS Parameter Average Power Supply Operating Current-x36 ( & SS Average Power Supply Operating Current-x18 ( & SS Power Supply Standby Current ...
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... K7P403622B K7P401822B AC TEST CONDITIONS Parameter Core Power Supply Voltage Output Power Supply Voltage Input High/Low Level Clock Input High/Low Level(PECL) Input Rise/Fall Time Clock Input Rise/Fall Time(PECL) Input and Out Timing Reference Level Clock Input Timing Reference Level AC CHARACTERISTICS Parameter Clock Cycle Time ...
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... K7P403622B K7P401822B TIMING WAVEFORMS OF NORMAL ACTIVE CYCLES (SS Controlled, G=Low KHKH t t AVKH KHAX SAn SVKH KHSX SS SW SWx t KHQV DQn NOTE the input data written in memory location the output data read from the write data buffer(not from the cell array result of address A 4 last write cycle address ...
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... K7P403622B K7P401822B TIMING WAVEFORMS OF STANDBY CYCLES KHKH SAn SWx ZZ t KHQV DQn ZZE 128Kx36 & 256Kx18 SRAM ZZR t KHQV Jul. 2003 Rev 1.2 ...
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... K7P403622B K7P401822B IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG The SRAM provides a limited set of IEEE standard 1149.1 JTAG functions. This is to test the connectivity during manufacturing between SRAM, printed circuit board and other components. Internal data is not driven out of SRAM under JTAG control. In conform- ance with IEEE 1149 ...
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... K7P403622B K7P401822B SCAN REGISTER DEFINITION Part Instruction Register 128Kx36 3 bits 256Kx18 3 bits ID REGISTER DEFINITION Revision Number Part (31:28) 128Kx36 0000 256Kx18 0000 BOUNDARY SCAN EXIT ORDER(x36 DQc DQc 8 44 ...
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... K7P403622B K7P401822B JTAG DC OPERATING CONDITIONS Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage(I =-2mA) OH Output Low Voltage(I =2mA) OL NOTE : 1. The input level of SRAM pin is to follow the SRAM DC specification JTAG AC TEST CONDITIONS Parameter Input High/Low Level ...
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... K7P403622B K7P401822B 119 BGA PACKAGE DIMENSIONS 14.00±0.10 Indicator of Ball(1A) Location C1.00 0.60±0.10 12.50±0.10 119 BGA PACKAGE THERMAL CHARACTERISTICS Parameter Junction to Ambient Junction to Case Junction to Solder Ball NOTE : 1. Junction temperature can be calculated 128Kx36 & 256Kx18 SRAM 22.00±0.10 20.50±0.10 C0.70 1.50REF NOTE : 0.60±0.10 1. All Dimensions are in Millimeters. ...