MT9196AP Zarlink Semiconductor, MT9196AP Datasheet
MT9196AP
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MT9196AP Summary of contents
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... Integrated Digital Phone Circuit (IDPC) MT9196AP MT9196AE MT9196AS MT9196ASR MT9196APR MT9196AE1 MT9196APR1 MT9196AP1 MT9196AS1 MT9196ASR1 Description The MT9196 Integrated Digital Phone Circuit (IDPC) is designed for use in digital phone products. The device incorporates a built-in Filter/Codec, digital gain pads, DTMF generator and tone ringer. Complete telephony interfaces are provided for connecting to handset and speakerphone transducers ...
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... DATA2 IRQ 14 Dout 28 PIN SOIC/PDIP Figure 2 - Pin Connections Description /2) volts is available at this pin for biasing external amplifiers SSA . SSA for normal operation Zarlink Semiconductor Inc. Data Sheet 28 1 VSSA 2 27 MIC AUXin 25 4 AUXout 5 24 VSS SPKR 23 6 SPKR+ ...
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... Finally, most electro- acoustic transducers (loudspeakers) require a large amount of power if they are to develop an acoustic signal. The inclusion of audio amplifiers to provide this power is required. MT9196 Description 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Motorola SPI and National Semiconductor Microwire is also brought to an external pin so that it Bias may only be used internally, a 0.1 F capacitor from the V Ref and V pins are situated on adjacent pins. Bias 4 Zarlink Semiconductor Inc. Data Sheet ® specifications. ), for Bias to Bias pin Ref ...
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... Transmit Filter Trans- Trans- Gain mit mit Gain Gain (1 dB steps) 6.37 dB -0. 8.93 dB Analog Domain Figure 3 - Audio Gain Partitioning 5 Zarlink Semiconductor Inc. Data Sheet Handset Receiver (150 ) -6 -3.6 dB HSPKR + Receiver 75 Driver HSPKR - 75 Speaker SPKR + Phone Driver SPKR - ...
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... CCITT (G.711) Sign/ Magnitude -Law A-Law 1111 1111 1000 0000 1010 1010 1000 0000 1111 1111 1101 0101 0000 0000 0111 1111 0101 0101 0111 1111 0000 0000 0010 1010 Table 1 6 Zarlink Semiconductor Inc. Data Sheet -RxFG control bits, respectively. 2 ...
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... The ringer program switches between these two frequencies rate as selected by the WR bit in the DTMF/Tone ringer register (address 18h). MT9196 Frequency (in Hz) = 7.8125 x COEFF % Deviation -.20% +.40% -.05% +.46% +.20% .00% -.03% -.01% COEFF = [32000/Frequency (Hz Zarlink Semiconductor Inc. Data Sheet ...
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... When the transmit signal level falls below this threshold the programmed loss is switched from the received path back to the transmit path and comparison reverts back to the high threshold level. MT9196 Attenuation (dB Zarlink Semiconductor Inc. Data Sheet ...
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... The handset speaker outputs (receiver), pins HSPKR+/HSPKR-. This internally compensated, fully differential output driver is capable of driving the load shown in Figure 4. The nominal handset receive path gain may be adjusted to either -12 -9.6 dB. Control of this gain is provided by the RxINC control bit (Control MT9196 9 Zarlink Semiconductor Inc. Data Sheet ...
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... Motorola/National timing is assumed. Motorola processor mode CPOL=0, CPHA=0 must be used. DATA1 is defined as the data transmit pin while DATA2 becomes the data receive pin. Although the dual MT9196 TxINC=0 TxINC=1 RxINC=0 RxINC=1 HSPKR + 75 75 HSPKR - Figure 4 - Handset Speaker Driver 10 Zarlink Semiconductor Inc. Data Sheet 150 ohm load (speaker) ...
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... bit - Read/Write 7 5 bits - Addressing Data 2 bits - Unused X 11 Zarlink Semiconductor Inc. Data Sheet COMMAND/ADDRESS ...
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... A serial link is required to transport data between the IDPC and an external digital transmission device. IDPC utilizes the ST-BUS architecture defined by Zarlink Semiconductor but also supports a strobed data interface found on many standard CODEC devices. This interface is commonly referred to as Synchronous Serial Interface (SSI). ...
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... I,II,III,IV). These di-bits are composed of the two D-Channel bits received during each of frames n, n-1, n-2 and n-3. Referring to Fig. 8a: di-bit I is mapped from frame n- 3, di-bit II is mapped from frame n-2, di-bit III is mapped from frame n-1 and di-bit IV is mapped from frame n. MT9196 13 Zarlink Semiconductor Inc. Data Sheet ...
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... D-Channel No preset value * note that frame n+4 is equivalent to frame n of the next cycle. Figure 8a - D-Channel 16 kb/s Operation MT9196 Microport Read/Write Access n-1 n n+1 III Di-bit Group D0 D1 Transmit D-Channel 14 Zarlink Semiconductor Inc. Data Sheet n+2 n+3 n+4* II III Power-up reset to 1111 1111 ...
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... VII VIII III Di-bit Group Transmit D-Channel Power-up reset to 1111 1111 Figure 8c - D-Channel 8 kb/s Operation 15 Zarlink Semiconductor Inc. Data Sheet t =500 nsec max pullup Reset coincident with Read/Write of Address 15 Hex or next FP, whichever occurs first n+4 n+6 n+5 n+7 n+8 D-Channel IV VI ...
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... IDPC. Control bits Asynch/Synch, CSL1 and CSL0 in FDI Control Register (address 10h) are used to program the bit rates as shown in Table 3. MT9196 CLOCKin 33 pF 100 k XSTL2 4096 kHz Nominal 33 pF Figure 9 - External Crystal Circuit (for asynchronous operation) 16 Zarlink Semiconductor Inc. Data Sheet ...
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... Auxiliary In port. Or MT9196 Bit Clock CLOCKin CSL1 CSL0 Rate (kHz) (kHz 128 4096 mandatory 0 1 256 4096 mandatory 0 0 512 512 0 1 1536 1536 1 0 2048 2048 1 1 4096 4096 Table 3 17 Zarlink Semiconductor Inc. Data Sheet ...
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... WD output after the current interval 'T' expires. WD will then toggle at this rate until the watchdog register is again written to correctly. 5-Bit Watchdog Reset Word x=don’t care MT9196 , for operation. Note that in SSI mode, if STB disappears the Zarlink Semiconductor Inc. Data Sheet ...
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... To attain complete power-down from a normal operating condition, write all “0s” to the Transmit and Receive Path Control Registers (address 12h and 13h), set PD to logic 1 at address 0Eh, and Asynch/Synch to logic 1 at address 10h. MT9196 19 Zarlink Semiconductor Inc. Data Sheet -Law ...
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... Pad Pad RESERVED 20 Zarlink Semiconductor Inc. Data Sheet TxFG FCodec Control STG FCodec Control 2 0 TxMute Control Register 1 - Control Register 2 CSL FDI Control 0 W Watchdog Path Control Path Control ...
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... Side-tone Gain Gain1 Gain0 Setting (dB (default) OFF 0 1 -9. -6. - 9.96 21 Zarlink Semiconductor Inc. Data Sheet Power Reset Value X000 X000 0 0 TxFG TxFG TxFG ...
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... Note: Bits marked "-" are reserved bits and should be written with logic "0". MT9196 ADDRESS = 0Eh WRITE/READ VERIFY - B2/B1 RxMute TxMute - ADDRESS = 0Fh WRITE/READ VERIFY Smag RxINC TxINC CCITT Zarlink Semiconductor Inc. Data Sheet ADDRESS = 0Dh RESERVED Power Reset Value 100X X000 Power Reset Value 0X00 00XX -Law ...
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... Bit Clock Rate (kHz 128 1 256 0 512 1 1536 0 2048 1 4096 Zarlink Semiconductor Inc. Data Sheet Power Reset Value X000 0000 0 0 CLOCKin (kHz) 4096 mandatory 4096 mandatory 512 1536 2048 4096 ADDRESS = 11h WRITE Power Reset Value XXXX XXXX 0 0 ...
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... Rx Filter Reserved AUXin Handset mic ( Handsfree mic (MIC +) Reserved Reserved Voice sidetone path disabled 1 Voice sidetone path enabled 24 Zarlink Semiconductor Inc. Data Sheet Power Reset Value XXXX 0000 Power Reset Value 0000 0000 ...
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... ADDRESS = 17h WRITE/READ VERIFY - - - Loop1 - Zarlink Semiconductor Inc. Data Sheet ADDRESS = 14h WRITE/READ Power Reset Value 1111 1111 ADDRESS = 15h WRITE/READ Power Reset Value 1111 1111 ADDRESS = 16h RESERVED Power Reset Value XX00 XXXX ...
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... ADDRESS = 1Ah WRITE/READ VERIFY Frequency (in Hz) = 7.8125 x COEFF 26 Zarlink Semiconductor Inc. Data Sheet Power Reset Value 0000 XXX0 Power Reset Value 1000 1000 0 TxG TxG TxG ...
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... ADDRESS = 1Eh WRITE/READ VERIFY THI4 THI3 THI2 THI1 THI0 ADDRESSES 1Fh to 3Fh are RESERVED 27 Zarlink Semiconductor Inc. Data Sheet Power Reset Value H0 0000 0000 0 Power Reset Value 0X10 X100 0 Power Reset Value X011 0000 0 Power Reset Value X001 0100 ...
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... IDPC DSTo DSTi F0 Lin C4 MT8972 DNIC Z T Lout 10.24 MHz 28 Zarlink Semiconductor Inc. Data Sheet 330 + 0.1 F 511 Electret + Microphone 0.1 F 511 330 VBias + 0.1 F Electret + Microphone To Auxiliary Audio Source 40 nom ...
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... IDPC +5V DOUT Layer 1 DIN Transceiver BCL STB Asynch 4096 kHz Crystal 4096 kHz 4096 kHz External Clock from Layer 1 Device or other source 29 Zarlink Semiconductor Inc. Data Sheet 330 + 0.1 F 511 Electret + Microphone 0.1 F 511 330 VBias + 0.1 F Electret ...
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... Address DATA 19h 89h (or as required, defaults = 0dB) 0Bh 94h 1Dh as required or leave default value 1Eh as required or leave default value 1Ch A4h 12h 09h 12h 01h 13h 85h 30 Zarlink Semiconductor Inc. Data Sheet ...
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... E0h (both Hi EN and Lo EN) 18h A0h or 60h as required Address DATA 19h 88h (or as required) 1Ah as required 1Bh as required 12h 0Ch 12h 04h 13h 01h 13h 04h 13h 10h 18h E0h (both Hi EN and LO EN) 18h A0h or 60h as required 31 Zarlink Semiconductor Inc. Data Sheet ...
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... A Sym. Min. Typ. Max. I 400 DDC1 I 1.5 DDF1 I 1.5 DDF2 I 1.25 DDF3 I 1.25 DDF4 I 1.0 DDF5 I 14.0 19.0 DDFT 32 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units - 150 C 750 mW Units Test Conditions V V Includes Noise margin = 400 mV V Includes Noise margin = ...
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... ‡ Min. Typ. Max. Units 4095.6 4096 4096.4 kHz 4096 kHz 100 ppm @ +85 C 7pF Maximum 130 0.003%/ C from Zarlink Semiconductor Inc. Data Sheet Units Test Conditions Max. Load = 10k ...
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... D 360 AX D 750 DX 380 130 750 PSSR 37 PSSR1 40 PSSR2 35 PSSR3 40 34 Zarlink Semiconductor Inc. Data Sheet for rms Units Test Conditions Vp-p -Law Vp-p A-Law Both at CODEC Transmit filter gain=0dB setting. Digital gain=0dB setting. dB TxINC = 0* dB TxINC = 1* dB TxINC = 0* dB TxINC = 1* dB ...
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... D 240 AR D 750 DR 380 130 750 Zarlink Semiconductor Inc. Data Sheet for A-Law, at the CODEC. (V =1.0 rms Ref Units Test Conditions Vp-p -Law Vp-p A-Law Receive filter gain = 0dB setting. Digital gain = 0dB setting. dB RxINC = 0* dB RxINC = @1020 Hz dB ...
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... V 1.51 Vp-p R-12 V 951 mVp-p R-16 V 600 mVp-p R-20 V 379 mVp-p R-24 V 239 mVp-p R-28 36 Zarlink Semiconductor Inc. Data Sheet Test Conditions dB TxINC, RxINC both 0* dB TxINC, RxINC both 1* M inputs to HSPKR outputs 1000 Hz dB SIDEA/u=0 dB SIDEA/u=1 from nominal relative measurements w.r.t. G & G AS1 AS2 Units Test Conditions ...
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... IOLM 0.580 V 1.63 IOLA 0.580 V 2.90 IOLH 1. Zarlink Semiconductor Inc. Data Sheet Test Conditions across HSPKR each pin: HSPKR+, HSPKR- 300 ohms load across HSPKR (tol-15%), VO 693mV , RxINC=1*, RMS Rx gain=0dB across SPKR each pin SPKR+, SPKR- 40 ohms load across SPKR (tol-15%), VO 6 ...
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... DSToD t 30 DSTiS t 30 DSTiH 1 bit cell t C4P t DSToD t t DSTiH DSTiS t F0iH t T NOTE: Levels refer to%V Figure 12 - ST-BUS Timing Diagram 38 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions 50pF, 1k load C4H C4L DD ...
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... DIS t 50 DIH BCL BCLL t DIH ENW SSS NOTE: Levels refer to Zarlink Semiconductor Inc. Data Sheet Units Test Conditions ns BCL=4096 kHz to 512 kHz ns BCL=4096 kHz ns BCL=4096 kHz ns Note 1 ns Note 1 - =150 pF, R =1K ...
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... DATA DATA +500ns+T j +(n- DATA Bit 2 Bit 3 T DATA DATA DATA NOTE: Levels refer to Zarlink Semiconductor Inc. Data Sheet Units Test Conditions ns BCL=128 kHz ns BCL=256 kHz =150 pF =150 pF ...
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... IDS t 30 IDH t 100 ODD t 500 1000 CYC t 250 500 CH t 250 500 CL t 200 CSSI t 100 CSSM t 100 CSH t 100 OHZ 41 Zarlink Semiconductor Inc. Data Sheet Test Conditions 150pF 150pF ...
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... CH SCLK IDH t IDS 2.0V DATA INPUT 0.8V Figure 15 - Serial Microport Timing Diagram MT9196 DATA INPUT DATA OUTPUT t CYC CYC ODD 2.0V DATA OUTPUT 0.8V 42 Zarlink Semiconductor Inc. Data Sheet 90% 2.0V HiZ 0.8V 10% Intel t Mode = 0 ODD 2.0V 0.8V t OHZ 2.0V 0.8V t CSH 2.0V Motorola Mode = 00 0.8V 90% HiZ 10% NOTE: % refers to ...
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... Zarlink Semiconductor 2005. All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...