MC68334 Freescale Semiconductor, Inc, MC68334 Datasheet
MC68334
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MC68334 Summary of contents
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... Technical Summary 32-Bit Modular Microcontroller 1 Introduction The MC68334, a highly-integrated 32-bit microcontroller, combines high-performance data manipula- tion capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that interface through a common intermodule bus (IMB). Standardization facilitates rapid development of devices tailored for specific applications. ...
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... Analog-to-Digital Converter Module 6.1 Analog Subsystem ....................................................................................................................63 6.2 Digital Control Subsystem .........................................................................................................63 6.3 ADC Address Map .....................................................................................................................64 6.4 ADC Registers ...........................................................................................................................66 7 Standby RAM with TPU Emulation 7.1 Overview ...................................................................................................................................72 7.2 TPURAM Register Block ...........................................................................................................72 7.3 TPURAM Registers ...................................................................................................................72 7.4 TPURAM Operation ..................................................................................................................73 8 Summary of Changes 2 TABLE OF CONTENTS Page MC68334 MC68334TS/D REV. 1 ...
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... Two Timer Count Registers with Programmable Prescalers — Selectable Channel Priority Levels • 1-Kbyte Standby RAM with TPU Emulation (TPURAM) — External Standby Voltage Supply Input — Can be Used as Standby RAM or TPU Microcode Emulation RAM 1.2 Block Diagram MC68334 MC68334TS/D ) SSA 3 ...
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... AN4/PADA4 AN3/PADA3 AN2/PADA2 AN1/PADA1 AN0/PADA0 BKPT/DSCLK IFETCH/DSI IPIPE/DSO 4 V STBY SELECTS TPURAM TPU 1 KBYTE IMB CPU 32 ADC Figure 1 MC68334 Block Diagram CHIP CSBOOT BR ECLK/ADDR23/CS10 BG PC6/ADDR22/CS9 BGACK PC5/ADDR21/CS8 CS[10:0] PC4/ADDR20/CS7 PC3/ADDR19/CS6 FC2 PC2/FC2/CS5 PC1/FC1/CS4 FC1 FC0 PC0/FC0/CS3 BGACK/CS2 BG/CS1 BR/CS0 ADDR[23:0] ...
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... ADDR17 41 ADDR18 AN0/PADA0 45 AN1/PADA1 46 AN2/PADA2 47 AN3/PADA3 48 AN4/PADA4 Figure 2 MC68334 132-Pin QFP Pin Assignments MC68334 MC68334TS/D MC68334 V 116 DD 115 BGACK/CS2 114 BG/CS1 113 BR/CS0 112 CSBOOT 111 DATA0 110 DATA1 109 DATA2 108 DATA3 V 107 DD V ...
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... The standardized modules in the MCU communi- cate with one another and with external components through the IMB. The IMB in the MCU uses 24 address lines and 16 data lines. 6 TPURAM ARRAY UPPER 1 KBYTES OF 2-KBYTE BLOCK ADC SIM TPU Figure 3 MC68334 Address Map 334 ADDRESS MAP MC68334 MC68334TS/D ...
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... B MODCLK R/W A RESET Bo RMC B SIZ[1:0] B TPUCH[15:0] A TSC — T2CLK A — — V — 3 XFC — 3 XTAL R/W A MC68334 MC68334TS/D Table 2 MCU Pin Characteristics Input Input Synchronized Hysteresis — — — — — ...
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... A/D Reference Voltage External Periphery Power (Source and Drain) Internal Module Power (Source and Drain) Table 4 MCU Driver Types Description Discrete Port I/O Designation — — I/O PE3 I/O PE[7:6] — — — — — — — — — — — — — — Description MC68334 MC68334TS/D ...
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... IRQ[7:1] MODCLK PADA[6:0] PC[6:0] PE[7:0] PF[7:0] QUOT R/W RESET RMC SIZ[1:0] TPUCH[15:0] TSC T2CLK XFC XTAL MC68334 MC68334TS/D Table 5 MCU Signal Characteristics MCU Module Signal Type SIM Bus ADC Input SIM Output SIM Input SIM Input SIM Output SIM Input CPU32 Input SIM ...
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... Provides the quotient bit of the polynomial divider System reset Indicates the direction of data transfer on the bus Indicates the number of bytes to be transferred during a bus cycle Bidirectional TPU channels Places all output drivers in a high-impedance state TPU clock input Function MC68334 MC68334TS/D ...
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... The “Access” column in the SIM address map below indicates which registers are accessible only at the supervisor privilege level and which can be assigned to either the supervisor or user privilege level, according to the value of the SUPV bit in the SIMCR. MC68334 MC68334TS/D REV. 1 CLKOUT EXTAL MODCLK ...
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... PORT F DATA (PORTF0) PORT F DATA (PORTF1) PORT F DATA DIRECTION (DDRF) PORT F PIN ASSIGNMENT (PFPAR) SYSTEM PROTECTION CONTROL (SYPCR) SOFTWARE SERVICE (SWSR) NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED PORT C DATA (PORTC) NOT USED MC68334 MC68334TS/D REV. 1 ...
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... MCU system protection includes a bus monitor, a HALT monitor, a spurious interrupt monitor, and a software watchdog timer. These functions have been made integral to the microcontroller to reduce the number of external components in a complete control system. MC68334 MC68334TS/D REV. 1 Table 7 SIM Address Map CHIP-SELECT OPTION 4 (CSOR4) ...
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... HALT MONITOR BUS MONITOR SPURIOUS INTERRUPT MONITOR SOFTWARE WATCHDOG TIMER PERIODIC INTERRUPT TIMER SHEN SUPV RESET REQUEST BERR RESET REQUEST IRQ [7:1] SYS PROTECT BLOCK $YFFA00 IARB MC68334 MC68334TS/D REV ...
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... The reset value of IARB for the SIM is %1111, and the reset IARB value for all other modules is %0000, which prevents SIM interrupts from being discarded during initialization. MC68334 MC68334TS/D REV. 1 Action Show cycles disabled, external arbitration enabled Show cycles enabled, external arbitration disabled ...
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... BMT Bus Monitor Time-out Period 00 64 System Clocks 01 32 System Clocks 10 16 System Clocks 11 8 System Clocks $YFFA21 SWT HME BME BMT Ratio MC68334 MC68334TS/D REV. 1 ...
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... The watchdog clock rate is affected by SWP and SWT in SYPCR. When SWT[1:0] are modified, a watchdog service sequence must be performed before the new time-out period takes effect. The reset value of SWP is affected by the state of the MODCLK pin on the rising edge of reset, as shown in the following table. MC68334 MC68334TS/D REV ...
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... Interrupt Request Level 4 101 Interrupt Request Level 5 110 Interrupt Request Level 6 111 Interrupt Request Level PTP MODCLK $YFFA22 PIV $YFFA24 PITM MC68334 MC68334TS/D REV ...
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... SYNCR control bits have no effect. To generate a reference frequency using the internal oscillator a reference crystal must be connected between the EXTAL and XTAL pins. The figure below shows a recommended circuit. MC68334 MC68334TS/D REV. 1 PITM Prescale 4 PIT Period = ...
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... PLL is disabled. The XFC pin must be left floating in this case 330k SSI Minimum External Clock Period = § Low Time supply. Refer to the SIM Reference Manual (SIMRM/AD) for more in- DD XTAL EXTAL 32 OSCILLATOR source. Adequate DDSYN pin to assure stable DDSYN DDSYN MC68334 MC68334TS/D REV. 1 ...
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... ECLK frequency can be set to system clock frequency divided by eight or system clock frequency divided by sixteen. The clock is enabled by the CS10 field in chip select pin assignment register 1 (CSPAR1). ECLK operation during low-power stop is described in the following paragraph. Refer to 3.5 Chip Selects for more information about the external bus clock. MC68334 MC68334TS/D REV 0 XFC ...
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... External Off Off Clock External External External Clock Clock Clock External Off Off Clock External External External Clock Clock Clock VCO VCO VCO Crystal or Off Off Reference Crystal or Crystal/ Off Reference Reference VCO Off Off VCO VCO VCO MC68334 MC68334TS/D REV. 1 ...
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... VCO is enabled, but has not locked VCO has locked on the desired frequency (or system clock is external). The MCU maintains reset state until the synthesizer locks, but SLOCK does not indicate synthesizer lock status until after the user writes to SYNCR. MC68334 MC68334TS/D REV ...
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... AS is asserted. R/W only chang- es state when a write cycle is preceded by a read cycle or vice versa. The signal can remain low for two consecutive write cycles. SIZ1 24 Table 9 Size Signal Encoding SIZ0 Transfer Size 0 1 Byte 1 0 Word Byte 0 0 Long Word MC68334 MC68334TS/D REV. 1 ...
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... The internal bus monitor can be used to generate the BERR signal for internal and internal-to-external transfers. When BERR and HALT are asserted simultaneously, the CPU takes a bus error exception. MC68334 MC68334TS/D REV. 1 FC1 FC0 Address Space ...
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... Complete Cycle — Data Bus Port Size is 8 Bits 1 Complete Cycle — Data Bus Port Size is 16 Bits 0 Reserved Byte Order OP0 OP1 OP2 OP0 OP1 OP0 Figure 9 Operand Byte Order Result OP3 OP2 OP1 OP0 MC68334 MC68334TS/D REV. 1 ...
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... Long Word to 16-Bit Port (Misaligned) 1. Operands in parentheses are ignored by the CPU32 during read cycles. 2. The CPU32 does not support misaligned word or long-word transfers. 3. Three-byte transfer cases occur only as a result of a long word to byte transfer. MC68334 MC68334TS/D REV. 1 Table 12 Operand Alignment SIZ1 SIZ0 ADDR0 ...
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... The following table lists allocation of chip-selects and discrete outputs on the pins of the MCU. 28 TIMING CONTROL OPTION COMPARE OPTION REGISTER PIN DSACK ASSIGNMENT GENERATOR REGISTER AND PIN PIN DATA REGISTER CHIP SEL BLOCK MC68334 MC68334TS/D REV. 1 ...
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... Chip Select CSBOOT CS0 CS1 CSPAR0 CS2 CS3 CS4 CS5 CS6 CS7 CSPAR1 CS8 CS9 CS10 MC68334 MC68334TS/D REV. 1 Table 13 Chip Select Allocation Chip Select Discrete Outputs CSBOOT CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8 CS9 CS10 Table 14 Chip-Select Pin Functions ...
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... CSBOOT CSPA0[2] CSPA0[1] DATA1 1 DATA1 1 1 DATA0 Discrete Output FC2 PC2 FC1 PC1 FC0 PC0 — BG — BR — — — $YFFA46 CSPA1[2] CSPA1[1] CSPA1[0] DATA 1 DATA 1 DATA [7:5] [7:4] [7:3] Discrete Output ECLK PC6 PC5 PC4 PC3 MC68334 MC68334TS/D REV ...
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... A memory device containing the reset vector and initialization routine can be automatically enabled by CSBOOT after a reset. The block size field in CSBARBT has a reset value of 512 Kbytes. MC68334 MC68334TS/D REV. 1 Chip-Select/Address Bus Pin Function DATA4 DATA3 ...
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... ADDR ADDR BLKSZ $YFFA4A AVEC SPACE IPL $YFFA4E–$YFFA76 AVEC SPACE IPL MC68334 MC68334TS/D REV ...
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... DSACK generation by controlling the number of wait states that are inserted to op- timize bus speed in a particular application. The following table shows the DSACK field encoding. The fast termination encoding (1110) is used for two-cycle access to external memory. MC68334 MC68334TS/D REV. 1 Byte Description 00 ...
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... Wait States 1110 Fast Termination 1111 External DSACK Space Address Space 00 CPU Space 01 User Space 10 Supervisor Space 11 Supervisor/User Space IPL Description 000 Any Level 001 IPL1 010 IPL2 011 IPL3 100 IPL4 101 IPL5 110 IPL6 111 IPL7 MC68334 MC68334TS/D REV. 1 ...
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... The bits in this register control the direction of the pin drivers when the pins are configured as I/O. Any bit in this register set to one configures the corresponding pin as an output. Any bit in this register cleared to zero configures the corresponding pin as an input. This register can be read or written at any time. MC68334 MC68334TS/D REV ...
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... Bus Control Signal SIZ1 SIZ0 AS DS RMC AVEC DSACK1 DSACK0 $YFFA19, $YFFA1B PF5 PF4 PF3 PF2 PF1 $YFFA1D DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 MC68334 MC68334TS/D REV PF0 ...
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... The logic states of certain data bus pins during reset determine SIM operating configuration. In addition, the state of the MODCLK pin determines system clock source and the state of the BKPT pin determines what happens during subsequent breakpoint assertions. The following table is a summary of reset mode selection options. MC68334 MC68334TS/D REV ...
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... Alternate Function (Pin Pulled Low) CSBOOT 8-Bit BR BG BGACK FC0 FC1 FC2 ADDR19 ADDR[20:19] ADDR[21:19] ADDR[22:19] ADDR[23:19] PORTE PORTF Test Mode Enabled EXTAL = System Clock Background Mode Enabled Function DSI/IFETCH DSO/IPIPE BKPT/DSCLK TPU Input TCR2 Clock Analog Input MC68334 MC68334TS/D REV. 1 ...
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... When TSC assertion takes effect, internal signals are forced to values that can cause inadvertent mode selection. Once the output drivers change state, the MCU must be powered down and restarted before normal operation can resume. MC68334 MC68334TS/D REV applied before and during reset. This mini- DDSYN is applied at power-on, start-up time is affected by specific DDSYN ramp-up time also affects pin state during reset ...
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... Arbitration is performed by means of serial contention between values stored in individual module inter- rupt arbitration (IARB) fields. Each module that can make an interrupt service request, including the SIM, has an IARB field in its configuration register. IARB fields can be assigned values from %0000 to 40 MC68334 MC68334TS/D REV. 1 ...
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... FC[2:0] are driven to %111 (CPU space) encoding. 2. The address bus is driven as follows: ADDR[23:20] = %1111; ADDR[19:16] = %1111, which indicates that the cycle is an interrupt acknowledge CPU space cycle; ADDR[15:4] = %111111111111; ADDR[3:1] = the priority of the interrupt request being acknowledged; and ADDR0 = %1. MC68334 MC68334TS/D REV. 1 WARNING 41 ...
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... TSTMSRA — Master Shift Register A TSTMSRB — Master Shift Register B TSTSC — Test Module Shift Count TSTRC — Test Module Repetition Count CREG — Test Module Control Register DREG — Test Module Distributed Register 42 $YFFA02 $YFFA08 $YFFA30 $YFFA32 $YFFA34 $YFFA36 $YFFA38 $YFFA3A MC68334 MC68334TS/D REV. 1 ...
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... The user programming model remains unchanged from previous M68000 Family microprocessors. Ap- plication software written to run at the non-privileged user level migrates without modification to the CPU32 from any M68000 platform. The move from SR instruction, however, is privileged in the CPU32 not privileged in the M68000. MC68334 MC68334TS/D REV ...
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... A7 (USP CCR 0 A7' (SSP (CCR VBR 2 0 SFC DFC Data Registers Address Registers User Stack Pointer Program Counter Condition Code Register Supervisor Stack Pointer Status Register Vector Base Register Alternate Function Code Registers MC68334 MC68334TS/D REV. 1 ...
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... Included in the register indirect addressing modes are the capabilities to post-increment, predecrement, and offset. The program counter relative mode also has index and offset capabilities. In addition to these addressing modes, many instructions implicitly specify the use of the status register, stack point- er, or program counter. MC68334 MC68334TS/D REV ...
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... Data), CCR shows results 8, 16, 32 (Destination – Source), CCR shows results 8, 16, 32 Lower bound Rn Operation + X Destination 10 Destination Destination Destination Destination Destination Destination Destination 0 X – (SSP); (vector (SP Upper bound, CCR shows result MC68334 MC68334TS/D REV. 1 ...
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... Rc, Rn MOVEC Rn, Rc MOVEM list list MOVEP MC68334 MC68334TS/D REV. 1 Table 23 Instruction Set Summary Operand Size 16 If condition false, then Dn – – 1), then 16: 16 Destination / Source (signed or unsigned Destination / Source (signed or unsigned) 32/ ...
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... Source condition true, then destination bits are set to one; else, destination bits are cleared to zero 16 Data SR; STOP 8, 16, 32 Destination – Source Operation Rn Destination Destination Destination Destination Destination SP; (SP) PC; SP; (SP) PC; SP – X Destination 10 Destination MC68334 MC68334TS/D REV ...
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... An NOTE: 1. Privileged instruction 4.7 Background Debugging Mode The background debugger on the CPU32 is implemented in CPU microcode. The background debug- ging commands are summarized below. MC68334 MC68334TS/D REV. 1 Table 23 Instruction Set Summary 16, 32 Destination – Source 8, 16, 32 Destination – Data 8, 16, 32 Destination – Data 8, 16, 32 Destination – ...
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... Instruction execution begins at user patch code. RST Asserts RESET for 512 clock cycles. The CPU is not reset by this command. Synonymous with the CPU RESET instruction. NOP NOP performs no operation and can be used as a null command. Description MC68334 MC68334TS/D REV. 1 ...
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... The TPU control register address map occupies 512 bytes. The “Access” column in the TPU address map below indicates which registers are accessible only at the supervisor privilege level and which can be assigned to either the supervisor or user privilege level, according to the value of the SUPV bit in the TPUMCR. MC68334 MC68334TS/D REV. 1 SCHEDULER SERVICE REQUESTS CONTROL T2CLK ...
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... HOST SEQUENCE REGISTER 1 (HSQR1) HOST SERVICE REQUEST REGISTER 0 (HSRR0) HOST SERVICE REQUEST REGISTER 1 (HSRR1) CHANNEL PRIORITY REGISTER 0 (CPR0) CHANNEL PRIORITY REGISTER 1 (CPR1) CHANNEL INTERRUPT STATUS REGISTER (CISR) LINK REGISTER (LR) SERVICE GRANT LATCH REGISTER (SGLR) DECODED CHANNEL NUMBER REGISTER (DCNR MC68334 MC68334TS/D REV. 1 ...
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... PAC — For input capture, PAC specifies the edge transition to be detected. For output comparison, PAC specifies the logic level to be output when a match occurs. TBS — Specifies channel direction (input or output) and assigns a time base to the input capture and output compare functions of the channel. MC68334 MC68334TS/D REV ...
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... AA — — BA — — CA — — DA — — MC68334 MC68334TS/D REV. 1 ...
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... The CPU need only write a desired position, and the TPU accelerates, slews, and decelerates the motor to the required position. Full and half step support is provided for two-phase mo- tors. In addition, a slew rate parameter allows fine control of the terminal running speed of the motor independent of the acceleration table. MC68334 MC68334TS/D REV ...
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... The function supports detection or generation of even, odd, and no parity. Baud rate is freely programmable and can be higher than 100 Kbaud. Eight bidirec- tional UART channels running in excess of 9600 baud could be implemented on the TPU. 56 MC68334 MC68334TS/D REV. 1 ...
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... TCR1 is clocked from the output of a prescaler. The prescaler's input is the internal TPU system clock divided by either 4 or 32, depending on the value of the PSCK bit. The prescaler divides this input Channels using TCR1 have the capability to resolve down to the TPU system clock divided by 4. MC68334 MC68334TS/D REV ...
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... Divide By Internal Clock Divided CSEL TCR1 MUX TPU PRE BLOCK 1 PSCK = 1 Number of Rate at Clocks 16 MHz 4 250 ns 8 500 External Clock Divided MC68334 MC68334TS/D REV. 1 ...
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... CIBV field specifies the most significant nibble of all 16 TPU channel interrupt vector numbers. The low- er nibble of the TPU interrupt vector number is determined by the channel number on which the interrupt occurs. MC68334 MC68334TS/D REV – – B T2C FILTER BIT T2CG CONTROL BIT ...
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... $YFFE0C CHANNEL12 $YFFE0E CHANNEL8 $YFFE10 CHANNEL4 $YFFE12 CHANNEL0 MC68334 MC68334TS/D REV ...
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... RESET CPR1 — Channel Priority Register RESET MC68334 MC68334TS/D REV ...
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... SGLR — Service Grant Latch Register DCNR — Decoded Channel Number Register TCR — Test Configuration Register 62 Service Guaranteed Time Slots Disabled — Low 4 out of 7 Middle 2 out of 7 High 1 out of 7 $YFFE04 $YFFE06 $YFFE22 $YFFE24 $YFFE26 $YFFE02 MC68334 MC68334TS/D REV. 1 ...
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... The ADC bus interface unit (ABIU) contains logic necessary to interface the ADC to the intermodule bus. The ADC is designed to act as a slave device on the bus. The interface must respond with appro- priate bus cycle termination signals and supply appropriate interface timing to the other submodules. MC68334 MC68334TS/D REV ...
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... PORT ADA DATA REGISTER RESULT 3 RESULT 4 RESULT 5 RESULT 6 RESULT 7 CLK SELECT/ PRESCALE ADC BUS INTERFACE UNIT INTERMODULE BUS (IMB) V DDA V SSA SUPPLY V RH REFERENCE V RL AN6/PADA6 AN5/PADA5 AN4/PADA4 AN3/PADA3 AN2/PADA2 AN1/PADA1 AN0/PADA0 INTERNAL V RH CONNECTIONS V RL ADC BLOCK 7CHAN MC68334 MC68334TS/D REV. 1 ...
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... S/U $YFF73A S/U $YFF73C S/U $YFF73E Y = M111, where M is the logic state of the MM bit in the SIMCR MC68334 MC68334TS/D REV. 1 Table 27 ADC Module Address Map 15 ADC MODULE CONFIGURATION REGISTER (ADCMCR) ADC FACTORY TEST REGISTER (ADTEST) (RESERVED) PORT ADA DATA (PORTADA) (RESERVED) ADC CONTROL 0 (ADCTL0) ...
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... NOT USED SUPV 0 FRZ Response 00 Ignore FREEZE 01 Reserved 10 Finish conversion, then freeze 11 Freeze immediately $YFF700 NOT USED $YFF702 $YFF706 PORT ADA DATA Reflects state of the input pins MC68334 MC68334TS/D REV. 1 ...
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... System clock is divided by the PRS value plus one, then sent to the divide-by-two circuit, as shown in the following table. Maximum ADC clock rate is 2 MHz. Reset value of PRS is a divisor value of eight, resulting in a nominal 2-MHz ADC clock. MC68334 MC68334TS/D REV ...
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... The bits in this field are used to select an input or block of inputs for A/D conversion. The following table summarizes the operation of S8CM and CD:CA when MULT is cleared (single chan- nel mode). Number of conversions per channel is determined by SCAN SCAN MULT 0 $YFF70C S8CM MC68334 MC68334TS/D REV. 1 ...
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... Since the ADC in the MCU has only seven external analog inputs, AN7 is connected to V MC68334 MC68334TS/D REV Input 0 AN0 1 AN1 0 AN2 1 AN3 0 AN4 1 AN5 0 AN6 1 AN7* 0 Reserved 1 Reserved 0 Reserved ...
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... RH – RL Test/Reserved Result Register RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 RSLT0 RSLT1 RSLT2 RSLT3 RSLT4 RSLT5 RSLT6 RSLT7 RSLT0 RSLT1 RSLT2 RSLT3 RSLT4 RSLT5 RSLT6 RSLT7 . SSA MC68334 MC68334TS/D REV. 1 ...
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... Bits [5:0] always return zero when read. LJURR — Unsigned Left-Justified Format Conversion result is unsigned left-justified data. Bits [15:6] are used for 10-bit resolution, bits [15:8] are used for 8-bit resolution (bits [7:6] are zero). Bits [5:0] always return zero when read. MC68334 MC68334TS/D REV ...
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... RESET TPURAM MODULE CONFIGURATION REGISTER (TRAMMCR) TPURAM TEST REGISTER (TRAMTST) TPURAM BASE ADDRESS REGISTER (TRAMBAR) NOT USED RASP normal operation. DD STBY 7 $YFFB00 NOT USED MC68334 MC68334TS/D REV ...
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... If reset occurs during the first word access of a long-word operation, only the first word access will be completed. If reset occurs during the second word access of a long word operation, the entire access will be completed. Data being read from or written to the RAM may be corrupted by asynchronous reset. MC68334 MC68334TS/D REV ...
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... Expanded and revised SIM section. Added new information to 3.3 System Clock, 3.5 Chip Selects, 3.7 Resets, and 3.8 Interrupts. Page 72-74 Revised Standby RAM with TPU Emulation section to include details of array map- ping to upper half of 2-Kbyte address block. 74 falls below V during stop mode, internal circuitry switch- DD STBY MC68334 MC68334TS/D REV. 1 ...
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... MC68334 MC68334TS/D REV ...
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