VSC7126 Vitesse Semiconductor Corp., VSC7126 Datasheet
VSC7126
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VSC7126 Summary of contents
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... MHz TTL Reference Clock General Description The VSC7126 is a full-speed Fibre Channel Transceiver optimized for Host Adapter and other space- con- strained applications. It accepts two 10-bit 8B/10B encoded transmit characters, latches them on the rising edge of TBC and serializes the data onto the TX+/- PECL differential outputs at a baud rate which is twenty times the TBC frequency ...
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... PLL which does not require any external components. Serializer: The VSC7126 accepts TTL input data as two parallel 10 bit characters on the T0:19 bus which is latched into the input latch on the rising edge of TBC. This data will be serialized and transmitted on the TX PECL dif- ferential outputs at a baud rate of twenty times the frequency of the TBC input, with bit T0 transmitted first. ...
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... RBC(0). If serial input data is not present, or does not meet the required baud rate, the VSC7126 will continue to produce a recovered clock so that downstream logic may continue to function. In the absence of a signal, the RBC(0)/RBC(1) output clocks will immediately lock to the TBC reference clock ...
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... Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION K28.5 TChar TChar TChar TChar TChar PC K28.5 TChar TChar PC PC TChar TChar TChar VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC7126 TChar TChar TChar K28.5 TChar TChar TChar TChar G52148-0, Rev. 4.3 3/4/99 ...
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... Datasheet VSC7126 AC Characteristics TBC T0:19 Data Valid 20 Bit Data Table 1: Transmit AC Characteristics Parameters Description T0:19 Setup time to the T 1 rising edge of TBC T0:19 hold time after the T 2 rising edge of TBC T ,T TX+/TX- rise and fall time SDR SDF Latency from rising edge T of TBC to T0 appearing on ...
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... VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC7126 Data Valid Units Conditions Measured between the 1.4V ns. point of RBC(0) and a valid level of R0:19 or COM_DET. All outputs ns. driving 10pF load. Nominal delay is 20 bit ps. times. Tested on sample basis ...
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... Datasheet VSC7126 TBC Table 3: Reference Clock Requirements Parameters Description FR Frequency Range FO Frequency Offset T ,T Pulse Width, Low / High TBC duty cycle T ,T TBC rise and fall time RCR RCF Total jitter tolerance REFCLK G52148-0, Rev. 4.3 3/4/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 ...
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... VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC7126 Units Conditions — - 2200 – 2 2200 – 2 3200 mV 5 ...
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... Datasheet VSC7126 Figure 7: Parametric Measurement Information Serial Input Rise and Fall Time T r Receiver Input Eye Diagram Jitter Tolerance Mask Serial Output Load G52148-0, Rev. 4.3 3/4/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION TTL Input and Output Rise and Fall Time ...
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... VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC7126 Trigger Digitizing Scope Trigger Digitizing Scope Deterministic jitter (DJ) mea- surements performed according to Fibre Channel 4.3 Annex A, Test Methods, Section A.4.3. Measure time of all the 50% points of all ten transitions ...
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... Datasheet VSC7126 Input Structures INPUT INPUT INPUT G52148-0, Rev. 4.3 3/4/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Figure 9: Input Structures V +3 Current Limit R R GND TBC and TTL Inputs +3.3 V All Resistors 3.3K GND High Speed Differential Input ...
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... PLL. Transmitter Serial Outputs. These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is HIGH, TX+ is HIGH and TX- is LOW. VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC7126 INPUTS - TTL INPUT - TTL OUTPUTS - Differential PECL (AC Coupling recommended) G52148-0, Rev. 4.3 ...
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... Datasheet VSC7126 Pin # Name 65,63,59,57, 55,52,50,48, 45,43,64,62, R0:19 58,56,54,51, 49,47,44,42 34 EWRAP 70 RX+ 69 RX- 39 RBC(0) 38 RBC(1) 27 EN_CDET 37 COMDET 35 TXEN# 66 LUNUSE 26 TEST1 28 TEST2 29 TEST3 1,21,30,68,72 VSS 40,41,60,61 VSST 74 VSSA 7,13,25,32,33, VDD 67,71,75 36,46,53 VDDT 76,80 VDDP 73 VDDA 78 N/C G52148-0, Rev. 4.3 3/4/99 741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION Description Receive Data Bus, Bits 0 thru 19 20-bit received character ...
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... Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896 VITESSE SEMICONDUCTOR CORPORATION 80-pin PQFP Package Drawing 0.30 RAD. TYP 0.20 RAD. TYP. A 0.25 0° - 8° 0.17 MAX. J VITESSE SEMICONDUCTOR CORPORATION Datasheet VSC7126 Item 14 mm Tolerance A 2.35 MAX D 2.00 +0.10/-0.05 E 0.30 ±.05 F 17.20 ±.25 G 14.00 ±.10 H 17.20 ± ...
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... Datasheet VSC7126 Package Thermal Characteristics The VSC7126 is packaged PQFP with an integrated heat spreader. These packages use indus- try-standard EIAJ footprints, but have been enhanced to improve thermal dissipation. The construction of the packages is as shown in Figure 11. Figure 11: Package Cross Section - 14 mm package ...
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... Channel Transceiver Ordering Information The order number for this product is formed by a combination of the device number, and package type. Device Type VSC7126: 1.0625 Gbps Transceiver Package Style QX: 80-pin PQFP Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products, specifications or other information at any time without prior notice ...