AT90S8515 ATMEL Corporation, AT90S8515 Datasheet

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AT90S8515

Manufacturer Part Number
AT90S8515
Description
8-bit microcontroller with 8K bytes in-system programmable flash, 2.7-6.0V
Manufacturer
ATMEL Corporation
Datasheet
Features
Utilizes the AVR
AVR – High-performance and Low-power RISC Architecture
Data and Nonvolatile Program Memory
Peripheral Features
Special Microcontroller Features
Specifications
Power Consumption at 4 MHz, 3V, 25°C
I/O and Packages
Operating Voltages
Speed Grades
– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
– 8K Bytes of In-System Programmable Flash
– 512 Bytes of SRAM
– 512 Bytes of In-System Programmable EEPROM
– Programming Lock for Flash Program and EEPROM Data Security
– One 8-bit Timer/Counter with Separate Prescaler
– One 16-bit Timer/Counter with Separate Prescaler
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– Programmable Serial UART
– Master/Slave SPI Serial Interface
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
– Active: 3.0 mA
– Idle Mode: 1.0 mA
– Power-down Mode: <1 µA
– 32 Programmable I/O Lines
– 40-lead PDIP, 44-lead PLCC and TQFP
– 2.7 - 6.0V for AT90S8515-4
– 4.0 - 6.0V for AT90S8515-8
– 0 - 4 MHz for AT90S8515-4
– 0 - 8 MHz for AT90S8515-8
Endurance: 1,000 Write/Erase Cycles
Endurance: 100,000 Write/Erase Cycles
Compare, Capture Modes and Dual 8-, 9-, or 10-bit PWM
®
RISC Architecture
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT90S8515
Rev. 0841G–09/01
1

Related parts for AT90S8515

AT90S8515 Summary of contents

Page 1

... Programmable I/O Lines – 40-lead PDIP, 44-lead PLCC and TQFP • Operating Voltages – 2.7 - 6.0V for AT90S8515-4 – 4.0 - 6.0V for AT90S8515-8 • Speed Grades – MHz for AT90S8515-4 – MHz for AT90S8515-8 8-bit Microcontroller with 8K Bytes In-System Programmable Flash AT90S8515 Rev. 0841G–09/01 ...

Page 2

... Pin Configurations AT90S8515 2 0841G–09/01 ...

Page 3

... Description Block Diagram 0841G–09/01 The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S8515 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. ...

Page 4

... The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not active. Port B also serves the functions of various special features of the AT90S8515 as listed on page 66. Port 8-bit bi-directional I/O port with internal pull-up resistors. The Port C output buffers can sink 20 mA ...

Page 5

... The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not active. Port D also serves the functions of various special features of the AT90S8515 as listed on page 73. Reset input. A low level on this pin for more than 50 ns will generate a reset, even if the clock is not running ...

Page 6

... Crystal Oscillator AT90S8515 6 XTAL1 and XTAL2 are input and output, respectively inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3. ...

Page 7

... The ALU supports arithmetic and logic functions between registers or between a con- stant and a register. Single register operations are also executed in the ALU. Figure 4 shows the AT90S8515 AVR RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations ...

Page 8

... AT90S8515 8 Figure 4. The AT90S8515 AVR RISC Architecture Program Counter Program Memory Instruction Register Instruction Decoder Control Lines A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a sepa- rate interrupt vector in the interrupt vector table at the beginning of the program memory ...

Page 9

... Figure 5. Memory Maps Program Memory Program FLASH (4K x 16) AT90S8515 Data Memory $000 32 Gen. Purpose Working Registers $001F 64 I/O Registers Internal SRAM (512 x 8) External SRAM (0 - 64K x 8) $FFF $0000 $0020 $005F $0060 $025F $0260 $FFFF 9 ...

Page 10

... General-purpose Register File X-register, Y-register and Z-register AT90S8515 10 Figure 6 shows the structure of the 32 general-purpose working registers in the CPU. Figure 6. AVR CPU General-purpose Working Registers 7 General Purpose Working Registers All the register operating instructions in the instruction set have direct and single-cycle access to all registers. The only exception are the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the LDI instruction for load immediate constant data ...

Page 11

... Since all instructions are 16- or 32-bit words, the Flash is organized 16. The Flash memory has an endurance of at least 1000 write/erase cycles. The AT90S8515 Program Counter (PC bits wide, thus addressing the 4096 program memory addresses. See page 86 for a detailed description of Flash data downloading. ...

Page 12

... SRAM Data Memory – Internal and External AT90S8515 12 Figure 8 shows how the AT90S8515 SRAM memory is organized. Figure 8. SRAM Organization Register File … R29 R30 R31 I/O Registers $00 $01 $02 … $3D $3E $3F The lower 608 data memory locations address the Register file, the I/O memory and the internal data SRAM ...

Page 13

... X, Y and Z are decremented and incremented. The 32 general-purpose working registers, 64 I/O registers, the 512 bytes of internal data SRAM, and the 64K bytes of optional external data SRAM in the AT90S8515 are all accessible through all these addressing modes. See the next section for a detailed description of the different addressing modes. ...

Page 14

... Register Direct, Two Registers Rd and Rr I/O Direct Data Direct AT90S8515 14 Figure 10. Direct Register Addressing, Two Registers Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). Figure 11. I/O Direct Addressing Operand address is contained in six bits of the instruction word the destination or source register address ...

Page 15

... Figure 13. Data Indirect with Displacement Operand address is the result of the Y- or Z-register contents added to the address con- tained in six bits of the instruction word. Figure 14. Data Indirect Addressing Operand address is the contents of the X-, Y-, or the Z-register. Figure 15. Data Indirect Addressing with Pre-decrement AT90S8515 15 ...

Page 16

... Data Indirect with Post- increment Constant Addressing Using the LPM Instruction AT90S8515 16 The X-, Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-, Y-, or the Z-register. Figure 16. Data Indirect Addressing with Post-increment The X-, Y-, or the Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or the Z-register prior to incrementing ...

Page 17

... Program execution continues at address The relative address k is -2048 to 2047. The AT90S8515 contains 512 bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 44, specifying the EEPROM address registers, the EEPROM data register and the EEPROM control register ...

Page 18

... AT90S8515 18 Figure 20. The Parallel Instruction Fetches and Instruction Executions T1 System Clock Ø 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 21 shows the internal timing concept for the register file single clock cycle an ALU operation using two register operands is executed and the result is stored back to the destination register ...

Page 19

... I/O Memory 0841G–09/01 The I/O space definition of the AT90S8515 is shown in Table 1. Table 1. AT90S8515 I/O Space Address Hex Name Function $3F ($5F) SREG Status Register $3E ($5E) SPH Stack Pointer High $3D ($5D) SPL Stack Pointer Low $3B ($5B) GIMSK General Interrupt Mask register $3A ($5A) GIFR General Interrupt Flag Register ...

Page 20

... Note: Reserved and unused locations are not shown in the table. All AT90S8515 I/Os and peripherals are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general-pur- pose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...

Page 21

... This must be handled by software. The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S8515 supports external SRAM, all 16 bits are used. Bit ...

Page 22

... Handling AT90S8515 22 The AT90S8515 provides 12 different interrupt sources. These interrupts and the sepa- rate reset vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits that must be set (one) together with the I-bit in the Status Register in order to enable the interrupt. ...

Page 23

... SPL,r16 $011 <instr> … … … The AT90S8515 has three sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). POT • External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns. • ...

Page 24

... Power-on Reset AT90S8515 24 The user can select the start-up time according to typical oscillator start-up. The number of WDT oscillator cycles used for each time-out is shown in Table 4. The frequency of the Watchdog Oscillator is voltage-dependent as shown in “Typical Characteristics” on page 95. Table 4. Number of Watchdog Oscillator Cycles ...

Page 25

... Refer to page 42 for details on operation of the Watchdog. TOUT Figure 27. Watchdog Reset during Operation The AT90S8515 has two 8-bit interrupt mask control registers; GIMSK (General Inter- rupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register). When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter- rupts are disabled ...

Page 26

... INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program mem- ory address $001. See also “External Interrupts”. • Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT90S8515 and always read as zero. Bit 7 6 ...

Page 27

... Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $007) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register (TIFR). • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT90S8515 and always reads zero. AT90S8515 5 4 ...

Page 28

... TOV0 is cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0 (Ti mer /Counter erfl ow Inte rr upt Enabl e) and TOV one ), the Timer/Counter0 Overflow interrupt is executed. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT90S8515 and always reads zero ...

Page 29

... Bit 6 – SRW: External SRAM Wait State When the SRW bit is set (one), a one-cycle wait state is inserted in the external data SRAM access cycle. When the SRW bit is cleared (zero), the external data SRAM access is executed with the normal three-cycle scheme. See Figure 43 and Figure 44. AT90S8515 ...

Page 30

... AT90S8515 30 • Bit 5 – SE: Sleep Enable The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP instruction is executed. To avoid the MCU entering the Sleep Mode, unless it is the pro- grammer’s purpose recommended to set the Sleep Enable (SE) bit just before the execution of the SLEEP instruction. • ...

Page 31

... INT0 or INT1 can wake up the MCU. Note that when a level-triggered interrupt is used for wake-up from power-down, the low level must be held for a time longer than the reset delay Time-out period t wise, the MCU will fail to wake up. AT90S8515 . Other- TOUT 31 ...

Page 32

... Timer/Counter0 AT90S8515 32 The AT90S8515 provides two general-purpose Timer/Counters – one 8-bit T/C and one 16-bit T/C. The Timer/Counters have individual prescaling selection from the same 10- bit prescaling timer. Both Timer/Counters can either be used as a timer with an internal clock time base counter with an external pin connection that triggers the counting ...

Page 33

... Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S8515 and always read as zero. • Bits – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0 The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0. ...

Page 34

... Timer Counter0 – TCNT0 16-bit Timer/Counter1 AT90S8515 34 The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PB0/(T0) will clock the counter even if the pin is configured as an output ...

Page 35

... Input Capture. Refer to “Analog Comparator” on page 59 for details on this. The ICP pin logic is shown in Figure 31. Figure 31. ICP Pin Schematic Diagram If the Noise Canceler function is enabled, the actual trigger condition for the capture event is monitored over four samples and all four must be equal to activate the capture flag. AT90S8515 35 ...

Page 36

... In PWM mode, these bits have a different function. Refer to Table 12 on page 40 for a detailed description. • Bits 3..2 – Res: Reserved Bits These bits are reserved bits in the AT90S8515 and always read zero. • Bits 1..0 – PWM11, PWM10: Pulse Width Modulator Select Bits 1 and 0 These bits select PWM operation of Timer/Counter1 as specified in Table 9. This mode is described on page 40 ...

Page 37

... ICP. • Bits 5, 4 – Res: Reserved Bits These bits are reserved bits in the AT90S8515 and always read zero. • Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match ...

Page 38

... AND TCNT1L Timer/Counter1 Output Compare Register – OCR1AH AND OCR1AL AT90S8515 38 The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter1, transitions on PB1/(T1) will clock the counter even if the pin is configured as an output ...

Page 39

... ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation. AT90S8515 12 11 ...

Page 40

... Timer/Counter1 in PWM Mode AT90S8515 40 The TEMP register is also used when accessing TCNT1, OCR1A and OCR1B. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program (and from interrupt routines if interrupts are allowed from within interrupt routines). ...

Page 41

... Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode, i.e executed when TOV1 is set, provided that Timer Overflow Interrupt1 and global interrupts are enabled. This also applies to the Timer Output Compare1 flags and interrupts. AT90S8515 Counter Value Compare Value PWM Output OC1X ...

Page 42

... Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the AT90S8515 and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. ...

Page 43

... Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the Watchdog Timer may not start to count from zero. To avoid unintentional MCU reset, the Watchdog Timer should be disabled or reset before changing the Watchdog Timer Prescale Select. AT90S8515 Typical Time-out Typical Time-out ...

Page 44

... Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90S8515 and will always read as zero. is likely to rise or fall slowly on power – – – – EEAR8 EEAR4 EEAR3 ...

Page 45

... The user should poll the EEWE bit before starting the read operation write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted and the result is undefined. AT90S8515 = 2.7V) has CC ...

Page 46

... Prevent EEPROM Corruption AT90S8515 46 During periods of low V , the EEPROM data can be corrupted because the supply volt- CC age is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using the EEPROM and the same design solutions should be applied ...

Page 47

... Serial Peripheral Interface – SPI 0841G–09/01 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90S8515 and peripheral devices or between several AVR devices. The AT90S8515 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • ...

Page 48

... SS Pin Functionality AT90S8515 48 Figure 35. SPI Master-slave Interconnection MSB MASTER 8-BIT SHIFT REGISTER SPI CLOCK GENERATOR The system is single-buffered in the transmit direction and double-buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received byte must be read from the SPI Data Register before the next byte has been completely shifted in ...

Page 49

... This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global interrupts are enabled. • Bit 6 – SPE: SPI Enable When the SPE bit is set (one), the SPI is enabled. This bit must be set to enable any SPI operations. AT90S8515 ...

Page 50

... Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT90S8515 and will always read as zero. The SPI interface on the AT90S8515 is also used for program memory and EEPROM downloading or uploading. See page 86 for serial programming and verification. SCK Frequency ...

Page 51

... The SPI Data Register is a read/write register used for data transfer between the regis- ter file and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. AT90S8515 ...

Page 52

... UART Data Transmission AT90S8515 52 The AT90S8515 features a full duplex (separate receive and transmit registers) Univer- sal Asynchronous Receiver and Transmitter (UART). The main features are: • Baud Rate Generator that can Generate a large Number of Baud Rates (bps) • High Baud Rates at Low XTAL Frequencies • ...

Page 53

... PD1 pin can be used for general I/O. When TXEN is set, the UART Transmitter will be connected to PD1, which is forced output pin regardless of the setting of the DDD1 bit in DDRD. Figure 39 shows a block diagram of the UART Receiver. Figure 39. UART Receiver AT90S8515 53 ...

Page 54

... AT90S8515 54 The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical “0” will be interpreted as the falling edge of a start bit and the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample ...

Page 55

... UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt rou- tine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready. • Bit 4 – FE: Framing Error This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incom- ing character is zero. AT90S8515 LSB ...

Page 56

... Receiver Shift register. The OR bit is buffered, which means that it will be set once the valid data still in UDRE is read. The OR bit is cleared (zero) when data is received and transferred to UDR. • Bits 2..0 – Res: Reserved Bits These bits are reserved bits in the AT90S8515 and will always read as zero. Bit 7 6 ...

Page 57

... UBRR settings in Table 17. UBRR values that yield an actual baud rate dif- fering less than 2% from the target baud rate are boldface in the table. However, using baud rates that have more than 1% error is not recommended. High error ratings give less noise immunity. AT90S8515 ...

Page 58

... UBRR= 95 9600 UBRR= 47 14400 UBRR= 31 19200 UBRR= 23 28800 UBRR= 15 38400 UBRR= 11 57600 UBRR= 7 76800 UBRR= 5 115200 UBRR= 3 UART BAUD Rate Register – UBRR AT90S8515 58 1.8432 MHz %Error 0.2 UBRR= 47 0.0 UBRR= 0.2 UBRR= 23 0.0 UBRR= 7.5 UBRR= 11 0.0 UBRR= 7.8 UBRR= 7 0.0 UBRR= 7.8 UBRR= 5 0.0 UBRR= 7.8 UBRR= 3 0.0 UBRR= 22 ...

Page 59

... ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. • Bit 6 – Res: Reserved Bit This bit is a reserved bit in the AT90S8515 and will always read as zero. • Bit 5 – ACO: Analog Comparator Output ACO is directly connected to the comparator output. ...

Page 60

... Interface to External SRAM AT90S8515 60 using the SBI or CBI instruction, ACI will be cleared if it has become set before the operation. • Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Ana- log Comparator interrupt is activated. When cleared (zero), the interrupt is disabled. • ...

Page 61

... Figure 42. External SRAM Connected to the AVR Port A ALE AVR Port Figure 43. External Data SRAM Memory Cycles without Wait State T1 System Clock Ø ALE Address [15..8] Prev. Address Data/Address [7..0] Prev. Address WR Data/Address [7..0] Prev. Address RD AT90S8515 D[7: A[7:0] G A[15: Address Address Data Address Data SRAM Address Address ...

Page 62

... AT90S8515 62 Figure 44. External Data SRAM Memory Cycles with Wait State T1 System Clock Ø ALE Address [15..8] Prev. Address Data/Address [7..0] Prev. Address WR Data/Address [7..0] Prev. Address Address Address Data Address Data T4 Addr. Addr. 0841G–09/01 ...

Page 63

... PAn, general I/O pin: The DDAn bit in the DDRA register selects the direction of this pin. If DDAn is set (one), PAn is configured as an output pin. If DDAn is cleared (zero), PAn is configured as an input pin. If PORTAn is set (one) when the pin is configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the AT90S8515 ...

Page 64

... Port A Schematics AT90S8515 64 PORTAn has to be cleared (zero) or the pin has to be configured as an output pin. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not active.. Table 19. DDAn Effects on Port A Pins DDAn PORTAn I/O Pull- Input ...

Page 65

... N/A N/A The Port B Input Pins address (PINB) is not a register; this address enables access to the physical value on each Port B pin. When reading PORTB, the Port B Data Latch is read and when reading PINB, the logical values present on the pins are read. AT90S8515 PORTB4 ...

Page 66

... Port B as General Digital I/O Alternate Functions of Port B AT90S8515 66 All eight pins in Port B have equal functionality when used as digital I/O pins. PBn, general I/O pin: The DDBn bit in the DDRB register selects the direction of this pin. If DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin ...

Page 67

... Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 46. Port B Schematic Diagram (Pins PB0 and PB1) MOS PULL- UP PBn WP: WRITE PORTB WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB n: 0,1 AT90S8515 RD RESET DDBn C WD RESET PORTBn TIMERn CLOCK ...

Page 68

... AT90S8515 68 Figure 47. Port B Schematic Diagram (Pins PB2 and PB3) Figure 48. Port B Schematic Diagram (Pin PB4) MOS PULL- UP PB4 WRITE PORTB WP: WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN RD: READ DDRB SPI MASTER ENABLE MSTR: SPE: SPI ENABLE RD RESET Q D DDB4 ...

Page 69

... MASTER SELECT Figure 50. Port B Schematic Diagram (Pin PB6) MOS PULL- UP PB6 WRITE PORTB WP: WRITE DDRB WD: READ PORTB LATCH RL: READ PORTB PIN RP: READ DDRB RD: SPI ENABLE SPE: MASTER SELECT MSTR AT90S8515 RD RESET DDB5 C WD RESET PORTB5 MSTR SPE ...

Page 70

... Port C Port C Data Register – PORTC AT90S8515 70 Figure 51. Port B Schematic Diagram (Pin PB7) MOS PULL- UP PB7 WRITE PORTB WP: WD: WRITE DDRB RL: READ PORTB LATCH RP: READ PORTB PIN READ DDRB RD: SPE: SPI ENABLE MSTR MASTER SELECT Port 8-bit bi-directional I/O port. Three I/O memory address locations are allo- cated for the Port C, one each for the Data Register – ...

Page 71

... Port C pins are tri-stated when a reset condition becomes active, even if the clock is not active. Table 22. DDCn Effects on Port C Pins DDCn PORTCn I Input 0 1 Input 1 0 Output 1 1 Output Note: n: 7…0, pin number AT90S8515 DDC4 DDC3 DDC2 DDC1 R/W R/W R/W R ...

Page 72

... Port C Schematics Port D AT90S8515 72 Note that all port pins are synchronized. The synchronization latch is, however, not shown in the figure. Figure 52. Port C Schematic Diagram (Pins PC0 - PC7) Port 8-bit bi-directional I/O port with internal pull-up resistors. Three I/O memory address locations are allocated for the Port D, one each for the Data Register – ...

Page 73

... Timer/Counter1 compare matches. The PD5 pin has to be configured as an output (DDD5 set [one]) to serve this function. See the Timer/Counter1 description for further details and how to enable the output. The OC1A pin is also the output pin for the PWM mode timer function. AT90S8515 ...

Page 74

... Port D Schematics AT90S8515 74 • INT1 – Port D, Bit 3 INT1: External Interrupt source 1. The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source. • INT0 – Port D, Bit 2 INT0: External Interrupt source 0. The PD2 pin can serve as an external interrupt source to the MCU ...

Page 75

... PULL- UP PD1 WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD TXD: UART TRANSMIT DATA UART TRANSMIT ENABLE TXEN: Figure 55. Port D Schematic Diagram (Pins PD2 and PD3) AT90S8515 RD RESET DDD1 C WD RESET PORTD1 TXEN ...

Page 76

... AT90S8515 76 Figure 56. Port D Schematic Diagram (Pin PD4) Figure 57. Port D Schematic Diagram (Pin PD5) 0841G–09/01 ...

Page 77

... Figure 58. Port D Schematic Diagram (Pin PD6) Figure 59. Port D Schematic Diagram (Pin PD7) AT90S8515 77 ...

Page 78

... EEPROM AT90S8515 78 The AT90S8515 MCU provides two Lock bits that can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 25. The Lock bits can only be erased with the Chip Erase command. Table 25. Lock Bit Protection Modes ...

Page 79

... This section describes how to parallel program and verify Flash program memory, EEPROM data memory, Lock bits and Fuse bits in the AT90S8515. In this section, some pins of the AT908515 are referenced by signal names describing their function during parallel programming. See Figure 60 and Table 27. Pins not described in Table 27 are referenced by pin names ...

Page 80

... Enter Programming Mode AT90S8515 80 Table 27. Pin Name Mapping Signal Name in Programming Mode Pin Name BSY RDY/ PD1 OE PD2 WR PD3 BS PD4 XA0 PD5 XA1 PD6 DATA PB7-0 Table 28. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS) ...

Page 81

... Wait until RDY/BSY goes high to program the next byte. (See Figure 61 for signal waveforms.) F: Load Data High Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data high byte ($00 - $FF). 3. Give XTAL1 a positive pulse. This loads the data high byte. G: Write Data High Byte AT90S8515 81 ...

Page 82

... AT90S8515 82 1. Set BS to “1”. This selects high data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. (See Figure 62 for signal waveforms.) The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered: • ...

Page 83

... The programming algorithm for the EEPROM data memory is as follows (refer to “Pro- gramming the Flash” for details on command, address and data loading Load Command “0001 0001”. 2. (AT90S8515 only) B: Load Address High Byte ($00 - $01 Load Address Low Byte ($00 - $FF Load Data Low Byte ($00 - $FF). ...

Page 84

... Programming the Lock Bits Reading the Fuse and Lock Bits Reading the Signature Bytes AT90S8515 84 Bit 5 = SPIEN Fuse bit Bit 0 = FSTRT Fuse bit Bit “1”. These bits are reserved and should be left unprogrammed (“1”). 3. Give -wide negative pulse to execute the programming, ...

Page 85

... OHDZ t WR Pulse Width Low for Chip Erase WLWH_CE WR Pulse Width Low for Programming the Fuse t Bits WLWH_PFB Notes: 1. Use t for Chip Erase and t WLWH_CE held longer than t WLWH AT90S8515 t XLWL t t XLDX BVWL t WLWH t WHRL t XLOL t OLDV = 25 ° C ± 10%, V ...

Page 86

... Low: > 2 XTAL1 clock cycles High: > 2 XTAL1 clock cycles When writing serial data to the AT90S8515, data is clocked on the rising edge of SCK. When reading data from the AT90S8515, data is clocked on the falling edge of SCK. See Figure 65, Figure 66 and Table 33 on page 89 for timing details. ...

Page 87

... This will not work for the value $7F, so when programming this value, the user will have to wait for at least t erased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. AT90S8515 value. before transmitting the next instruction. WD_PROG value ...

Page 88

... The signature bytes are not readable in lock mode 3, i.e., both Lock bits programmed address high bits b = address low bits – Low byte, 1 – High Byte o = data out i = data don’t care 1 = Lock bit Lock bit 2 AT90S8515 88 Figure 65. Serial Programming Waveforms Instruction Format Byte 2 Byte 3 0101 0011 xxxx xxxx 100x xxxx ...

Page 89

... SCK Low to MISO Valid SLIV Table 34. Minimum Wait Delay after the Chip Erase Instruction Symbol 3. WD_ERASE Table 35. Minimum Wait Delay after Writing a Flash or EEPROM Location Symbol 3. WD_PROG AT90S8515 t t SLSH SHOX t SHSL t SLIV = -40 ° ° Min Typ = 2.7 - 4.0V) ...

Page 90

... I/O Pin Pull-up Resistor I/O Power Supply Current I CC (5) Power-down mode Analog Comparator V ACIO Input Offset Voltage Analog Comparator I ACLK Input Leakage Current Analog Comparator t ACPD Propagation Delay AT90S8515 90 *NOTICE: + 0.5V CC Condition Min (Except XTAL1) -0.5 (XTAL1) -0.5 (Except XTAL1, RESET) 0.6 V (XTAL1) 0.8 V (RESET ...

Page 91

... CC 0841G–09/01 may exceed the related specification. Pins are not guaranteed to sink current greater OL may exceed the related specification. Pins are not guaranteed to source current OH AT90S8515 = 5V 3V) under steady state 5V, 1 3V) under steady state ...

Page 92

... External Clock Drive Waveforms AT90S8515 92 Figure 67. External Clock VIH1 VIL1 Table 36. External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL Note: See “External Data Memory Timing” for a description of how the duty cycle influences the timing for the external data memory ...

Page 93

... CLCL 105.0 145.0 1.0 t CLCL 42.5 82.5 0.5 t CLCL 60.0 60.0 70.0 0.0 0.0 105.0 1.0 t CLCL 27.5 0.5 t CLCL 0.0 0.0 95.0 1.0 t CLCL 42.5 0.5 t CLCL 8 MHz Oscillator Min Max Min 0.0 195.0 230.0 2.0 t CLCL 220.0 2.0 t CLCL 167.5 1.5 t CLCL AT90S8515 Variable Oscillator Max Unit 8.0 MHz (1) - 30.0 ns (1) - 40.0 ns ( ( 30.0 ns ( 20.0 1 20.0 ns CLCL (2) (2) - 20.0 0 20.0 ns CLCL ns 1 55.0 ns CLCL ns - 20.0 ...

Page 94

... WR Pulse Width WLWH Notes: 1. This assumes 50% clock duty cycle. The half-period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half-period is actually the low time of the external clock, XTAL1. AT90S8515 94 4 MHz Oscillator Min Max Min ...

Page 95

... Timer enabled and Power-down mode with Watchdog Timer disabled represents the dif- ferential current drawn by the Watchdog Timer. Figure 69. Active Supply Current vs. Frequency ACTIVE SUPPLY CURRENT vs. FREQUENCY AT90S8515 = operating voltage and f = average 25˚ 3. 3. ...

Page 96

... AT90S8515 96 Figure 70. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs 2.5 3 3.5 Figure 71. Idle Supply Current vs. Frequency IDLE SUPPLY CURRENT vs. FREQUENCY FREQUENCY = 4 MHz 4 4.5 5 5 25˚ 3. 3. 3.0V ...

Page 97

... Figure 72. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs 3.5 3 2.5 2 1 2.5 3 Figure 73. Power-down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER DISABLED 2.5 3 AT90S8515 CC cc FREQUENCY = 4 MHz 3 3 -40 C ˚ ˚ A ...

Page 98

... AT90S8515 98 Figure 74. Power-down Supply Current vs. V POWER DOWN SUPPLY CURRENT vs. V WATCHDOG TIMER ENABLED 140 120 100 2.5 3 3.5 Figure 75. Analog Comparator Current vs. V ANALOG COMPARATOR CURRENT vs. V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0 2 ˚ 4.5 5 5 -40 C ˚ ...

Page 99

... Common Mode Voltage (V) Figure 77. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 Common Mode Voltage (V) AT90S8515 ˚ 2.5 3 3 ˚ ...

Page 100

... AT90S8515 100 Figure 78. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT -10 0 0.5 1 1.5 2 2.5 Figure 79. Watchdog Oscillator Frequency vs. V WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 1400 1200 1000 800 600 400 200 0 2 2 ˚ ...

Page 101

... ˚ A 100 ˚ 0.5 1 1.5 Figure 81. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ˚ ˚ 0.5 1 AT90S8515 2.5 3 3.5 4 4 2.7V cc 1.5 2 2 101 ...

Page 102

... AT90S8515 102 Figure 82. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 1 Figure 83. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0 ...

Page 103

... Figure 84. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0.5 1 Figure 85. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 1 0.5 0 2.7 AT90S8515 V = 2.7V cc 1.5 2 2 ˚ 5.0 103 ...

Page 104

... AT90S8515 104 Figure 86. I/O Pin Input Hysteresis vs. V I/O PIN INPUT HYSTERESIS vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 Figure 87. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0 ˚ ˚ ˚ 1.5 V (V) OL 5.0 2 0841G–09/01 ...

Page 105

... PIND4 PIND3 SPI Data Register WCOL - - SPE DORD MSTR CPOL UART I/O Data Register TXC UDRE FE OR TXCIE UDRIE RXEN TXEN UART Baud Rate Register - ACO ACI ACIE AT90S8515 Bit 2 Bit 1 Bit SP10 SP9 SP8 SP2 SP1 SP0 - - - - - TOIE0 - - TOV0 - ...

Page 106

... Branch if T-flag Set BRTC k Branch if T-flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled AT90S8515 106 Operation Flags Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← ...

Page 107

... CLT Clear T in SREG SEH Set Half-carry Flag in SREG CLH Clear Half-carry Flag in SREG NOP No Operation SLEEP Sleep WDR Watchdog Reset 0841G–09/01 AT90S8515 Operation Flags Rd ← Rr None Rd ← K None Rd ← (X) None Rd ← (X), X ← None X ← ← (X) None Rd ← ...

Page 108

... Speed (MHz) Power Supply 4 2.7V - 6.0V 8 4.0V - 6.0V Note: Order AT90S8515A-XXX for devices with the FSTRT Fuse programmed. 44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) ...

Page 109

... Dimension in Millimeters and (Inches)* JEDEC STANDARD MS-026 ACB 0.80(0.0315) BSC 0.20(0.008) 0.09(0.004) REV. A 04/11/2001 0841G–09/01 PIN 1 ID PIN 1 0˚~7˚ 0.75(0.030) 0.45(0.018) *Controlling dimension: millimetter AT90S8515 12.25(0.482) SQ 11.75(0.462) 0.45(0.018) 0.30(0.012) 10.10(0.394) SQ 9.90(0.386) 1.20(0.047) MAX 0.15(0.006) 0.05(0.002) 109 ...

Page 110

... Plastic J-leaded Chip Carrier (PLCC) Dimensions in Milimeters and (Inches)* JEDEC STANDARD MS-018 AC 1.14(0.045) X 45˚ 0.813(0.032) 0.660(0.026) 1.27(0.050) TYP REV. A 04/11/2001 AT90S8515 110 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFY 16.70(0.656) SQ 16.50(0.650) 17.70(0.695) 17.40(0.685) 12.70(0.500) REF SQ 0.51(0.020)MAX 45˚ MAX (3X) *Controlling dimensions: Inches 0 ...

Page 111

... Demension in Millimeters and (Inches)* JEDEC STANDARD MS-011 AC 4.83(0.190)MAX SEATING PLANE 3.56(0.140) 3.05(0.120) 2.54(0.100)BSC 0.38(0.015) 0.20(0.008) REV. A 04/11/2001 0841G–09/01 52.71(2.075) 51.94(2.045) 48.26(1.900) REF 1.65(0.065) 1.27(0.050) 15.88(0.625) 15.24(0.600) 0º ~ 15º 17.78(0.700)MAX *Controlling dimension: Inches AT90S8515 PIN 1 13.97(0.550) 13.46(0.530) 0.38(0.015)MIN 0.56(0.022) 0.38(0.015) REF 111 ...

Page 112

... Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein ...

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