LTC2241 Linear Technology Corporation, LTC2241 Datasheet
LTC2241
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LTC2241 Summary of contents
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... DESCRIPTION The LTC ® 2241- 210Msps, sampling 10-bit A/D con- verter designed for digitizing high frequency, wide dynamic range signals. The LTC2241-10 is perfect for demanding communications applications with AC performance that includes 60.5dB SNR and 78dB SFDR. Ultralow jitter of 95fs RMS performance. ...
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... For more information on lead free part marking, go to: For more information on tape and reel specifi cations (Notes Power Dissipation .............................................1500mW Operating Temperature Range + 0.3V) LTC2241C-10 ........................................... 0°C to 70° 0.3V) LTC2241I-10 ........................................–40°C to 85° 0.3V) Storage Temperature Range ................... –65°C to 150°C DD TOP VIEW + 1 ...
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... Input 70MHz Input 140MHz Input 240MHz Input 10MHz Input 70MHz Input 140MHz Input 240MHz Input 10MHz Input 70MHz Input 140MHz Input 240MHz Input f = 135MHz 140MHz IN1 IN2 LTC2241-10 MIN TYP MAX UNITS ● 10 Bits ● –0.8 ±0.3 0.8 LSB ● –0.6 ±0.15 0.6 LSB ● ...
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... LTC2241-10 INTERNAL REFERENCE CHARACTERISTICS PARAMETER V Output Voltage CM V Output Tempco CM V Line Regulation CM V Output Resistance CM DIGITAL INPUTS AND DIGITAL OUTPUTS full operating temperature range, otherwise specifi cations are at T SYMBOL PARAMETER + – ENCODE INPUTS (ENC , ENC ) V Differential Input Voltage ...
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... Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) (Note 7) (Note 7) (t – (Note (Note 7) (Note 7) (t – (Note LTC2241-10 MIN TYP MAX UNITS ● 2.375 2.5 2.625 ● 2.375 2.5 2.625 V ● ...
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... LTC2241-10 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with GND and OGND wired together (unless otherwise noted) ...
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... RANGE RANGE 45 40 100 200 600 700 900 0 300 400 500 800 1000 INPUT FREQUENCY (MHz) 224110 G11 LTC2241-10 8192 Point FFT 240MHz, IN –1dB, 2V Range, LVDS Mode 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 0 20 ...
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... LTC2241-10 TYPICAL PERFORMANCE CHARACTERISTICS SFDR and SNR vs Sample Rate, 2V Range 30MHz, –1dB, IN LVDS Mode 95 90 SFDR SNR 100 150 200 SAMPLE RATE (Msps) 224110 G13 I vs Sample Rate, 5MHz Sine VDD Wave Input, –1dB 240 230 220 ...
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... Output and Input Common Mode Bias. CM Bypass to ground with 2.2μF ceramic chip capacitor. GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. LTC2241-10 selects demux CMOS DD selects offset DD selects 2’s complement DD selects 2’ ...
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... LTC2241-10 PIN FUNCTIONS (LVDS Mode) + AIN (Pins 1, 2): Positive Differential Analog Input. – AIN (Pins 3, 4): Negative Differential Analog Input. REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, 12 with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor ...
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... CLOCK DRIVER REFLB REFHA REFLA REFHB 2.2μF + – ENC ENC 0.1μF 0.1μF 1μF 1μF Figure 1. Functional Block Diagram LTC2241-10 FOURTH PIPELINED FIFTH PIPELINED ADC STAGE ADC STAGE SHIFT REGISTER AND CORRECTION CONTROL OUTPUT LOGIC DRIVERS 224110 F01 OGND LVDS SHDN M0DE ...
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... LTC2241-10 TIMING DIAGRAMS ANALOG INPUT – ENC + ENC D0-D9, OF – CLKOUT + CLKOUT ANALOG INPUT – ENC + ENC DA0-DA9, OFA CLKOUTB CLKOUTA DB0-DB9, OFB 12 LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels – – ...
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... All Outputs Are Single-Ended and Have CMOS Levels – – LTC2241- – – – 2 224110 TD03 – – – – 1 224110 TD04 224110fb 13 ...
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... SNR JITTER CONVERTER OPERATION As shown in Figure 1, the LTC2241- CMOS pipelined multi-step converter. The converter has fi ve pipelined ADC stages; a sampled analog input will result in a digitized value fi ve cycles later (see the Timing Diagram section). For optimal performance the analog inputs should be driven differentially ...
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... SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2241-10 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (C NMOS transistors. The capacitors shown attached to ...
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... Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2241-10 being driven transformer with a center tapped secondary. The secondary center tap is DC biased with V , setting the ADC input CM signal at its optimum DC level ...
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... ADC bandwidth. Reference Operation Figure 9 shows the LTC2241-10 reference circuitry consist- ing of a 1.25V bandgap reference, a difference amplifi er and switching and control circuit. The internal voltage reference can be confi gured for two pin selectable input ranges of 2V (± ...
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... HIGH REFERENCE SNR will degrade by 1.7dB. See the Typical Performance Characteristics section. Driving the Encode Inputs DIFF AMP The noise performance of the LTC2241-10 can depend on the encode signal quality as much as on the analog INTERNAL ADC input. The ENC LOW REFERENCE differentially, primarily for noise immunity from com- 224110 F09 mon mode noise sources ...
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... PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3V The lower limit of the LTC2241-10 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specifi ...
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... As with all high speed/high resolution converters, the 10 0000 0000 digital output loading can affect the performance. The digital outputs of the LTC2241-10 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an 74VCX245 CMOS latch ...
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... LOGIC LATCH OE Figure 13a. Digital Output Buffer in CMOS Mode Data Format The LTC2241-10 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3V selects offset binary output format. Connecting ...
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... HEAT TRANSFER Most of the heat generated by the LTC2241-10 is trans- ferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed ...
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... ADC precedence. The clock signals to the FPGA should have series termination at the driver to prevent high frequency noise from the FPGA disturbing the sub- LTC2241-10 strate of the clock fan-out device. If you use an FPGA as a programmable divider, you must re-time the signal using the original oscillator, and the re-timing fl ...
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... LTC2241-10 APPLICATIONS INFORMATION GND 16 GND 61 GND 64 GND ...
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... APPLICATIONS INFORMATION Silkscreen Top Layer 1 Component Side LTC2241-10 Layer 2 GND Plane Layer 3 Power/Ground Plane 25 224110fb ...
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... LTC2241-10 APPLICATIONS INFORMATION Layer 4 Power/Ground Planes Layer 5 Power/Ground Planes 26 Layer Back Solder Side Silk Screen Back, Solder Side 224110fb ...
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... EXPOSED PAD SHALL BE SOLDER PLATED 5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 6. DRAWING NOT TO SCALE PACKAGE OUTLINE 0.75 ± 0. 0.115 7.15 ± 0.10 (4-SIDES) 0.200 REF 0.00 – 0.05 LTC2241-10 BOTTOM VIEW—EXPOSED PAD TYP 63 64 0.40 ± 0. PIN 1 CHAMFER (UP64) QFN 1003 0.25 ± ...
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