ZL10353 Zarlink Semiconductor, ZL10353 Datasheet
ZL10353
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ZL10353 Summary of contents
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... PC-TV receivers • Portable applications Description The ZL10353 is a superior fourth generation fully compliant ETSI ETS300 744 COFDM demodulator that exceeds, with margin, the performance requirements of all known DVB-T digital terrestrial television standards, including Unified Nordig and DTG. Figure 1 - Block Diagram 1 Zarlink Semiconductor Inc ...
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... The ZL10353 has a wide frequency capture range able to automatically compensate for the combined offset introduced by the tuner xtal and broadcaster triple frequency offsets. An on-chip state machine controls all acquisition and tracking operations of the ZL10353 as well as controlling the tuner via a 2-wire bus. Any frequency range can be automatically scanned for digital TV channels. This mechanism ensures minimal interaction, maximum flexibility and fast acquisition - very low software overhead ...
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... Pin & Package Details 1.1 Pin Outline Figure 2 below shows the basic, non-diversity, pin functions of the ZL10353. The device can effectively be set up in seven different pin configurations, so for brevity only this version is shown. ZL10353 Figure 2 - Pin Outline 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Function Pin AGC1 42 GPP3/DvClk AGC2/GPP2/DvVal 41 IRQ/Dv4/Dv0 AGnd 29 MDO0/Dv0/ Dv1 AGnd 32 MDO1/Dv1/ Dv3 AVdd 28 MDO2/Dv2 BKERR 62 MDO3/Dv3/ Dv1 CLK1 4 MDO4/Dv4/ Dv0 CLK2/GPP0 35 MDO5 ZL10353 Function Pin SADD1 33 Vdd SADD0 34 RFLEV CVdd 35 CLK2/GPP0 Vss 36 DATA2/GPP1 PLLVdd 37 CVdd PLLGND 38 Vss XTI 39 CVdd XTO 40 Vss ...
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... MPEG Pins 47 MOSTRT 48 MOVAL (or DvVal-O) 49-53, MDO(0:4)/Dv(0:4)-O 56-58 MDO(5:7) 61 MOCLK (or DvClk-O) 62 BKERR 63 MICLK 11 STATUS (or Dv3/1) 6 IRQ (or Dv4/0) Control Pins 4 CLK1 5 DATA1 ZL10353 Function Pin Function 57 SADD4/Dv2 58 SLEEP 63 SMTEST 61 STATUS/Dv3/ Dv1 47 Vdd 48 Vdd 27 Vdd 22 Vdd Pin Description MPEG packet start MPEG/diversity data valid MPEG/diversity data bus ...
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... CVdd 59 13, 45, 54, Vdd 14, 20, Vss 25, 38, 40, 46, 55 AVdd 29, 32 AGnd 33 Vdd ZL10353 Pin Description I/O Low phase noise oscillator I O Device power down I Serial address set I Serial address set or I/O Diversity data I/O Serial address set Production test (only set low) ...
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... Functional Description A functional block diagram of the ZL10353 OFDM demodulator is shown in Figure 3. This accepts an IF analogue signal and delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing and frequency synchronization operations are all digital and there are no analogue control loops except the AGC. The frequency capture range is large enough for all practical applications ...
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... The algorithms and architectures used in the ZL10353 have been optimized to minimize power consumption. 2.1 Analogue-to-Digital Converter The ZL10353 has a high performance 10-bit analogue-to-digital converter (ADC) which can sample MHz bandwidth OFDM signal, with its spectrum centred at: • 36.17 MHz IF • ...
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... The AGC is free running during OFDM channel changes and locks to the new channel while the tuner lock is being established. This is one of the features of ZL10353 used to minimize acquisition time. A robust AGC lock mechanism is provided and the other parts of the ZL10353 begin to acquire only after the AGC has locked. 2 Baseband Conversion Sampling a 36 ...
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... This module also generates dynamic channel state information (CSI) for every carrier in every symbol. 2.11 Impulse Filtering ZL10353 contains several mechanisms to reduce the impact of impulse noise on system performance. 2.12 Transmission Parameter Signalling (TPS) An OFDM frame consists of 68 symbols and a superframe is made up of four such frames. There is a set of TPS carriers in every symbol and all these carry one bit of TPS ...
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... MPEG data can be output in parallel or serial mode. The output clock frequency is automatically chosen to present the MPEG data as uniformly spaced as possible to the transport processor. This frequency depends on the guard ratio, constellation, hierarchy and code rate. There is also an option for the data to be extracted from the ZL10353 with a clock provided by the user. ...
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... VSS VSS VDD When the ZL10353 is powered up, the RESET pin 9 should be held low for at least 50 ms after VDD has reached normal operation levels. As the RESET pin goes high, the logic levels on SADD[4:0] are latched as the 2-wire bus address. ADDR[0] is the R/W bit. ...
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... Write operation - as a slave receiver: S DEVICE W A RADD ADDRESS (n) Read operation - ZL10353 as a slave transmitter: S DEVICE R A DATA ADDRESS (reg 0) Write/read operation with repeated start - ZL10353 as a slave transmitter: S DEVICE W A RADD ADDRESS (n) 3.1.4 Primary 2-Wire Bus Timing t BUFF DATA1 CLK1 ...
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... Fall time of both CLK and DATA signals, (100 pF to ground). Set-up time for a STOP condition operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum. 2. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation. ZL10353 Symbol f CLK ...
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... If TEI_En bit is low then TEI bit will not be changed (but note that if this bit is already 1, for example, due to a channel error which has not been corrected, it will remain high at output). ZL10353 188 byte packet output 184 Transport packet bytes ...
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... MOSTRT MOVAL BKERR 3.2.3 MPEG Output Timing Maximum delay conditions: VDD = 3.0V, CVDD = 1.62V, Tamb = 80 Minimum delay conditions: VDD = 3.6V, CVDD = 1.98V, Tamb = -10 MOCLK frequency = 45.06 MHz. ZL10353 188 byte packet n Tp Figure 7 - MPEG Output Data Waveforms o C, Output load = 10pF Output load = 10pF. ...
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... Data output delay t 3.0 D Setup Time t 18.0 SU Hold Time t 1.0 H The hold time is better when MOCLKINV = 1, therefore this should be used if possible. MOCLK MDO } MOSTRT MOVAL BKERRB BKERR ZL10353 Units Minimum 1.0 10 Figure 8 - MPEG Timing - MOCLKINV = 1 Delay conditions Units Minimum 1 ...
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... Storage temperature Operating ambient temperature Junction temperature Note: Stresses exceeding these listed under absolute maximum ratings may induce failure. Exposure to absolute maximum ratings for extended periods may reduce reliability. Functionality at or above these conditions is not implied. ZL10353 Symbol Min. periphery VDD ...
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... Crystal Specification and External Clocking Parallel resonant fundamental frequency (preferred) Tolerance over operating temperature range Tolerance overall Typical load capacitance Drive level Equivalent series resistance ZL10353 Pins MDO(7:0), MOVAL, MOSTRT, MOCLK, STATUS, BKERR GPP(3:0), DATA1, AGC1, AGC2, IRQ MOSTRT, MOCLK, STATUS, BKERR ...
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... V operation - typical gm 8.736 mA/V - transconductance of amplifier at 1.8 V operation -typical Rf 2 internal feedback resistor ESR maximum equivalent series resistance of crystal - given by crystal manufacturer ( ) f fundamental frequency of crystal (Hz) ZL10353 XTI XT0 XTI C1 C2 Figure 10 - Crystal Oscillator Circuit + out ...
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... Finally the power dissipation in the crystal must be checked too high C1 and C2 must be reduced. If this is not feasible C2 alone may be reduced. Unbalancing C1 and C2 will, however, require checking if the loop gain condition is still satisfied. This must be done using Equation Note: 2 > > 0 ZL10353 ...
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... Vpp must be >100 mV recommended that differential clock signals have VCM = 1.0V. For Vpp > 400 mV a resistor of >390 or supplied to the clock sources. ZL10353 for a clock signal switching between 0 V and and 22 k resistors) must be 800 mV < VCM < CVDD and the amplitude ...
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... Application Circuit ZL10353 Figure 12 - Typical Application Circuit 23 Zarlink Semiconductor Inc. Design Manual ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...