S5H1420 Samsung, S5H1420 Datasheet
S5H1420
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S5H1420 Summary of contents
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... Samsung Electronics Co, Ltd. Note: This documentation is preliminary and is subject to change. Samsung Electronics Co, Ltd. reserves the right to do any kind of modification in this data sheet regarding hardware or software implementations without notice. Samsung Electronics Co, Ltd. Proprietary Information S5H1420 10 Jan. 2004 (Version 4.5.1) [Channel Lab ...
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... Data Sheet Update History…………………………………………………………………………...…….31 Samsung Electronics Co, Ltd. Proprietary Information S5H1420 DBS Channel Decoder for DVB-S/DSS ...
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... INTRODUCTION 1.1 Overview The S5H1420 is a single chip channel decoder IC for DBS (Digital Broadcasting System for Satellite) receiver. It consists of a multi-standard QPSK/BPSK demodulator and FEC (Forward Error Correction) decoder compliant with DVB-S and DSS standard. For multi-antenna control it provides DiSEqC1.x and 2.0 standards. ...
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... Generator I 64-LQFP Top View S5H1420 DBS Channel Decoder for DVB-S/DSS Byte De- Sync interleaver Error RS Monitor Decoder MPEG De- I/F scrambler AVSS_PLL 31 AVDD_PLL 30 DATA7 29 TEST_SEL1 28 TEST_SEL0 27 VDD25 26 ...
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... ADC Analog Input 53 ADC Bottom Reference Voltage 54 ADC Top Reference Voltage 55 Common Mode Level Voltage 60 Gain Control Output 61 Antenna Select 62 Data Transfer clock 63 LNB Voltage Select Flag 64 LNB Enable Flag 46 13 19, 26, 43 20, 27, 44, 59 S5H1420 - - 5 ...
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... Where is roll-off factor: 0.35 for DVB-S, 0.2 for DSS. Thus Timing NCO frequency word register setting is: NCO frequency word = Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS clk for =1. for = sym 2 f clk S5H1420 / ( and 16) in order ...
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... Carrier lock detector Samsung Electronics Co, Ltd. Proprietary Information is integral gain and is timing factor. t Bandwidth (BL), as follows and . /2 (± f /2). clk sampling is integral gain and is phase factor and . S5H1420 DBS Channel Decoder for DVB-S/DSS - - 7 ...
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... Forward Error Correction 3.4.1 FEC modes Since the S5H1420 is a multi-standard decoder, several combinations are possible, at different levels: v the demodulator may accept either QPSK or BPSK signals - the only impact is on the carrier algorithm choice. The algorithm choice also affects the carrier lock detector and the noise evaluation. ...
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... Energy dispersal descrambler and output energy dispersal descrambler generator The polynomial is initialized every eight blocks with the sequence 100101010000000. The sync words are unscrambled and the scrambler is reset every 8 packets. Samsung Electronics Co, Ltd. Proprietary Information 1=0 S5H1420 DBS Channel Decoder for DVB-S/DSS - - 9 ...
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... The first bit detected in a valid packet may be decoded found on the appropriate edge of BYTE_CLOCK, where SYNC = 1, ERROR = 0, VALID = 1. The following bits only require the assertion of VALID (while VALID = 1,). Outputs remain at low level in serial mode. Samsung Electronics Co, Ltd. Proprietary Information S5H1420 DBS Channel Decoder for DVB-S/DSS - - ...
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... Serial Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS No Error Uncorrectible Packet Data Parity 1/fclk DATA First bit of the packet Useful Data 1 packet Bit4 of 0x02 MPEG Data SER_SEL_MODE 1 DATA [7:0] 1 DATA[7] S5H1420 No Error Parity Parity MPEG Clock BYTE_CLK BYTE_CLK - - 11 ...
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... MPEG Clock Control - Through Register Setting, S5H1420 can control MPEG CLOCK to MCU. STB MCU Symbol Rate Symbol Rate >= 25 S5H1420 Master 59MHz Clock Sampling - Control register, 3-bit, uses Address 0x22 ( - If Control registers changes, Some blocks will be reset automatically case, Auto reset does not work, these blocks’ reset can be done manually. ...
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... The Identification Register (at Address Hex 00) gives the release number of the circuit. The content of this register at reset is presently (Hex02) 3.5.5 Sampling frequency The S5H1420 converts the analog inputs into digital 6 bit I and Q flow. The sampling frequency is f which is derived from an external reference described in Section 3.5.6 ‘Clock generation’. The maximum value of fclk is 90 MHz. ...
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... The S5H1420 complies with DiSEqC2.0. Figure illustrates a typical application of the DiSEqC mode. < Receive > The S5H1420 receives the data from LNBs using DiSEqC pin. In order to receive the data from LNBs should set the register RCV_EN to 1. The received data is stored to register set. Two control signals are available on the I DiS_RDY (Transfer Ready/Finish) and DiS_LENGTH (Message Length) ...
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... Samsung Electronics Co, Ltd. Proprietary Information 11 Periods 11 Periods Register set Empty DATA=00 Unmodulated tone burst DATA=FFor00 Note 1 xx S5H1420 DBS Channel Decoder for DVB-S/DSS Next bit Transmission of 1's Transmission of 0 b)SWITCH_CON=0 Output Continuous tone Module tone burst DiSEpC signal ...
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... CLK_CONT TONE_FREQ DIS_LENGTH DIS_RDY LNB_MESGE0 LNB_MESGE1 LNB_MESGE2 LNB_MESGE3 LNB_MESGE4 LNB_MESGE5 LNB_MESGE6 LNB_MESGE7 SLAVE_ADDR ALARM _MODE ERR_CNT_PRD ERR_CNT_L ERR_CNT_H PARITY_ERR S5H1420 DBS Channel Decoder for DVB-S/DSS bit2 bit1 bit0 0 0 DSS_DVB 0 PWR_DN I2C_RPT P 1 MODE Q_START DC_WIN PRE_TH POST_TH ...
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... I2C repeater enable, [0] I2C repeater disable. R/W Note: The master should be set this bit to “1” in order to interface with the tuner. When the master is not communicated with the tuner, this bit should be set to “0” PLL programming information R ((M+8) F )/((P+2)×2 ) out in R MHz in R/W S5H1420 - - 17 ...
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... DUMP_ACC “0” and then “1”. Window position from MSB removing DC offset. Unsigned integer R/W (0 DC_WIN 7) PWM signal is reversed R/W [1] PWM signal active low [0] PWM signal active high R/W Set to “0” R/W Set to “1” R/W PRE-AGC threshold R/W Set to “0” R/W POST-AGC threshold S5H1420 - - 18 ...
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... R/W Integral gain in the tracking mode R/W Timing loop, proportional gain (default +8 added) R/W Timing loop, integral gain LOOP_OUT [1] R/W Read PLF accumulator + PNCO LOOP_OUT [0] R/W Read PLF accumulator R/W LOOP_OUT [1] R/W Read TLF accumulator + TNCO LOOP_OUT [0] R/W Read TLF accumulator R/W S5H1420 N ) before the acquisition mode - - 19 ...
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... Phase loop lock (Carrier sync) R [1] Phase loop has locked [0] Phase loop has not locked R PRE-AGC gain level R POST-AGC gain level R DC offset of I samples R DC offset of Q samples R Reserved R Reserved Reserved Reserved R QPSK output monitoring R/W [1] Do not update DC_OFFSET Reserved S5H1420 - - 20 ...
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... Include code rate 3/4 in sync search R/W [0] Disable [1] Include code rate 2/3 in sync search R/W [0] Disable [1] Include code rate 1/2 in sync search R/W [0] Disable Parameter fix mode R/W [1] Known parameter [0] Unknown parameter Initial spectrum information R/W [1] Inv spectrum [0] Not inv spectrum Start synchronization search at code rate as follows: [0] R=1/2 [1] R=2/3 R/W [2] R=3/4 [3] R=5/6 [4] R=6/7 [5] R=7/8 S5H1420 - - 21 ...
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... R=2/3 R [2] R=3/4 [3] R=5/6 [4] R=6/7 [5] R=7/8 R/W Sync byte detector’s miss threshold Sync byte detector’s hit threshold R/W *Note: This value should be greater than 2 [1] Acquire byte sync R [0] Not acquire byte sync R Reserved [1] Viterbi decoder is in sync R [0] Viterbi decoder is out of sync S5H1420 - - 22 ...
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... When this bit is “1”, the slaver is not yet received message. The slaver is starting to receive the signal at the rising edge detection Satellite switch in tone burst mode R/W [1] Satellite B [0] Satellite A LNB control mode [0] Continuous mode R/W [1] Tone burst mode [2] DiSEqC mode [3] Reserved S5H1420 - - 23 ...
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... Samsung Electronics Co, Ltd. Proprietary Information DBS Channel Decoder for DVB-S/DSS R/W [1] Disable [0] OLF (active low) R/W [1] LNB down [0] Disable (active high) 13V/18V select register R/W [1] 18V [0] 13V LNB message contents R/W *MSB sent first on each byte R/W R/W R/W R/W R/W R/W R/W R/W RF tuner slave Address (SOC VERSION) S5H1420 - - 24 ...
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... DBS Channel Decoder for DVB-S/DSS R/W Set to “1” R/W Set to “1” Error monitoring source [0] QPSK bit errors R/W [1] Viterbi bit errors [2] Viterbi byte errors [3] Packet errors R Error counter value register (LSB 8 bits) R Error counter value register (MSB 8 bits) R Error flag for DiSEqC receive data S5H1420 - - 25 ...
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... VREF-L Value (VREF-H)-(VREF-L) CML Output V = 59MHz DD=2. 88MHz DD=2.6V F =30MHz, F =90MHz =30MHz, F =90MHz =30MHz, F =90MHz =30MHz, F =90MHz =30MHz, F =90MHz IN S S5H1420 Range Unit V +0 ºC ºC Range Unit V ºC º ºC Typ Max Unit 3.3 3.6 V 2.5 2.7 V 0.7 VDD - 2 ...
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... CLK_OUT Falling Edge f = 90M H z. Refer to Figure 9 CLK 3.5 2 CLK_OUT Falling Edge Figure 7 CLK_OUT D[7:0], D/P STR_OUT, ERROR t CKH Figure 9 CLK_OUT D[7:0], D/P STR_OUT, ERROR t CKH S5H1420 DBS Channel Decoder for DVB-S/DSS Typ Max Unit 400 CKSU ...
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... Min Pull 10% - 0.5 2.0 Pull 10% VIN = -10 0 VOL = 0.5V Normal Mode 0 Standby Mode 0 1.3 0.6 1.3 0.6 0.6 0.6 100 U U ’ 45" " " S5H1420 Typ Max Unit 0.8 V 5.5 V 5 /40 _ M_CLK f /10 _ M_CLK ...
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... ’ O ’ Samsung Electronics Co, Ltd. Proprietary Information S5H1420 DBS Channel Decoder for DVB-S/DSS ’ &’ ’ &’ ’ O ’ ...
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... Package Dimension #64 #1 0.50 NOTE: Dimensions are in millimeters. Samsung Electronics Co, Ltd. Proprietary Information 12.00 + 0.20 10.00 + 0.07 0.20 - 0.03 0.08 MAX M S5H1420 DBS Channel Decoder for DVB-S/DSS 0-7 + 0.073 0.127 - 0.037 0.25TYP 0.08 MAX 0.05 MIN 1.40 + 0.05 1.60 MAX - - 30 ...
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... Update chapter : 3.4.9.2 Serial output interface (Page 10). Update chapter : 3.4.9.3 MPEG Clock Control (Page 12). Samsung Electronics Co, Ltd. www.samsung.com T : 82-31-279-7640 Suwon P.O.BOX 416 Maetan-3dong, YoungTong-gu, Suwon-si, Gyeonggi-do, Korea 442-742 Samsung Electronics Co, Ltd. Proprietary Information (Page 16). ’ S5H1420 DBS Channel Decoder for DVB-S/DSS - - 31 ...