MPC9350 Integrated Device Technology, Inc., MPC9350 Datasheet
MPC9350
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MPC9350 Summary of contents
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... VCO frequency for PLL feedback. This feedback divider must be selected to match the VCO frequency range. With the available feedback output dividers, the internal VCO of the MPC9350 is running at either 16x or 32x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either one half, one fourth or one eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD pins, respectively ...
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... Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc ÷ 2 PLL Ref 4 ÷ ÷ ÷ 200 – 400 MHz 32 ÷ Figure 1. MPC9350 Logic Diagram GND CCO 28 QA MPC9350 29 GND ...
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... PLL enabled. The VCO output is routed to the output dividers Selects feedback divider ÷ 16 VCO = 16 * Input reference clock Outputs disabled QA = VCO ÷ VCO ÷ VCO ÷ VCO ÷ 8 Max Unit Condition ±20 mA ±50 mA 125 °C MPC9350 MPC9350 3 ...
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... CCA I Maximum Quiescent Supply Current CC V Output termination voltage TT 1. The MPC9350 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of V Table 5. AC Characteristics (V CC Symbol Characteristics f Input Frequency ...
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... Maximum Quiescent Supply Current CC V Output termination voltage TT 1. The MPC9350 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of V output. IDT™ Low Voltage PLL Clock Driver Advanced Clock Drivers Devices ...
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... MPC9350 Low Voltage PLL Clock Driver Programming the MPC9350 The MPC9350 clock driver outputs can be configured into several divider modes. In addition, the internal feedback of the device allows for flexibility in establishing two input to output frequency relationships. The output division settings establish the output frequency relationship. The output divider of the four output groups allows the user to configure the outputs into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios ...
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... S series terminated lines in parallel. When taken to its extreme, specification of CC the fanout of the MPC9350 clock driver is effectively doubled due to its capability to drive multiple lines. IN 2.5V or 3.3V IN =5–15Ω S 22µ ...
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... Time (ns) Figure 5. Single versus Dual Waveforms Pulse Generator Z = 50Ω Figure 7. TCLK MPC9350 AC Test Reference for V MPC9350 IDT™ Low Voltage PLL Clock Driver Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 8 Since this step is well above the threshold region, it will not cause any false clock triggering ...
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... The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles ÷ GND 100 Figure 9. Output Duty Cycle (DC 1 –1/f | JIT(PER Figure 12. Period Jitter MPC9350 NETCOM MPC9350 9 ...
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... THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP. MILLIMETERS DIM MIN MAX A 1.40 1.60 A1 0.05 0. 1.35 1.45 b 0.30 0.45 b1 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 D 9.00 BSC D1 7.00 BSC e 0.80 BSC E 9.00 BSC E1 7.00 BSC L 0.50 0.70 L1 1.00 REF q 0˚ 7˚ 12 REF 0.08 0.20 R2 0.08 --- S 0.20 REF Advanced Clock Drivers Devices Freescale Semiconductor NETCOM MPC9350 ...
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... MPC92459 MPC9350 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer Low Voltage PLL Clock Driver INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. ...