U2739M-B ATMEL Corporation, U2739M-B Datasheet
U2739M-B
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U2739M-B Summary of contents
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... DAB One-Chip Channel- and Source Decoder Description The U2739M integrated circuit in advanced CMOS technology for demodulation and decoding of a DAB signal according to ETS 300 401. The channel decoder part includes the main features OFDM demodulation & decoding and time & frequency synchro- nization algorithms, using the embedded OAK DSP core ...
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... U2739M-B Table of Contents 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Channel Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Audio Source Decoder 1.4 Data Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... U2739M ...
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... U2739M-B Table of Contents (continued) 8.2 ’Set Configuration’ Commands 8.2.1 Set Global Configuration 8.2.2 Set TS Configuration 8.2.3 Set FS Configuration 8.2.4 Set XO Configuration 8.2.5 Set HSSO / RS232 Configuration 8.2.6 Set WAGC Configuration 8.2.7 Set RCC Slot Configuration 8.2.8 Set RFU 8.3 ’Read Status’ Commands 8.3.1 Read Global Status 8.3.2 Read Synchronization Status 8.3.3 Read CIR Status 8.4 ’ ...
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... D Digital Null-Symbol detection (FSYNCH generation) D Channel filtering (48 dB) D Optional SAW filter equalization D Digital AFC (freq. tolerance < 0.5 Hz for mode I) Rev. A1, 22-May-01 U2739M-B D Digital AGC with a wide gain control range D Off-chip de-interleaver memory for full 1.8 Mbit/s decoding data rate D Time & frequency synchronization on DSP OAK core ...
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... PWM dF AMD VCXO XO tank UNIT BOOT ROM UNIT U2739M-B HSSO 6 (69) D 10-bit ADC interface and SPDIF – ADC sampling clock generation – ADC binary or 2’s complement format selection – support of several intermediate frequencies D DSP OAK core bootstrap ROM interface ...
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... PRO04T C-bus address bit 2 PRO04T C-bus address bit 3 PRO04T C-bus address bit 4 PRO04T C-bus address bit 5 PRO04T C-bus address bit 6 PRO04T Test output bit 0 PRO02T C-bus address bit 7 PRO04T U2739M-B Pad Type Dir Tol. out ...
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... U2739M-B QFP144 QFP100 Pin Name 45 33 C_ADD8 46 34 C_ADD9 47 35 C_ADD10 48 36 C_ADD11 49 37 C_ADD12 50 38 DVDD1 51 39 C_ADD13 52 C_ADD14 53 C_ADD15 54 40 C_DATA0/DBG 55 41 C_DATA1/BOOT 56 C_DATA8 57 C_DATA9 58 42 DVSS2 59 43 C_DATA2/URST 60 44 C_DATA3/XUSE 61 C_DATA10 62 C_DATA11 63 45 C_DATA4/PSPC 64 46 C_DATA5/RDI_VBIT 65 C_DATA12 66 C_DATA13 ...
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... SRAM address bit 12 PRO04T Test output bit 14 PRO02T SRAM address bit 11 PRO04T SRAM address bit 10 PRO04T Test output bit 15 PRO02T SRAM address bit 9 PRO04T SRAM address bit 8 PRO04T U2739M-B Pad Type Dir Tol. out out out out out out out out pwr x ...
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... U2739M-B QFP144 QFP100 Pin Name 131 TOUT16 132 92 SRAM_A7 133 93 SRAM_A6 134 94 DVDD3 135 TOUT17 136 95 SRAM_A5 137 96 SRAM_A4 138 TMUX0 139 97 SRAM_A3 140 98 SRAM_A2 141 TMUX1 142 99 SRAM_A1 143 100 SRAM_A0 144 TMUX2 4 Strap Pins QFP144 QFP100 Pin Name 16 10 ...
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... ADC_D0 11 DVSS1 12 AVSS1 13 XOUT 14 15 XIN AVDD1 16 /RS 17 PWM 18 W_AGC 19 SLI 20 HSSO_WIN 21 HSSO_CLK 22 HSSO_DAT 23 C_ADD0 24 C_ADD1 25 Rev. A1, 22-May-01 QFP100 Figure 3. Production version QFP100 U2739M-B 75 SRAM_D2 74 SRAM_D3 73 SRAM_D4 72 SRAM_D5 71 SRAM_D6 70 SRAM_D7 69 TOUT8 68 DVDD2 67 SFCO_WIN 66 SFCO_CLK 65 SFCO_DAT 64 SFCO_ERR 63 SFCO_SID 62 DVSS3 61 RDI_TX 60 RDI_RX 59 TOUT3 ...
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C_ADD2 38 C_ADD3 39 C_ADD4 40 C_ADD5 41 C_ADD6 42 TOUT0 43 C_ADD7 44 C_ADD8 45 C_ADD9 46 C_ADD10 47 C_ADD11 48 C_ADD12 49 DVDD1 50 C_ADD13 51 C_ADD14 52 C_ADD15 53 C_DATA0 54 C_DATA1 55 C_DATA8 56 ...
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C_ADD2 38 C_ADD3 39 40 C_ADD4 41 C_ADD5 C_ADD6 42 43 C_ADD7 44 C_ADD8 45 C_ADD9 46 C_ADD10 47 C_ADD11 48 C_ADD12 49 DVDD1 50 C_ADD13 C_DATA0 54 C_DATA1 DVSS2 58 C_DATA2 ...
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... ADC_DATA0 14 (69) signal divided into twelve sections, which are related to the different interfaces. An overview of all interfaces is shown in the functional block diagram below. Several standard output interfaces like I offer a flexible usage of the U2739M-B. SRAM De- De- Decodeing modulation interleaving FS_IN SLI ...
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... ADC data input signal ADC_DATA(9:0) and the ADC sampling clock output signal U2739M-B can be connected to every standard AD with either binary or 2’s complement output format. The sampling frequency is 8.192 MHz and a bandwidth of 2 MHz is necessary. The possible IF’s, which are supported in conjunction with the IF input signal mode (parameter IFM) are given by the formula ...
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... Further the MCM trigger signal indicates the synchro- nization status. If the MCM trigger has period of 8 ms, then the U2739M-B is not locked. In the synchronized (‘locked’) state the MCM trigger period correspond to the CIF frame, which is provided every 24 ms. The complete FIC is processed at the beginning of the transmission frame ...
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... MCU) MC_MODE MC_CLK MC_DAT (U2739M MCU) Rev. A1, 22-May-01 1 Address mode tHC 0 1 ts1 th1 2 Data mode tHC th1 0 1 td1 3 Halt mode tL th2 td3 high Z Figure bus interface timing diagram U2739M-B th2 6 7 th2 ts2 td2 17 (69) ...
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... U2739M-B 6.4.4 L3 Bus Timing Parameter Parameter MC_CLK low phase MC_CLK high phase MC_DAT input setup time MC_DAT input hold time MC_MODE hold time MC_MODE setup time MC_CLK(h/l) / MC_DAT delay MC_MODE(l/h) / MC_DAT (output driven) MC_CLK(l/h) / MC_DAT(high Z) 6.4.5 I2C Bus Interface Timing Diagram tBF thS ...
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... C-bus data bit 13 (pull down) PRD04TZ C-bus data bit 6 (pull down) PRD04TZ C-bus data bit 7 (pull down) PRD04TZ C-bus data bit 14 (pull down) PRD04TZ C–-bus data bit 15 (pull down) PRD04TZ U2739M-B Pad Type Dir Tol. out out out out out out ...
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... U2739M-B 6.5.2 C-Bus / BOOT Bus Interface Description The C-Bus is a multiplexed program as well as data bus system to communicate with external components. The complete bus system is available only in the QFP144 package version and needed for debugging the internal OAK DSP core. The BOOT bus covers a subset of the C-Bus signals. The user is able to download his own so-called ’ ...
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... SRAM address bit 5 SRAM address bit 4 SRAM address bit 3 SRAM address bit 2 SRAM address bit 1 SRAM address bit 0 Due to the high data rates a fast SRAM with a access time below is necessary. 8 bit. U2739M-B Pad Type Dir Tol. PRB04TZ inout x PRB04TZ inout ...
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... U2739M-B 6.6.3 SRAM Interface Timing Diagram READ CYCLE XIN SRAM_A(18:0) SRAM_WR SRAM_OE SRAM_D(7:0) WRITE CYCLE XIN SRAM_A(18:0) SRAM_WR SRAM_OE SRAM_D(7:0) 22 (69) td1 tavav valid address td2 td3 HIGH–Z tavav td1 valid address td2 twleh td3 data valid tdvwh tddata Figure 11. SRAM interface timing diagram ...
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... U2739M-B PWM PAD f PWM –> f The U2739M-B master clock should be derived from a voltage-controlled reference oscillator. The pulse width modu- lated output signal PWM of the U2739M-B can be used to control the VCXO frequency of 24.576 MHz. Rev. A1, 22-May-01 Symbol Min. tavav td1 15.0 td2 12 ...
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... U2739M-B 6.8 Audio Interfaces 6.8.1 I2S Interface Signal Description QFP144 QFP100 Pin Name 79 56 I2S_CLK 80 57 I2S_DAT 82 58 I2S_WIN 6.8.2 I2S Interface Description The I2S interface is a standard continuous audio interface consisting of bit clock (_CLK), word select (_WIN) and data (_DAT) lines. The word select line indicates the transmitted channel: LOW for left, HIGH for right ...
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... Audio Broadcasting System: Preliminary Specification of the RDI Control Channel], [Proposal of DAB Command Set for Receiver (DCSR)]. Figure 15. RDI interface timing diagram U2739M-B A2 A14 A15 Flag bits (bi–phase coded) Pad Type Dir ...
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... U2739M-B 6.9.4 RDI Interface Timing Parameter The RDI interface is realized according to the digital audio interface IEC958 specification [CEI/ISO 958 Digital Audio Interface Standard]. Parameter Data high period Data low period 6.10 SFCO Interface 6.10.1 SFCO Interface Signal Description QFP144 QFP100 Pin Name 90 63 SFCO_SID ...
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... SFCO_data 1 6*clk SFCO_SubChId ID SFCO_ErrFl Rev. A1, 22-May-01 FIC clk 16*clk 80*clk FIB1 FIB1 12 CRC MSC 32*clk 22*clk 10 *clk MSC MSC n n – 1 Figure 16. SFCO interface timing diagram U2739M clk 48*clk 32 * clk 20*clk 12*clk 16 *clk FIB2 FIBn FIBn 1 12 CRC 27 (69) 0 ...
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... U2739M-B 6.10.4 Detailed SFCO Interface Timing Diagram td1 SFCO_win SFCO_clk SFCO_data SFCO_SubChId SFCO_ErrFl SFCO_win SFCO_clk SFCO_data SFCO_SubChId SFCO_ErrFl Figure 17. Detailed SFCO interface timing diagram 28 (69) FIC tHC tLC MSC tHW th tHC tLC td2 Rev. A1, 22-May-01 ...
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... Please notice the byte order: first the high byte is trans- set – mitted followed by the low byte (LSB first both Figure 18. RS232 interface timing diagram U2739M-B Typ. Max. Unit 160 160 160 160 10.56 10.24 10.24 Pad Type Dir ...
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... U2739M-B 6.12 HSSO Interface 6.12.1 HSSO Interface Signal Description QFP144 QFP100 Pin Name 30 21 HSSO_WIN 32 22 HSSO _CLK 34 23 HSSO _DAT 6.12.2 HSSO Interface Description The High Speed Serial Output (HSSO standard 3-line output interface implemented to give out data bursts in a multiplexed way applications can be given out ...
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... Tstg –65 Symbol Min. Typ. VDD 3.0 3.3 Vin/Vout 0 Tamb –40 Pstat 20 Pdyn 860 Pad Type Symbol Min. VIH 2.0 VIL VT VOH Pxx02x 2.4 Pxx04x 2.4 VOL Pxx02x Pxx04x U2739M-B Max. Unit VDD + 0.5 V VDD + 0.5 V 125 C Max. Unit 3.6 V VDD V + Typ. Max. Unit V 0.8 V 1.4 V VDD V VDD V ...
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... U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode NSM 0 0 Meaning 00: DAB system mode 4 01: DAB system mode 1 10: DAB system mode 2 11: DAB system mode 3 0: SMODE not valid ...
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... U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode IDV DCCV FADV DRCON DRCFIX SBCHID DRCFV U2739M-B Command sequence $ $ $ SCFON $XX $XX $XX 33 (69) ...
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... U2739M-B Command Parameters: Parameter ASDE ASD enable MUTE ASD mute state IDV ASD SBCHID valid DCCV DCC setting valid FADV Fader setting valid DRCON DRC on/off switch DRCFIX DRC additional fixed gain value valid SCFON ScF–CRC on/off switch FAD Fader value SBCHID(5..0) Sub– ...
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... DD1 enabled 0: DD1 decodes MSC 1: DD1 decodes FIDC 0: Last set DD1 PA remains valid 1: Following DD1 PA valid 0: Last set DD1 SBCHID remains valid 1: Following DD1 SBCHID valid n: DD1 packet address n: DD1 sub–channel ID U2739M-B Command sequence $ $ ...
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... D Set DD2 packet address U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode PA2V ID2V 0 PA(7..0) SBCHID Meaning 0: DD2 disabled 1: DD2 enabled 0: DD2 decodes MSC 1: DD2 decodes AIC 0: Last set DD2 PA remains valid ...
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... Sub–channel & service organization change 0: Alarm messages not accessible 1: Alarm messages accessible n: CIF counter higher part (modulo 20) n: CIF counter lower part (modulo 250) n: Value for CIFCL, from which the new configuration is valid U2739M-B Command sequence $ ...
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... DAB SCEFC SCU(1..0) 38 (69 U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode SBCHID SCU(9..2) EP EPPAR CU(7..0) Command sequence $ $ $ $XX $XX CU(9..8) ...
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... Protection level 4–A (code rate 6/8) 1xx: EEP long form option 1 (protection level xx–B) 00: Protection level 1–B (code rate 4/9) 01: Protection level 2–B (code rate 4/7) 10: Protection level 3–B (code rate 4/6) 11: Protection level 4–B (code rate 4/5) n: Sub–channel size in CU’s (4..864) U2739M-B Description 39 (69) ...
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... DAB SCEFC SCU(1..0) 40 (69 U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode SBCHID SCU(9..2) EP EPPAR CU(7..0) Command sequence $ $ $ $XX $XX CU(9..8) ...
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... Protection level 4–A (code rate 6/8) 1xx: EEP long form option 1 (protection level xx–B) 00: Protection level 1–B (code rate 4/9) 01: Protection level 2–B (code rate 4/7) 10: Protection level 3–B (code rate 4/6) 11: Protection level 4–B (code rate 4/5) n: Sub–channel size in CU’s (4..864) U2739M-B Description 41 (69) ...
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... U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode SBCHID Meaning Switch sub–channel off 1: Switch sub–channel on 0: Single sub–channel for EFC remains unchanged 1: Set SBCHID as single sub–channel for EFC n: Sub– ...
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... Following global parameters valid 0: Common IF representation 1: Reverse IF representation 00: Very high 01: High 10: Low 11: Very low 0: Equalization off 1: Equalization on 0: Binary ADC input format 1: 2’s complement ADC input format U2739M-B Command sequence $ $ PSC(10..8) $XX $XX 0 $XX ...
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... DAB 7 6 PARV COV 44 (69 U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode PKS TMIN CIRTH NSTH GFCH GFCL Command sequence $ $ $ ...
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... Number of peaks required for ’CIR correct’ indication ISPCnt CIR post processing average TMIN(7..0) CIR minimum dT output CIRTH(7..0) CIR threshold NSTH(7..0) Noise threshold B0(15..0) IIR filter coefficients Rev. A1, 22-May-01 U2739M-B Description 0: Parameters not valid 1: Following parameters valid 0: Coefficients not valid 1: following coefficients valid ...
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... Max. frame–to–frame tolerance 46 (69 U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode THA GB THB GC F2FT Description n: Fractional part n: Fractional part n: Fractional part n: Fractional part n: Fractional part ...
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... U2739M-B Write Command Data Mode XO_Rough line XO_Fine line XOAVG Description nd Coefficients for 2 order IIR filter used for XO control n: XO control average over n+1 values U2739M-B Command sequence $ $ $ $XX $XX 0 $XX ...
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... U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode HCIRL HPAD HDD2 0 Meaning 00: 0.768 MHz 01: 1.536 MHz 00: N values (DAB system mode dependent) 01: N/2 1x: N PAD output via HSSO 1: PAD output 0: No DD2 output via HSSO ...
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... Internal set2 module used 1: External USE module used 0: Internal set2 module used 1: External USE module used 0: Internal set2 module used 1: External USE module used 0: Internal set2 module used 1: External USE module used 0: Internal set2 module used 1: External USE module used U2739M-B Description 49 (69) ...
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... U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode WRISE(11..4) WRISE(17..12) WFALL(9..2) WFALL(17..10) Meaning 0: use default WAGC values 1: use following WAGC values n: value for WAGC rising edge n: value for WAGC falling edge ...
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... Write Command Data Mode U2739M-B Write Command Data Mode RCC(7..0) RCC(15..8) RCC(23..16) RCC(31..24) RCC(39..32) RCC(47..40) RCC(55..48) RCC(63..56) Meaning U2739M-B Command sequence $ $ $ $XX $XX $XX $XX $XX $XX $XX $XX Description 51 (69) ...
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... U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode (reserved) (reserved) (reserved) (reserved) RFU4 RFU5 RFU6 ... ... RFU42 RFU43 RFU44 Meaning Reserved for internal use (Atmel Wireless & Microcontrollers will deliver default values, if necessary) ...
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... U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode OAKMODE MV FSLI CIRS CCIR PSLI P(7..0) U2739M-B Command sequence $ $ $ SLI WDSP $XX CAFC $XX IDSL P(8) $XX $XX 53 (69) ...
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... U2739M-B Command Parameters: Parameter DABMODE(1..0) DAB system mode OAKMODE(1..0) OAK operating mode MV MODE_VALID line status FSLI FSLI line status SLI SLI line status CIRS CIR status CCIR(1..0) Coded CIR status CAFC(1..0) Coded AFC status PSLI(3..0) Precise signal level infor- mation IDSL(1..0) Input data signal level P(8 ...
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... U2739M-B Write Command Data Mode DT(9..2) 0 DF(15..8) DF(7..0) Meaning n: Cycle count (signed, @2.048 MHz) n: Deviation in carriers (signed, Q11 format) /2 guard U2739M-B Command sequence $ $ $ $XX DF(19..16) $XX $XX $XX Description 1) 55 (69) ...
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... If time synchronization has lost all values are set to $8000 ! 2) Signed values refers to zero (69 U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode P_FIRST(15..8) P_FIRST(7..0) P_AGV(15..8) P_AGV(7..0) P_LAST(15..8) P_LAST(7..0) Meaning guard Command sequence $ ...
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... Data Mode U2739M-B Write Command Data Mode MPG_HW1(15..8) MPG_HW1(7..0) MPG_HW2(15..8) MPG_HW2(7..0) Meaning Sync. word ($FFFx) expected MPEG stream signature U2739M-B Command sequence $ $ $ $XX $XX $XX $XX Description 57 (69) ...
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... X–PAD0 ... X–PAD31 Description The maximum X–PAD capacity supported by the U2739M-B is 64kbit/s. The access is splitted into 6 blocks (numbered 1.. bytes. The blocks are time aligned, that means block 1 is the first block in an MPEG frame after audio samples. Byte 0 is the first byte of block n, byte 31 the last one followed by the first one of block n+1. Use MC command “ ...
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... F–PAD byte 1 Rev. A1, 22-May- U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode F–PAD0 F–PAD1 Meaning U2739M-B Command sequence $ $ $ $XX $XX Description 59 (69) ...
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... Data Mode U2739M-B Write Command Data Mode AIC0 ... AIC31 Description The access is splitted into 16 blocks (numbered 0..15 bytes. The blocks are time aligned, that means block 0 is the first filled block. Byte 0 is the first byte of block n, byte 31 the last one followed by the first one of block n+1 ...
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... The maximum TII capacity is 128 bytes. The access is splitted into 4 blocks (numbered 0.. bytes. The blocks are time aligned, that means block 0 is the first filled block. Byte 0 is the first byte of block n, byte 31 the last one followed by the first one of block n+1. U2739M-B Command sequence ...
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... U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode EFC(7..0) EFC(15..8) Meaning 00: EFC of FIC 01: EFC of all MSC applications n: EFC value summarized over... ... 12 FIB’s ... 3 FIB’s ... 4 FIB’s ... 6 FIB’s Command ...
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... FIB0 bit 255 (LSB of FIB31). NOTE: The last 2 bytes of an FIB represent the result of the U2739M internal CRC check. That means, if these bytes are $00 both, the internal CRC check was successful and the FIB data bytes are correct. U2739M-B Command sequence ...
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... Parameter RCC(63..0) RCC slot data 64 (69 U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode RCC(7..0) RCC(15..8) RCC(23..16) RCC(31..24) RCC(39..32) RCC(47..40) RCC(55..48) RCC(3..56) Meaning Command sequence $ ...
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... RCC TX slot pointer Rev. A1, 22-May- U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode TXPTR Meaning U2739M-B Command sequence $ $ $ RXPTR $XX Description 65 (69) ...
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... XPAD block 6 RFU0..11 66 (69 U2739M-B Write Command Data Mode U2739M-B Write Command Data Mode RFU0 ... RFU43 Meaning See: read XPAD command Reserved for future use Command sequence $ $9X ...
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... Package Information Rev. A1, 22-May-01 U2739M-B 67 (69) ...
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... U2739M-B 68 (69) Rev. A1, 22-May-01 ...
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... Data sheets can also be retrieved from the Internet: Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423 Rev. A1, 22-May-01 U2739M-B http://www.atmel–wm.com 69 (69) ...