MC68HC908GP20CFB Freescale Semiconductor, Inc, MC68HC908GP20CFB Datasheet
MC68HC908GP20CFB
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MC68HC908GP20CFB Summary of contents
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MC68HC908GP20 Advance Information M68HC08 Microcontrollers Rev. 2.1 MC68HC908GP20/D 08/2005 freescale.com ...
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Advance Information — MC68HC908GP20 Section 1. General Description . . . . . . . . . . . . . . . . . . . 31 Section 2. Memory Map . . . . . . . . ...
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List of Sections Section 19. System Integration Module (SIM 287 Section 20. Serial Peripheral Interface Section 21. Timebase Module (TBM ...
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Advance Information — MC68HC908GP20 1.1 1.2 1.3 1.3.1 1.3.2 1.4 1.5 1.6 1.6.1 1.6.2 1.6.3 1.6.4 1.6.5 1.6.6 1.6.7 1.6.8 1.6.9 1.6.10 1.6.11 1.6.12 1.6.13 1.6.14 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Section 1. General Description Contents . . . ...
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Advance Information 6 Section 2. Memory Map Contents . . ...
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MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Low-Voltage Inhibit Module (LVI) . ...
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Advance Information 8 Interrupts ...
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MC68HC908GP20 Rev 2.1 — Freescale Semiconductor I/O Signals . . . . . . . . ...
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Advance Information 10 Section 7. Clock Generator Module ...
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MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Special Modes . . . . . . ...
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Advance Information 12 Low-Power Modes . . . . . . . . ...
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Wait Mode ...
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Advance Information 14 Section 14. Low-Voltage Inhibit (LVI) Contents . . . . . . . . ...
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MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Section 16. Input/Output (I/O) Ports Contents . . . . . ...
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Advance Information 16 Section 18. Serial Communications ...
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MC68HC908GP20 Rev 2.1 — Freescale Semiconductor SCI Status Register ...
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Resetting the SPI . . . . . . . . . . . . ...
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I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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I/O Registers ...
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ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 23.14 5.0-V SPI Characteristics ...
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Advance Information 22 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor ...
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Advance Information — MC68HC908GP20 Figure 1-1 1-2 1-3 1-4 2-1 2-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 5-1 5-2 5-3 5-4 6-1 6-2 6-3 6-4 6-5 6-6 6-7 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Title MCU Block ...
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List of Figures Figure 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 8-1 8-2 9-1 9-2 10-1 10-2 10-3 10-4 10-5 10-6 11-1 11-2 11-3 12-1 12-2 12-3 13-1 13-2 13-3 13-4 Advance Information 24 Title CGMC Block ...
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Figure 14-1 14-2 14-3 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 16-10 16-11 16-12 16-13 16-14 16-15 16-16 16-17 16-18 16-19 18-1 18-2 18-3 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor ...
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List of Figures Figure 18-4 18-5 18-6 18-7 18-8 18-9 18-10 18-11 18-12 18-13 18-14 18-15 18-16 19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 19-11 19-12 19-13 19-14 19-15 19-16 19-17 19-18 19-19 19-20 19-21 19-22 Advance ...
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Figure 20-1 20-2 20-3 20-4 20-5 20-6 20-7 20-8 20-9 20-10 20-11 20-12 20-13 20-14 20-15 21-1 21-2 22-1 22-2 22-3 22-4 22-5 22-6 22-7 22-8 22-9 22-10 22-11 22-12 22-13 22-14 22-15 22-16 22-17 MC68HC908GP20 Rev 2.1 — Freescale ...
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List of Figures Figure 23-1 23-2 23-3 23-4 23-5 23-6 23-7 23-8 23-9 23-10 23-11 Advance Information 28 Title Typical High-Side Driver Characteristics – Ports PTA7–PTA0, PTB7–PTB0, PTC6–PTC5, PTD7–PTD0, and PTE1–PTE0 (V Typical High-Side Driver Characteristics – Ports PTA7–PTA0, PTB7–PTB0, ...
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Advance Information — MC68HC908GP20 Table 2-1 4-1 4-2 5-1 5-2 7-1 7-2 7-3 10-1 10-2 11-1 11-2 14-1 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Title Vector Addresses . . . . ...
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List of Tables Table 16-1 16-2 16-3 16-4 16-5 16-6 18-1 18-2 18-3 18-4 18-5 18-6 18-7 18-8 19-1 19-2 19-3 19-4 20-1 20-2 20-3 20-4 21-1 22-1 22-2 22-3 25-1 Advance Information 30 Title Port Control Register Bits Summary ...
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Advance Information — MC68HC908GP20 1.1 Contents 1.2 1.3 1.3.1 1.3.2 1.4 1.5 1.6 1.6.1 1.6.2 1.6.3 1.6.4 1.6.5 1.6.6 1.6.7 1.6.8 1.6.9 1.6.10 1.6.11 1.6.12 1.6.13 1.6.14 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Section 1. General Description Introduction . . ...
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Introduction The MC68HC908GP20 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory ...
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MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Low-power design; fully static with stop and wait modes Standard low-power modes of operation: – Wait mode ...
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Features of the CPU08 Features of the CPU08 include: • • • • • • • • • • 1.4 MCU Block Diagram Figure 1-1 parentheses within a module block indicates the module name. ...
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M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH — 19968 BYTES USER RAM — 512 BYTES MONITOR ROM — 307 BYTES USER FLASH VECTOR SPACE — 36 BYTES CLOCK GENERATOR MODULE 32-kHz ...
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Pin Assignments PTE0/TxD/FLSPMGN Advance Information 36 V (PLL) DDA 1 V (PLL) 2 SSA CGMXFC(PLL) 3 OSC2 4 OSC1 5 RST 6 PTC0 7 PTC1 8 PTC2 9 PTC3 10 PTC4 11 12 PTE1/RxD 13 IRQ/V /FLSEPMGN 14 PP ...
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Pin Functions Descriptions of the pin functions are provided here. 1.6.1 Power Supply Pins ( from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent ...
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Use a high-frequency-response ceramic capacitor for C1 optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. 1.6.2 Oscillator Pins (OSC1 and OSC2) The OSC1 and OSC2 pins ...
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External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See 1.6.5 CGM Power Supply Pins (V V DDA clock generator module (CGM). Decoupling of these pins should be as per ...
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Port A Input/Output (I/O) Pins (PTA7/KBD7–PTA0/KBD0) PTA7–PTA0 are general-purpose, bidirectional I/O port pins. Any or all of the port A pins can be programmed to serve as keyboard interrupt pins. See Keyboard Interrupt Module These port pins also have ...
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These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis. 1.6.14 Port E I/O Pins (PTE1/RxD–PTE0/TxD) PTE0–PTE1 are general-purpose, ...
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Advance Information 42 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor ...
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Advance Information — MC68HC908GP20 2.1 Contents 2.2 2.3 2.4 2.5 2.2 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in • • • • 2.3 Unimplemented Memory Locations Accessing an unimplemented location can cause ...
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Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In the reserved locations are marked with the word Reserved or with the letter R. 2.5 Input/Output (I/O) Section Most of the control, status, and ...
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MC68HC908GP20 Rev 2.1 — Freescale Semiconductor $0000 I/O Registers ↓ 64 Bytes $003F $0040 ↓ 512 Bytes $023F $0240 Unimplemented ↓ 44,480 Bytes $AFFF $B000 FLASH Memory ↓ 19,968 Bytes $FDFF $FE00 SIM Break Status Register (SBSR) $FE01 SIM Reset ...
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Note: $FFF6–$FFFD reserved for 8 security bytes Advance Information 46 $FE10 Unimplemented 16 Bytes ↓ Reserved for Compatibility with Monitor Code for A-Family Parts $FE1F $FE20 Monitor ROM ↓ 307 Bytes $FF52 $FF53 Unimplemented ↓ 45 Bytes $FF7F $FF80 FLASH ...
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Addr. Register Name Read: Port A Data Register $0000 Write: (PTA) Reset: Read: Port B Data Register $0001 Write: (PTB) Reset: Read: Port C Data Register $0002 Write: (PTC) Reset: Read: Port D Data Register $0003 Write: (PTD) Reset: Read: ...
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Addr. Register Name Read: $000A Unimplemented Write: Reset: Read: $000B Unimplemented Write: Reset: Read: Data Direction Register E $000C Write: (DDRE) Reset: Read: Port A Input Pullup Enable $000D Write: Register (PTAPUE) Reset: Read: Port C Input Pullup Enable $000E ...
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Addr. Register Name Read: SCI Control Register 2 $0014 Write: (SCC2) Reset: Read: SCI Control Register 3 $0015 Write: (SCC3) Reset: Read: SCI Status Register 1 $0016 Write: (SCS1) Reset: Read: SCI Status Register 2 $0017 Write: (SCS2) Reset: Read: ...
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Addr. Register Name Read: Configuration Register 2 $001E (CONFIG2)† Write: Reset: Read: Configuration Register 1 $001F Write: † (CONFIG1) Reset: Read: Timer 1 Status and Control $0020 Write: Register (T1SC) Reset: Read: Timer 1 Counter Register $0021 Write: High (T1CNTH) ...
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Addr. Register Name Read: Timer 1 Channel 1 Status $0028 and Control Register Write: (T1SC1) Reset: Read: Timer 1 Channel 1 $0029 Write: Register High (T1CH1H) Reset: Read: Timer 1 Channel 1 $002A Write: Register Low (T1CH1L) Reset: Read: Timer ...
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Addr. Register Name Read: Timer 2 Channel 0 $0032 Write: Register Low (T2CH0L) Reset: Read: Timer 2 Channel 1 Status $0033 and Control Register Write: (T2SC1) Reset: Read: Timer 2 Channel 1 $0034 Write: Register High (T2CH1H) Reset: Read: Timer ...
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Addr. Register Name Read: Analog-to-Digital Status $003C and Control Register Write: (ADSCR) Reset: Read: Analog-to-Digital Data $003D Write: Register (ADR) Reset: Read: Analog-to-Digital Input $003E Write: Clock Register (ADCLK) Reset: Read: $003F Unimplemented Write: Reset: Read: SIM Break Status Register ...
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Addr. Register Name Read: Interrupt Status Register 3 $FE06 Write: (INT3) Reset: Read: FLASH Test Control $FE07 Write: Register (FLTCR) Reset: Read: FLASH Control Register $FE08 Write: (FLCR) Reset: Read: Break Address Register $FE09 Write: High (BRKH) Reset: Read: Break ...
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Vector Priority MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Table 2-1. Vector Addresses Vector Address Lowest $FFDC IF16 $FFDD $FFDE IF15 $FFDF $FFE0 IF14 $FFE1 $FFE2 IF13 $FFE3 $FFE4 IF12 $FFE5 $FFE6 IF11 $FFE7 $FFE8 IF10 $FFE9 $FFEA IF9 $FFEB $FFEC ...
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Advance Information 56 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor ...
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Advance Information — MC68HC908GP20 3.1 Contents 3.2 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.7 3.7.1 3.7.2 3.8 3.8.1 3.8.2 3.9 3.9.1 3.9.2 3.10 3.10.1 3.10.2 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Section ...
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Introduction The MCU may enter two low-power modes: wait mode and stop mode. They are common to all HC08 MCUs and are entered through instruction ...
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Stop Mode Stop mode is entered when a STOP instruction is executed. The CPU clock is disabled and the bus clock is disabled if the OSCSTOPENB bit in the CONFIG register logic 0. (See Register 3.3 ...
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Stop Mode The break module is inactive in stop mode. A break interrupt causes exit from stop mode and sets the BW bit in the break status register. The STOP instruction does not affect break module register states. 3.5 ...
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PLL without turning it off. Applications that require the PLL to wake the MCU from wait mode also can deselect the PLL output without turning off the PLL. 3.6.2 Stop Mode If the OSCSTOPEN bit in ...
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The STOP bit in the configuration register (CONFIG) enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit. 3.8 External Interrupt Module (IRQ) 3.8.1 Wait Mode ...
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Low-Voltage Inhibit Module (LVI) 3.10.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 3.10.2 Stop ...
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Serial Peripheral Interface Module (SPI) 3.12.1 Wait Mode The SPI module remains active in wait mode. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. If SPI module functions are not ...
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Timebase Module (TBM) 3.14.1 Wait Mode The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during wait mode, ...
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Advance Information 66 External interrupt — A high-to-low transition on an external interrupt pin (IRQ pin) loads the program counter with the contents of locations: $FFFA and $FFFB; IRQ pin. Break ...
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Exiting Stop Mode These events restart the system clocks and load the program counter with the reset vector or with an interrupt vector: • • • • • MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Serial communications ...
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Upon exit from stop mode, the system clocks begin running after an oscillator stabilization delay. A 12-bit stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external interrupt. The short stop recovery bit, SSREC, ...
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Advance Information — MC68HC908GP20 4.1 Contents 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.3.1 4.3.3.2 4.3.3.3 4.3.3.4 4.3.3.5 4.3.4 4.4 4.4.1 4.4.2 4.4.2.1 4.4.2.2 4.4.2.3 4.4.2.4 4.4.2.5 4.4.2.6 4.4.2.7 4.4.2.8 4.4.2.9 4.4.2.10 4.4.2.11 4.4.3 4.4.3.1 4.4.3.2 4.4.3.3 MC68HC908GP20 Rev 2.1 — Freescale ...
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Introduction Resets and interrupts are responses to exceptional events during program execution. A reset re-initializes the MCU to its startup condition. An interrupt vectors the program counter to a service routine. 4.3 Resets A reset immediately returns the MCU ...
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Internal Reset Sources: • • • • • All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external devices. The MCU is held in reset for an additional 32 CGMXCLK cycles ...
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Power-On Reset A power-on reset (POR internal reset caused by a positive transition on the V reset the MCU. This distinguishes between a reset and a POR. The POR is not a brown-out detector, low-voltage detector, or ...
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COP Reset A COP reset is an internal reset caused by an overflow of the COP counter. A COP reset sets the COP bit in the system integration module (SIM) reset status register. To clear the COP counter and ...
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Illegal Address Reset An illegal address reset is an internal reset caused by opcode fetch from an unmapped address. An illegal address reset sets the ILAD bit in the SIM reset status register. A data fetch from an unmapped ...
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PIN — External Reset Flag COP — Computer Operating Properly Reset Bit ILOP — Illegal Opcode Reset Bit ILAD — Illegal Address Reset Bit LVI — Low-Voltage Inhibit Reset Bit 4.4 Interrupts An interrupt temporarily changes the sequence of program ...
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STACKING ORDER After every instruction, the CPU checks all pending interrupts if the I bit is not set. If more than one interrupt is pending when an instruction is done, the highest priority interrupt is serviced first. In the example ...
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The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE: To maintain compatibility with the M6805 Family, the H register is not ...
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YES Advance Information 78 FROM RESET YES BREAK INTERRUPT ? NO I BIT SET? I BIT SET? NO YES IRQ INTERRUPT ? NO YES CGM INTERRUPT ? NO OTHER YES INTERRUPTS ? NO STACK CPU REGISTERS LOAD PC WITH INTERRUPT ...
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Sources The sources in Reset SWI instruction IRQ pin CGM (PLL) TIM1 channel 0 TIM1 channel 1 TIM1 overflow TIM2 channel 0 TIM2 channel 1 TIM2 overflow SPI receiver full SPI overflow SPI mode fault SPI transmitter empty SCI ...
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SWI Instruction The software interrupt instruction (SWI) causes a non-maskable interrupt. NOTE: A software interrupt pushes PC onto the stack. An SWI does not push PC – hardware interrupt does. 4.4.2.2 Break Interrupt The break module ...
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TIM2 TIM2 CPU interrupt sources: • • 4.4.2.7 SPI SPI CPU interrupt sources: • • • MC68HC908GP20 Rev 2.1 — Freescale Semiconductor TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter value rolls over ...
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SCI SCI CPU interrupt sources: • • • • • Advance Information 82 Overflow bit (OVRF) — The OVRF bit is set if software does not read the byte in the receive data register before the next full ...
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KBD0–KBD7 Pins A logic keyboard interrupt pin latches an external interrupt request. 4.4.2.10 ADC (Analog-to-Digital Converter) When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after ...
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Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. status register flags that they set. The interrupt status registers can be useful for debugging. Advance Information 84 Table 4-2 summarizes the interrupt sources and ...
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Interrupt Status Register 1 Address: Read: Write: Reset: IF6–IF1 — Interrupt Flags 6–1 These flags indicate the presence of interrupt requests from the sources shown in Bit 1 and Bit 0 — Always read 0 4.4.3.2 Interrupt Status Register ...
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Interrupt Status Register 3 Address: Read: Write: Reset: IF16–IF15 — Interrupt Flags 16–15 This flag indicates the presence of an interrupt request from the source shown Interrupt request present interrupt request present Bits ...
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Advance Information — MC68HC908GP20 Section 5. Analog-to-Digital Converter (ADC) 5.1 Contents 5.2 5.3 5.4 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.5 5.6 5.6.1 5.6.2 5.7 5.7.1 5.7.2 5.7.3 5.8 5.8.1 5.8.2 5.8.3 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Introduction . . ...
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Introduction This section describes the 8-bit analog-to-digital converter (ADC). 5.3 Features Features of the ADC module include: • • • • • • 5.4 Functional Description The ADC provides eight pins for sampling external sources at pins PTB7/AD7–PTB0/AD0. An ...
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INTERNAL DATA BUS INTERRUPT AIEN 5.4.1 ADC Port I/O Pins PTB7/AD7–PTB0/AD0 are general-purpose I/O (input/output) pins that share with the ADC channels. The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC ...
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Voltage Conversion When the input voltage to the ADC equals V signal to $FF (full scale). If the input voltage equals V converts it to $00. Input voltages between V straight-line linear conversion. All other input voltages will result ...
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Interrupts When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC conversion. A CPU interrupt is generated if the COCO/IDMAS bit is at logic 0. If COCO/IDMAS bit is set, a ...
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ADC Analog Power Pin (V The ADC analog portion uses V V DDAD be necessary to ensure clean V NOTE: For maximum noise immunity, route V capacitors as close as possible to the package. 5.7.2 ADC Analog Ground Pin ...
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ADC Status and Control Register Function of the ADC status and control register (ADSCR) is described here. Address: $0003C Read: Write: Reset: COCO/IDMAS — Conversions Complete/Interrupt DMA Select Bit When the AIEN bit is a logic 0, the COCO/IDMAS ...
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AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset ...
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ADCH4 NOTE: If any unused channels are selected, the resulting ADC conversion will be unknown 5.8.2 ADC Data Register One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC conversion completes. Address: ...
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ADC Clock Register The ADC clock register (ADCLK) selects the clock frequency for the ADC. Address: $0003E Read: Write: Reset: ADIV2–ADIV0 — ADC Clock Prescaler Bits ADIV2–ADIV0 form a 3-bit field which selects the divide ratio used by the ...
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If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the clock source. ...
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Advance Information 98 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor ...
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Advance Information — MC68HC908GP20 6.1 Contents 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.2 Introduction This section describes the break module. The break module can generate a break interrupt that stops normal ...
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Features Features of the break module include: • • • • 6.4 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the CPU. The ...
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IAB15–IAB0 Figure 6-1. Break Module Block Diagram Addr. Register Name Read: SIM Break Status Register $FE00 Write: (SBSR) Reset: Read: SIM Break Flag Control $FE03 Write: Register (SBFCR) Reset: Read: Break Address Register $FE09 Write: High (BRKH) Reset: Read: Break ...
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Flag Protection During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. 6.4.2 CPU During Break Interrupts The CPU starts a break interrupt by: • ...
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Stop Mode A break interrupt causes exit from stop mode and sets the SBSW bit in the break status register. 6.6 Break Module Registers These registers control and monitor operation of the break module: • • • • • ...
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BRKA — Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic before exiting ...
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Break Status Register The break status register (SBSR) contains a flag to indicate that a break caused an exit from wait mode. The flag is useful in applications requiring a return to wait mode after exiting from a break ...
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Break Flag Control Register The break flag control register (SBFCR) contains a bit that enables software to clear status bits while the MCU break state. Address: Read: Write: Reset: BCFE — Break Clear Flag Enable Bit ...
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Advance Information — MC68HC908GP20 Section 7. Clock Generator Module (CGMC) 7.1 Contents 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.6 7.6.1 7.6.2 7.6.3 7.6.4 ...
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Introduction This section describes the clock generator module. The CGMC generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGMC also generates ...
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Features Features of the CGMC include: • • • • • • • • 7.4 Functional Description The CGMC consists of three major submodules: • • • Figure 7-1 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Phase-locked loop with output ...
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OSCILLATOR (OSC) OSC2 OSC1 SIMOSCEN (FROM SIM) OSCSTOPENB (FROM CONFIG) PHASE-LOCKED LOOP (PLL) CGMRDV REFERENCE DIVIDER RDS3–RDS0 V DDA PHASE DETECTOR LOCK DETECTOR LOCK MUL11–MUL0 CGMVDV FREQUENCY DIVIDER Advance Information 110 CGMRCLK BCS CGMXFC V SSA VPR1–VPR0 VRS7–VRS0 VOLTAGE LOOP ...
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Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration ...
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The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGM/XFC noise. The VCO frequency is bound to a range from roughly one-half to twice the ...
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Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: • • 7.4.5 Manual and Automatic PLL Bandwidth Modes The PLL can change the ...
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Circuit.) If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software ...
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The following conditions apply when in manual mode: • • • • • 7.4.6 Programming the PLL The following procedure shows how to program the PLL. NOTE: The round function in the following equations means that the real number should ...
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Select a VCO frequency multiplier < N Advance Information 116 P, the power of two multiplier, and N, the range multiplier, are integers. In cases where desired bus frequency has some tolerance, choose f ...
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MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Then recalculate round × VCLKDES ------------------------------------ - P × RCLK Advance Information 117 ...
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Calculate and verify the adequacy of the VCO and bus 7. Select the VCO’s power-of-two range multiplier E, according to 8. Select a VCO linear range multiplier, L, where f 9. Calculate and verify the adequacy of the VCO ...
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Program the PLL registers accordingly: Table 7-1 notation): MC68HC908GP20 Rev 2.1 — Freescale Semiconductor a. In the PRE bits of the PLL control register (PCTL), program the binary equivalent the VPR bits of the PLL ...
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Special Programming Exceptions The programming method described in does not account for three possible exceptions. A value of 0 for meaningless when used in the equations given. To account for these exceptions: • • ...
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CGMC External Connections In its typical configuration, the CGMC requires up to nine external components. Five of these are for the crystal oscillator and two or four are for the PLL. The crystal oscillator is normally connected in a ...
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SIMOSCEN OSCSTOPENB (FROM CONFIG) OSC1 Note: Filter network in box can be replaced with a 0.47 µF capacitor, but will degrade stability. Figure 7-2. CGMC External Connections 7.5 I/O Signals The following paragraphs describe the CGMC I/O ...
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External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure NOTE: To prevent noise problems, the filter network should ...
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Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (f Figure 7-2 OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown ...
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Figure 7-3 Addr. Register Name Read: PLL Control Register $0036 Write: (PCTL) Reset: Read: PLL Bandwidth Control $0037 Write: Register (PBWC) Reset: Read: PLL Multiplier Select High $0038 Write: Register (PMSH) Reset: Read: PLL Multiplier Select Low $0039 ...
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PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, the prescaler bits, and the VCO power-of-two range selector bits. Address: Read: Write: Reset: PLLIE — ...
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PLLON — PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See Circuit.) Reset sets this bit ...
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VPR1 and 0 — VCO Power-of-Two Range Select Bits These read/write bits control the VCO’s hardware power-of-two range multiplier E that, in conjunction with L (See Programming the controls the hardware center-of-range frequency, f cannot be written when the PLLON ...
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Read: Write: Reset: AUTO — Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the ...
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PLL Multiplier Select Register High The PLL multiplier select register high (PMSH) contains the programming information for the high byte of the modulo feedback divider. Address: Read: Write: Reset: Figure 7-6. PLL Multiplier Select Register High (PMSH) MUL11–MUL8 — ...
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PLL Multiplier Select Register Low The PLL multiplier select register low (PMSL) contains the programming information for the low byte of the modulo feedback divider. Address: Read: Write: Reset: MUL7–MUL0 — Multiplier Select Bits These read/write bits control the ...
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PLL VCO Range Select Register NOTE: PMRS may be called PVRS on other HC08 derivatives. The PLL VCO range select register (PMRS) contains the programming information required for the hardware configuration of the VCO. Address: Read: Write: Reset: VRS7–VRS0 ...
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PLL Reference Divider Select Register NOTE: PMDS may be called PRDS on other HC08 derivatives. The PLL reference divider select register (PMDS) contains the programming information for the modulo reference divider. Address: Read: Write: Reset: RDS3–RDS0 — Reference Divider ...
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Interrupts When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables ...
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PLL is first enabled and waiting for LOCK or LOCK is lost. 7.8.2 Stop Mode If the OSCSTOPENB bit in the CONFIG register is cleared (default), then the STOP instruction disables the CGMC (oscillator and ...
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Acquisition/Lock Time Specifications The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 7.9.1 Acquisition/Lock Time ...
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Parametric Influences on Reaction Time Acquisition and lock times are designed short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition ...
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Choosing a Filter As described in external filter network is critical to the stability and reaction time of the PLL. The ...
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Advance Information — MC68HC908GP20 Section 8. Configuration Register (CONFIG) 8.1 Contents 8.2 8.3 8.2 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers enable or disable these options: • • • • • • 8.3 Functional ...
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NOTE FLASH device, the options except LVI5OR3 are one-time writeable by the user after each reset. The LVI5OR3 bit is one-time writeable by the user only after each POR (power-on reset). The CONFIG registers are not in the ...
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NOTE: For V The voltage regular must always be enabled. The charge pump must have the voltage regulator on to provide the proper voltage to the FLASH memory. For V The voltage regulator may be disabled to conserve power. The ...
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LVISTOP — LVI Enable in Stop Mode Bit When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP. (See 3.6.2 Stop 1 = LVI enabled during stop mode 0 ...
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NOTE: When the LVISTOP is enabled, the system stabilization time for power on reset and long stop recovery (both 4096 CGMXCLK cycles) gives a delay longer than the enable time for the LVI. There is no period where the MCU ...
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Advance Information 144 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor ...
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Advance Information — MC68HC908GP20 Section 9. Computer Operating Properly (COP) 9.1 Contents 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.4.8 9.5 9.6 9.7 9.8 9.8.1 9.8.2 9.9 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor Contents . . ...
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Introduction The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The ...
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The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 2 CGMXCLK cycles, depending on the state of the COP rate ...
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COPCTL Write Writing any value to the COP control register (COPCTL) (see Control of the prescaler. Reading the COP control register returns the low byte of the reset vector. 9.4.4 Power-On Reset The power-on reset (POR) circuit clears the ...
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COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte ...
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Wait Mode The COP remains active during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter in a CPU interrupt routine. 9.8.2 Stop Mode Stop mode turns off the CGMXCLK input to the ...
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Advance Information — MC68HC908GP20 10.1 Contents 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.5 10.6 10.6.1 10.6.2 10.7 10.8 10.9 10.2 Introduction The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. ...
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Features • • • • • • • • • • • 10.4 CPU Registers Figure 10-1 the memory map. Advance Information 152 Object code fully upward-compatible with M68HC05 Family 16-bit stack pointer with stack manipulation instructions 16-bit index ...
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Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68HC908GP20 Rev 2.1 — Freescale Semiconductor ...
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Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed ...
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Read: Write: Reset: NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer ...
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Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the ...
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I — Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU ...
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C — Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and ...
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Stop Mode The STOP instruction: • • After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. 10.7 CPU During Break Interrupts If a break module is present on the MCU, the CPU starts a ...
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Instruction Set Summary Table 10-1. Instruction Set Summary Source Operation Form ADC #opr ADC opr ADC opr ADC opr,X Add with Carry ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X Add ...
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Table 10-1. Instruction Set Summary (Continued) Source Operation Form BCLR n, opr Clear Bit BCS rel Branch if Carry Bit Set (Same as BLO) BEQ rel Branch if Equal Branch if Greater Than or Equal To BGE ...
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Table 10-1. Instruction Set Summary (Continued) Source Operation Form BNE rel Branch if Not Equal BPL rel Branch if Plus BRA rel Branch Always BRCLR n,opr,rel Branch if Bit Clear BRN rel Branch Never BRSET n,opr,rel Branch ...
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Table 10-1. Instruction Set Summary (Continued) Source Operation Form CMP #opr CMP opr CMP opr CMP opr,X Compare A with M CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX Complement (One’s Complement) COM opr,X COM ,X ...
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Table 10-1. Instruction Set Summary (Continued) Source Operation Form INC opr INCA INCX Increment INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X Jump JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X Jump to Subroutine ...
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Table 10-1. Instruction Set Summary (Continued) Source Operation Form NEG opr NEGA NEGX Negate (Two’s Complement) NEG opr,X NEG ,X NEG opr,SP NOP No Operation NSA Nibble Swap A ORA #opr ORA opr ORA opr ORA opr,X Inclusive OR A ...
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Table 10-1. Instruction Set Summary (Continued) Source Operation Form SBC #opr SBC opr SBC opr SBC opr,X Subtract with Carry SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC Set Carry Bit SEI Set Interrupt Mask STA opr STA opr ...
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Table 10-1. Instruction Set Summary (Continued) Source Operation Form TST opr TSTA TSTX Test for Negative or Zero TST opr,X TST ,X TST opr,SP TSX Transfer SP to H:X TXA Transfer TXS Transfer H ...
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Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH INH MSB LSB BRSET0 BSET0 BRA NEG NEGA NEGX 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...
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Advance Information — MC68HC908GP20 11.1 Contents 11.2 11.3 11.4 11.5 11.5.1 11.5.2 11.6 11.7 11.8 11.9 11.10 Wait Mode ...
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FLASH array is organized into pages within rows. There are eight pages of memory per row with eight bytes per page. The minimum erase block size is a single row, 64 bytes. Programming is performed on a per ...
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NOTE: A security feature prevents viewing of the FLASH contents. 11.4 FLASH Control Register The FLASH control register (FLCR) controls FLASH program, erase, and margin read operations. Address: Read: Write: Reset: FDIV1 — Frequency Divide Control Bit This read/write bit ...
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HVEN — High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the ...
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Charge Pump The internal FLASH charge pump is an analog circuit that provides the proper voltage to the FLASH memory when reading, programming, and erasing the memory arrays. 11.5.1 FLASH Charge Pump Frequency Control The internal charge pump required ...
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FLASH Erase Operation Use this step-by-step procedure to erase a block of FLASH memory to read as logic operating voltage is below 3.6 V, set the PMPSGVLVEN bit in 2. Set the ERASE bit, the BLK0, ...
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Write to Address Address BLK1 Value Bit Any FLASH Any 0 address A14 1 0 A14 step 4 of the erase operation, the desired erase ...
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This block erase can also be accomplished by writing to any FLASH address in which A14 = 1 while BLK1 = 0 and BLK0 = 1. In the 1/5 array case (A14 = 0, BLK1 = 0, ...
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In the other “single row case” ( BLK1 = 1, BLK0 = 1), the state determines that the range from $<A15:A12><A11:A8><A7,000><0000> to $<A15:A12><A11:A8><A7,011><1111> is erased. Address bits A15–A7 indicate arbitrary address bit values defined ...
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To program and margin read the FLASH memory, use this procedure operating voltage is below 3.6 V, ...
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Smart Programming Algorithm Page Program/Margin Read Procedure Note: This algorithm is mandatory for programming the FLASH. Note: This page program algorithm assumes the page programmed are initially erased. Figure 11-2. Smart Programming Algorithm MC68HC908GP20 Rev 2.1 — Freescale ...
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FLASH Block Protection NOTE: In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit. Due to the ability of the on-board ...
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FLASH Block Protect Register The block protect register (FLBPR) is implemented as a byte within the FLASH memory. Each bit, when programmed, protects a range of addresses in the FLASH. Address: Read: Write: Reset: BPR3 — Block Protect Register ...
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BPR0 — Block Protect Register Bit larger memory, this bit would protect the memory contents in the address range $8000 to $FFFF redundant in this implementation. Setting this bit locks everything from $B000 to $FFFF. ...
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Stop Mode When the MCU is put into stop mode, if the FLASH is in read mode, it will be put into low-power standby. Exit from stop is possible with an external interrupt, such as IRQ, keyboard interrupt, or ...
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Advance Information 184 MC68HC908GP20 Rev 2.1 — Freescale Semiconductor ...
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Advance Information — MC68HC908GP20 12.1 Contents 12.2 12.3 12.4 12.5 12.6 12.7 12.2 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. 12.3 Features Features of the IRQ module include: • • • • • • MC68HC908GP20 Rev ...
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Functional Description A logic 0 applied to the external interrupt pin can latch a CPU interrupt request. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following ...
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NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. ACK RESET VECTOR FETCH DECODER V DD INTERNAL PULLUP DEVICE IRQ Figure 12-1. IRQ Module Block Diagram Addr. Register Name Read: ...
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IRQ Pin A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is ...
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NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. 12.6 IRQ Module During Break Interrupts The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the ...
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Address: Read: Write: Reset: Figure 12-3. IRQ Status and Control Register (INTSCR) IRQF — IRQ Flag Bit This read-only status bit is high when the IRQ interrupt is pending IRQ interrupt pending 0 = IRQ interrupt not pending ...
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Advance Information — MC68HC908GP20 Section 13. Keyboard Interrupt Module (KBI) 13.1 Contents 13.2 13.3 13.4 13.5 13.6 13.6.1 13.6.2 13.7 13.8 13.8.1 13.8.2 13.2 Introduction The keyboard interrupt module (KBI) provides eight independently maskable external interrupts. MC68HC908GP20 Rev 2.1 — ...
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Features • • • • • 13.4 Functional Description Writing to the KBIE7–KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also ...
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KBD0 . TO PULLUP ENABLE . KB0IE . KBD7 TO PULLUP ENABLE KB7IE Figure 13-1. Keyboard Module Block Diagram Addr. Register Name Read: Keyboard Status $001A and Control Register Write: (INTKBSCR) Reset: Read: Keyboard Interrupt Enable $001B Write: Register (INTKBIER) ...
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If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low-level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: • • The vector fetch or software clear and ...
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NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin. ...
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Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 13.6.2 Stop Mode The keyboard module ...
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I/O Registers These registers control and monitor operation of the keyboard module: • • 13.8.1 Keyboard Status and Control Register The keyboard status and control register: • • • • Address: $001A Read: Write: Reset: Figure 13-3. Keyboard Status ...
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ACKK — Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK — Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write ...
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Advance Information — MC68HC908GP20 14.1 Contents 14.2 14.3 14.4 14.4.1 14.4.2 14.4.3 14.4.4 14.5 14.6 14.7 14.7.1 14.7.2 14.2 Introduction This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the V voltage falls below the LVI ...
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Functional Description Figure 14-1 out of reset. The LVI module contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor V enables the LVI module to generate a reset when ...