MPC991FA Motorola, MPC991FA Datasheet

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MPC991FA

Manufacturer Part Number
MPC991FA
Description
Low voltage PLL clock driver
Manufacturer
Motorola
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage PLL Clock Driver
driver. The fully differential design ensures optimum skew and PLL jitter
performance. The performance of the MPC990/991 makes the device
ideal for Workstation, Mainframe Computer and Telecommunication
applications. The MPC990 and MPC991 devices are identical except in
the interface to the reference clock for the PLL. The MPC990 offers an
on–board crystal oscillator as the PLL reference while the MPC991 offers
a differential ECL/PECL input for applications which need to lock to an
existing clock signal. Both designs offer a secondary single–ended ECL
clock for system test capabilities.
programmed via the the four fsel pins of the device. There are 16 different
output frequency configurations available in the device. The
configurations include output ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 4:3:1 and
4:3:2. The programming table in this data sheet illustrates the various
programming options. The SYNC output monitors the relationship
between the Qa and Qc output banks. The output pulses per the timing
diagrams in this data sheet signal the coincident edges of the two output
banks. This feature is useful for non binary relationships between output frequencies (i.e., 3:2 or 4:3 relationships). The Sync_Sel
input toggles the Qd outputs between sync signals and extensions to the Qc bank of outputs.
programmed independently of the other outputs allowing for unique input vs output frequency relationships. The fselFB inputs
provide 6 different feedback frequencies from the QFB differential output pair.
the MPC991’s use as a “zero” delay buffer. The propagation delay between the input reference and the output is dependent on
the input reference frequency. The selection of higher reference frequencies will provide near zero delay through the device.
directly. This allows the user to single step a design during system debug. Note that the Test_Clk input is routed through the
dividers so that depending on the programming several edges on the Test_Clk input will be needed to get corresponding edge
transitions on the outputs. The VCO_Sel input provides a means of recentering the VCO to provide a broader range of VCO
frequencies for stable PLL operation.
output synchronization and phase–lock. If the VCO is driven beyond its maximum frequency, the VCO can outrun the internal
dividers when the VCO_Sel pin is low. This will also prevent the PLL from achieving lock. Again, a master reset signal will need to
be applied to allow for phase–lock. The device employs a power–on reset circuit which will ensure output synchronization and
PLL lock on initial power–up.
2/97
Motorola, Inc. 1997
Fully Integrated PLL
Output Frequency Up to 400MHz
ECL/PECL Inputs and Outputs
Operates from a 3.3V Supply
Output Frequency Configurable
TQFP Packaging
The MPC990/991 is a 3.3V compatible, PLL based ECL/PECL clock
The MPC990/991 offers three banks of outputs which can each be
The MPC990/991 provides a separate output for the feedback to the PLL. This allows for the feedback frequency to be
The MPC990/991 features an external differential ECL/PECL feedback to the PLL. This external feedback feature allows for
The PLL_En, Ref_Sel and the Test_Clk input pins provide a means of bypassing the PLL and driving the output buffers
If the frequency select or the VCO_Sel pins are changed during operation, a master reset signal must be applied to ensure
50ps Cycle–to–Cycle Jitter
1
REV 2
PLL CLOCK DRIVER
52–LEAD TQFP PACKAGE
LOW VOLTAGE
MPC990
MPC991
CASE 848D–03
FA SUFFIX

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MPC991FA Summary of contents

Page 1

... VCO_Sel pin is low. This will also prevent the PLL from achieving lock. Again, a master reset signal will need to be applied to allow for phase–lock. The device employs a power–on reset circuit which will ensure output synchronization and PLL lock on initial power–up. 2/97 Motorola, Inc. 1997 1 REV 2 MPC990 ...

Page 2

... MOTOROLA MPC990/ MPC991 Figure 1. 52–Lead Pinout (Top View) INPUTS fsel1 fsel0 ...

Page 3

... Bypass PLL fVCO fVCO/2 Test_Clk — Reset Outputs SYNC Outputs Match Qc Outputs Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 Qa3 Qa3 Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 Qb3 Qb3 Qc0 Qc0 Qc1 Qc1 Qc2 Qc2 Qd0 Qd0 Qd1 Qd1 QFB QFB MOTOROLA ...

Page 4

... MPC990 MPC991 Qa Qc Sync (Qd Sync (Qd Sync (Qd Sync (Qd Sync (Qd) MOTOROLA 1:1 Mode 2:1 Mode 3:1 Mode 3:2 Mode 4:3 Mode Figure 3. Timing Diagrams TIMING SOLUTIONS BR1333 — Rev 6 ...

Page 5

... Common Mode Range I IH Input HIGH Current I GNDI Power Supply Current 1. Refer to Motorola Application Note AN1545/D “ Thermal Data for MPC Clock Drivers ” for thermal management guidelines. PECL DC CHARACTERISTICS ( CCA = V CCI = V CCO = 3.3V 5%, GNDI = 0V, Note 2.) Symbol Characteristic V OH Output HIGH Voltage (Note 3 ...

Page 6

... For a design which utilizes the external feedback to the PLL the selection of the crystal frequency is straight forward; simply chose a crystal which is equal in frequency to the fed back signal. MOTOROLA Min Note 6. Note 6. 25 APPLICATIONS INFORMATION Table 1 ...

Page 7

... The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs =5–15 VCCA 0.01 F MPC990/991 VCC Figure 4. Power Supply Filter 7 3. 0.01 F MOTOROLA ...

Page 8

... VIEW Y 3X –L– –N– –H– –T– SEATING 4X PLANE 0.05 (0.002 VIEW AA MOTOROLA OUTLINE DIMENSIONS FA SUFFIX TQFP PACKAGE CASE 848D-03 ISSUE TIPS 0.20 (0.008) T L– –M– 0.10 (0.004) T ...

Page 9

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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