PCF8594C-2 Philips Semiconductors, PCF8594C-2 Datasheet
PCF8594C-2
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PCF8594C-2 Summary of contents
Page 1
... Rev. 05 — 25 October 2004 1. Description The PCF8594C floating gate Electrically Erasable Programmable Read Only Memory (EEPROM) with 4 kbits (512 internal redundant storage code fault tolerant to single bit errors. This feature dramatically increases the reliability compared to conventional EEPROMs. Power consumption is low due to the full CMOS technology used ...
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... V DD Ordering information Package Name Description DIP8 plastic dual in-line package; 8 leads (300 mil) SO8 plastic small outline package 8 leads (straight); body width 3.9 mm Ordering options Topside mark PCF8594C-2 8594C-2 Rev. 05 — 25 October 2004 PCF8594C-2 2 C-bus interface Min Typ Max Unit 2.5 - 6.0 ...
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... PCF8594C-2 6 SCL INPUT 5 FILTER SDA n ADDRESS SHIFT SWITCH REGISTER 3 A2 TEST MODE DECODER POWER-ON-RESET Fig 1. Block diagram C-BUS CONTROL LOGIC ADDRESS BYTE HIGH COUNTER REGISTER 3 BYTE ...
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... Rev. 05 — 25 October 2004 PCF8594C-2 2 C-bus interface PTC SCL 6 5 SDA 2 C-bus) 2 C-bus) © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... The Most Significant Bit (MSB) ‘b7’ is sent first. A2 and A1 are hardware selectable pins and A0 is software selectable pin. A system could have up to four PCF8594C-2 devices on the same I equivalent kbit EEPROM or 4 devices of 512 bytes of memory. A0 selects the lower (logic level ‘0’) or the higher (logic level ‘1’) 256-byte page on the selected device ...
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... Data transfer is unlimited in the read mode. The information is transmitted in bytes and each receiver acknowledges with a ninth bit. Within the I fast-speed mode (400 kHz clock rate) are defined. The PCF8594C-2 operates in only the standard-speed mode. By definition, a device that sends a signal is called a ‘transmitter’, and the device which receives the signal is called a ‘ ...
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... EEPROM if the pin WP is HIGH. When the pin WP is HIGH the upper 256 bytes of the EEPROM are write-protected and no acknowledge will be given by the PCF8594C-2 when data is sent. However, an acknowledge will be given after the slave address and the word address. Byte/word write: fi ...
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... Fig 5. Auto-increment memory word address; two byte write. Page write: initiated in the same manner as the byte write operation. The master can transit eight data bytes within one transmission. After receipt of each byte, the PCF8594C-2 will respond with an acknowledge. The typical E/W time in this mode ...
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... S SLAVE ADDRESS 0 A R/W Fig 7. Master reads PCF8594C-2 slave after setting word address (write word address; read data); sequential read. S SLAVE ADDRESS Fig 8. Master reads PCF8594C-2 immediately after first byte (read mode); current address read. 9397 750 14221 Product data ...
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... C to +85 C; unless otherwise specified. Conditions f = 100 kHz SCL 100 kHz SCL Rev. 05 — 25 October 2004 PCF8594C-2 2 C-bus interface Min Max 0.3 +6.5 V 0.8 +6 +150 40 +85 Min Typ Max 2 200 - - 0 2.0 ...
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... CMOS EEPROM with +85 C; unless otherwise specified. Conditions mA DD(min amb see Figure 9. DD Conditions repeated start Rev. 05 — 25 October 2004 PCF8594C-2 2 C-bus interface Min Typ Max 0.8 - 0.3V DD 0. Min Max ...
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... HD;DAT SU;DAT 2 C-bus. Conditions internal oscillator external clock +85 C amb amb HIGH t LOW 1 2 STOP Rev. 05 — 25 October 2004 PCF8594C-2 2 C-bus interface t HD;STA SU;STA SU;STO MBA705 Min Typ Max 100000 1000000 ...
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... HIGH t LOW 1 2 STOP HIGH t LOW 1 2 STOP A DATA A DATA negative edge SCL 8-bit Rev. 05 — 25 October 2004 PCF8594C-2 2 C-bus interface n x 256 + 1 MBA698 1153 MBA699 P A (1) undefined 1 2 257 clock ( 513 clock ( 1153 clock (4) ...
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... 0.53 1.07 0.36 9.8 6.48 2.54 0.38 0.89 0.23 9.2 6.20 0.021 0.042 0.014 0.39 0.26 0.1 0.015 0.035 0.009 0.36 0.24 REFERENCES JEDEC JEITA MO-001 SC-504-8 Rev. 05 — 25 October 2004 PCF8594C-2 2 C-bus interface 3.60 8.25 10.0 7.62 0.254 3.05 7.80 8.3 0.14 0.32 0.39 0.3 0.01 0.12 0.31 0.33 EUROPEAN ISSUE DATE PROJECTION 99-12-27 03-02-13 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... 0.49 0.25 5.0 4.0 6.2 1.27 0.36 0.19 4.8 3.8 5.8 0.019 0.0100 0.20 0.16 0.244 0.05 0.041 0.014 0.0075 0.19 0.15 0.228 REFERENCES JEDEC JEITA MS-012 Rev. 05 — 25 October 2004 PCF8594C-2 2 8-bit CMOS EEPROM with I C-bus interface detail 1.0 0.7 1.05 0.25 0.25 0.1 0.4 0.6 0.039 0.028 ...
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... C (SnPb process) or below 245 C (Pb-free process) – for all the BGA and SSOP-T packages 9397 750 14221 Product data 512 8-bit CMOS EEPROM with I Rev. 05 — 25 October 2004 PCF8594C-2 2 C-bus interface ). stg(max) © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Product data 512 2.5 mm thick/large packages. parallel to the transport direction of the printed-circuit board; transport direction of the printed-circuit board. Rev. 05 — 25 October 2004 PCF8594C-2 2 8-bit CMOS EEPROM with I C-bus interface 3 350 called small/thin packages. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... DHVQFN, HBCC, HBGA, not suitable HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS [7] PLCC , SO, SOJ suitable LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO, not recommended VSSOP Rev. 05 — 25 October 2004 PCF8594C-2 2 C-bus interface [2] Reflow Dipping [3] suitable not suitable suitable [6] suitable suitable [7][8] ...
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... Product data; initial version (as PCF85xxC-2 family , 9397 750 01773). 9397 750 14221 Product data 512 8-bit CMOS EEPROM with I 6, third paragraph: change ‘high-speed’ to re-written. Rev. 05 — 25 October 2004 PCF8594C-2 2 C-bus interface © Koninklijke Philips Electronics N.V. 2004. All rights reserved ...
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... Licenses Purchase of Philips I Rev. 05 — 25 October 2004 PCF8594C-2 2 C-bus interface 2 C components 2 Purchase of Philips I ...
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... Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 25 October 2004 Document order number: 9397 750 14221 PCF8594C-2 512 8-bit CMOS EEPROM with I 2 C-bus interface ...