MX29LV320CBTC-90G Macronix International Co., MX29LV320CBTC-90G Datasheet
MX29LV320CBTC-90G
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MX29LV320CBTC-90G Summary of contents
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FEATURES GENERAL FEATURES • 4,194,304 2,097,152 x 16 switchable • Sector Structure - 8K-Byte x 8 and 64K-Byte x 63 • Extra 64K-Byte sector for security - Features factory locked and identifiable, and cus- tomer lockable • ...
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The MX29LV320C T/B uses a 2.7V to 3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses ...
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PIN CONFIGURATION 48 TSOP A15 1 A14 2 A13 3 A12 4 A11 5 A10 A19 9 A20 10 WE# 11 RESET WP#/ACC 14 RY/BY# 15 A18 16 A17 ...
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BLOCK DIAGRAM CE# CONTROL OE# INPUT WE# LOGIC RESET# BYTE# ADDRESS LATCH A0-A20 AND BUFFER Q0-Q15/A-1 P/N:PM1188 MX29LV320C T/B PROGRAM/ERASE HIGH VOLTAGE FLASH ARRAY ARRAY SOURCE HV Y-PASS GATE PGM SENSE DATA AMPLIFIER HV PROGRAM DATA LATCH I/O BUFFER 4 ...
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Table 1.a: MX29LV320CT SECTOR GROUP ARCHITECTURE Sector Sector Sector Address Group A20-A12 1 SA0 000000xxx 1 SA1 000001xxx 1 SA2 000010xxx 1 SA3 000011xxx 2 SA4 000100xxx 2 SA5 000101xxx 2 SA6 000110xxx 2 SA7 000111xxx 3 SA8 001000xxx 3 ...
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Sector Sector Sector Address Group A20-A12 11 SA40 101000xxx 11 SA41 101001xxx 11 SA42 101010xxx 11 SA43 101011xxx 12 SA44 101100xxx 12 SA45 101101xxx 12 SA46 101110xxx 12 SA47 101111xxx 13 SA48 110000xxx 13 SA49 110001xxx 13 SA50 110010xxx 13 ...
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Table 1.b: MX29LV320CB SECTOR GROUP ARCHITECTURE Sector Sector Sector Address Group A20-A12 1 SA0 000000000 2 SA1 000000001 3 SA2 000000010 4 SA3 000000011 5 SA4 000000100 6 SA5 000000101 7 SA6 000000110 8 SA7 000000111 9 SA8 000001xxx 9 ...
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Sector Sector Sector Address Group A20-A12 17 SA39 100000xxx 17 SA40 100001xxx 17 SA41 100010xxx 17 SA42 100011xxx 18 SA43 100100xxx 18 SA44 100101xxx 18 SA45 100110xxx 18 SA46 100111xxx 19 SA47 101000xxx 19 SA48 101001xxx 19 SA49 101010xxx 19 ...
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Table 2. BUS OPERATION--1 Operation CE# OE# WE# RE- Read Write (Note Accelerate L H Program Standby VCC X X 0.3V Output Disable Reset Sector Group L H ...
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BUS OPERATION--2 Operation CE# OE# WE# Read Silicon Manufacturer Code Read Silicon MX29LV320CT Read Silicon MX29LV320CB Sector Protect L L Verification Security Sector L L Indicater Bit (Q7) Notes: 1.Code=00h means ...
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REQUIREMENTS FOR READING ARRAY DATA To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array ...
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OUTPUT DISABLE With the OE# input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins high impedance state. RESET# OPERATION The RESET# pin provides a hardware method ...
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It is also possible to determine if the chip is unprotected in the system by writing the Read Silicon ID command. Performing a read operation with A1=VIH, it will produce 00H at data outputs(Q0-Q7) for an unprotected sector ...
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The system accesses the Security Sector through a com- mand sequence (see "Enter Security Sector/Exit Secu- rity Sector Command Sequence"). After the system has written the Enter Security Sector command se-quence, it ...
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LOGICAL INHIBIT Writing is inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle CE# and WE# must be a logical zero while OE logical one. POWER-UP ...
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TABLE 3. MX29LV320C T/B COMMAND DEFINITIONS Command Bus Cycles Addr Data Addr Data Addr Data Addr Read(Note 5) 1 Reset(Note 4) 1 Automatic Select(Note 5) Manufacturer ID Word 4 Byte 4 Device ID Word 4 Byte 4 Security Sector Factory ...
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READING ARRAY DATA The device is automatically set to reading array data af- ter device power-up. No commands are required to re- trieve data. The device is also ready to read array data after completing an Automatic Program or Automatic ...
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Table 3 shows the address and data requirements for the byte/word program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array ...
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SECTOR ERASE COMMANDS The device does not require the system to entirely pre-program prior to executing the Automatic Set-up Sector Erase command and Automatic Sector Erase command. Upon executing the Automatic Sector Erase command, the device will automatically program and ...
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WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/ BY#. Table 5 and the following subsections describe the functions of these bits. Q7, RY/BY#, and ...
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Q7: Data# Polling The Data# Polling bit, Q7, indicates to the host system whether an Automatic Algorithm is in progress or com- pleted, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of ...
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Erase Suspend, but cannot distinguish which sec- tors are selected for erasure. Thus, both status bits are required for sectors and mode information. Refer to Table 5 to compare ...
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Data# Polling or Toggle Bit low ("0"), the device will accept additional sector erase commands. To insure the command has been ac- cepted, the system software should check the status of Q3 prior ...
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Table 6-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set ...
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Table 6-3. CFI Mode: Device Geometry Data Values Description Device size (2 N bytes) Flash device interface code (02=asynchronous x8/x16) Maximum number of bytes in multi-byte write (not supported) Number of erase sector regions Erase Sector Region 1 Information [2E,2D] ...
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Table 6-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address sensitive unlock (0=required, 1= not required) Erase suspend (2= to read and write) Sector protect (N= ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . ..... -65 Ambient Temperature with Power Applied .... ...
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DC CHARACTERISTICS VCC=2.7V~3.6V Para- Description meter ILI Input Load Current (Note 1) ILIT A9 Input Load Current ILO Output Leakage Current ICC1 VCC Active Read Current (Notes 2, 3) ICC2 VCC Active Write Current (Notes ICC3 VCC ...
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SWITCHING TEST CIRCUITS DEVICE UNDER TEST CL 6.2K ohm KEY TO SWITCHING WAVEFORMS WAVEFORM Don't Care, Any Change Permitted SWITCHING TEST WAVEFORMS 3.0V 0.0V P/N:PM1188 MX29LV320C T/B TEST SPECIFICATIONS Test Condition Output Load 1.6K ohm +3.3V Output Load Capacitance,CL (including ...
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AC CHARACTERISTICS TA=-40° 85° C, VCC=2.7V~3.6V Symbol DESCRIPTION tACC Address to output delay tCE Chip enable to output delay tOE Output enable to output delay tDF OE# High to output float(Note1) tOH Output hold time of from the ...
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Figure 1. COMMAND WRITE OPERATION VCC 3V VIH Addresses VIL tAS VIH WE# VIL tOES CE# VIH VIL tCS OE# VIH VIL VIH Data VIL P/N:PM1188 MX29LV320C T/B ADD Valid tAH tWP tCWC tCH tDS tDH DIN 31 tWPH REV. ...
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READ/RESET OPERATION Figure 2. READ TIMING WAVEFORMS VIH Addresses VIL VIH CE# VIL VIH WE# VIL VIH OE# VIL HIGH Z VOH Outputs VOL P/N:PM1188 MX29LV320C T/B tRC ADD Valid tCE tOEH tOE tACC DATA Valid 32 tDF tOH HIGH ...
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AC CHARACTERISTICS Parameter Description tREADY1 RESET# PIN Low (During Automatic Algorithms) to Read or Write (See Note) tREADY2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write (See Note) tRP1 RESET# Pulse Width (During Automatic Algorithms) tRP2 RESET# ...
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ERASE/PROGRAM OPERATION Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM Erase Command Sequence(last two cycle) tWC 2AAh Address CE# tGHWL OE# tWP WE# tCS Data RY/BY# tVCS VCC Note: SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation ...
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Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART P/N:PM1188 MX29LV320C T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 10H Address ...
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Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM Erase Command Sequence(last two cycle) tWC 2AAh Address CE# tCH tGHWL OE# tWP WE# tCS tDS tDH 55h Data RY/BY# tVCS VCC Note: SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see ...
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Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART P/N:PM1188 MX29LV320C T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 80H Address 555H Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data 30H Sector ...
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Figure 8. ERASE SUSPEND/RESUME FLOWCHART P/N:PM1188 MX29LV320C T/B START Write Data B0H ERASE SUSPEND NO Toggle Bit checking Q6 not toggled YES Read Array or Program Reading or NO Programming End YES Write Data 30H ERASE RESUME Continue Erase Another ...
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Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS Program Command Sequence(last two cycle) tWC 555h Address CE# tGHWL OE# tWP WE# tCS tDS tDH Data RY/BY# tVCS VCC Note: 1.PA=Program Address, PD=Program Data, DOUT is the true data the program address Figure ...
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Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM 555 for program 2AA for erase Address tWC tWH WE# tGHEL OE# tCP CE# tWS tDS Data tRH RESET# RY/BY# Notes: 1. PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to ...
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Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART Increment Address P/N:PM1188 MX29LV320C T/B START Write Data AAH Address 555H Write Data 55H Address 2AAH Write Data A0H Address 555H Write Program Data/Address Data Poll from system No Verify Data OK ? YES ...
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SECTOR GROUP PROTECT/CHIP UNPROTECT Figure 13. Sector Group Protect/Chip Unprotect Waveform (RESET# Control) VID VIH RESET# SA, A6 A1, A0 Sector Group Protect or Chip Unprotect Data 60h 1us CE# WE# OE# Note: 1. For sector group protect A6=0, A1=1, ...
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Figure 14. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH RESET#=VID START PLSCNT=1 RESET#=VID Wait 1us No First Write Temporary Sector Unprotect Mode Cycle=60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6=0, A1=1, A0=0 Wait ...
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Table 7. TEMPORARY SECTOR GROUP UNPROTECT Parameter Std. Description tVIDR VID Rise and Fall Time (See Note) tRSP RESET# Setup Time for Temporary Sector Unprotect Note: Not 100% tested Figure 15. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS 12V RESET ...
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Figure 16. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART Temporary Sector Unprotect Completed(Note 2) Notes : 1. All protected sectors are temporary unprotected. VID=11.5V~12.5V. (if WP#/ACC=VIL, outermost boot sectors will remain protected) 2. All previously protected sectors are protected again. P/N:PM1188 MX29LV320C ...
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Figure 17. SILICON ID READ TIMING WAVEFORM VCC 3V VID ADD VIH A9 VIL VIH ADD A0 VIL tACC A1 VIH VIL VIH ADD VIL CE# VIH VIL tCE VIH WE# VIL VIH OE# VIL VIH DATA VIL Q0-Q7 P/N:PM1188 ...
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WRITE OPERATION STATUS Figure 18. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) tRC Address tACC tCE CE# tCH tOE OE# tOEH WE# Q7 Q0-Q6 tBUSY RY/BY# Note: VA=Valid address. Figure shows are first status cycle after command sequence, last status ...
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Figure 19. Data# Polling Algorithm No Notes: 1. VA=valid address for programming or erasure should be rechecked even Q5="1" because Q7 may change simultaneously with Q5. P/N:PM1188 MX29LV320C T/B START Read Q7~Q0 Add (1) Yes Q7 ...
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Figure 20. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) tRC Address VA tACC tCE CE# tCH tOE OE# tOEH WE# Q6/Q2 tBUSY RY/BY# Note: VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last ...
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Figure 21. Toggle Bit Algorithm NO Complete, Write Reset Command Notes: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1". P/N:PM1188 MX29LV320C ...
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Figure 22. Q6 versus Q2 Enter Embedded Erase Erasing Suspend Erase WE Note: The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended P/N:PM1188 MX29LV320C T/B Enter ...
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AC CHARACTERISTICS WORD/BYTE CONFIGURATION (BYTE#) Parameter Description JEDEC Std tELFL/tELFH CE# to BYTE# Switching Low or High tFLQZ BYTE# Switching Low to Output HIGH Z tFHQV BYTE# Switching High to Output Active Figure 23. BYTE# TIMING WAVEFORM FOR READ OPERATIONS ...
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RECOMMENDED OPERATING CONDITIONS At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) ...
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ERASE AND PROGRAMMING PERFORMANCE(1) PARAMETER Sector Erase Time Chip Erase Time Byte Programming Time Word Program Time Chip Programming Time Byte Mode Word Mode Accelerated Byte/Word Program Time Erase/Program Cycles Note: 1.Not 100% Tested, Excludes external system level over head. ...
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... ORDERING INFORMATION PART NO. ACCESS TIME (ns) MX29LV320CTTC-70 70 MX29LV320CBTC-70 70 MX29LV320CTTI-70 70 MX29LV320CBTI-70 70 MX29LV320CTTC-90 90 MX29LV320CBTC-90 90 MX29LV320CTTI-90 90 MX29LV320CBTI-90 90 MX29LV320CTXBC-70 70 MX29LV320CBXBC-70 70 MX29LV320CTXEC-70 70 MX29LV320CBXEC-70 70 MX29LV320CTXBI-70 70 MX29LV320CBXBI-70 70 MX29LV320CTXEI-70 70 MX29LV320CBXEI-70 70 MX29LV320CTXBC-90 90 MX29LV320CBXBC-90 90 MX29LV320CTXEC-90 90 MX29LV320CBXEC-90 90 MX29LV320CTXBI-90 90 MX29LV320CBXBI-90 90 MX29LV320CTXEI-90 90 MX29LV320CBXEI-90 90 P/N:PM1188 MX29LV320C T/B Ball Pitch/ PACKAGE Ball Size - 48 Pin TSOP - 48 Pin TSOP - 48 Pin TSOP ...
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... PART NO. ACCESS TIME (ns) MX29LV320CTTC-70G 70 MX29LV320CBTC-70G 70 MX29LV320CTTI-70G 70 MX29LV320CBTI-70G 70 MX29LV320CTTC-90G 90 MX29LV320CBTC-90G 90 MX29LV320CTTI-90G 90 MX29LV320CBTI-90G 90 MX29LV320CTXBC-70G 70 MX29LV320CBXBC-70G 70 MX29LV320CTXEC-70G 70 MX29LV320CBXEC-70G 70 MX29LV320CTXBI-70G 70 MX29LV320CBXBI-70G 70 MX29LV320CTXEI-70G 70 MX29LV320CBXEI-70G 70 MX29LV320CTXBC-90G 90 MX29LV320CBXBC-90G 90 MX29LV320CTXEC-90G 90 MX29LV320CBXEC-90G 90 MX29LV320CTXBI-90G 90 MX29LV320CBXBI-90G 90 MX29LV320CTXEI-90G 90 MX29LV320CBXEI-90G 90 P/N:PM1188 MX29LV320C T/B Ball Pitch/ PACKAGE Ball Size - 48 Pin TSOP - 48 Pin TSOP - 48 Pin TSOP - 48 Pin TSOP ...
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PART NAME DESCRIPTION 320 P/N:PM1188 MX29LV320C T OPTION: G: Lead-free package R: Restricted VCC (3.0V~3.6V) Q: Restricted VCC (3.0V~3.6V) with Lead-free package blank: normal SPEED: 70: 70ns 90: 90ns TEMPERATURE RANGE: ...
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PACKAGE INFORMATION P/N:PM1188 MX29LV320C T/B 58 REV. 1.0, AUG. 02, 2005 ...
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P/N:PM1188 MX29LV320C T/B 59 REV. 1.0, AUG. 02, 2005 ...
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P/N:PM1188 MX29LV320C T/B 60 REV. 1.0, AUG. 02, 2005 ...
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REVISION HISTORY Revision No. Description 1.0 1. Removed "Preliminary" 2. Added "Pb-free devices are RoHS Compliant" P/N:PM1188 MX29LV320C T/B Page Date AUG/02/2005 REV. 1.0, AUG. 02, 2005 ...
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... MX29LV320C T/B MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. ...