W83877ATF Winbond, W83877ATF Datasheet
W83877ATF
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W83877ATF Summary of contents
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... W83877ATF WINBOND I/O ...
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... W83877ATF Data Sheet Revision History Pages 1 n.a. 07/29/97 1,3,6,49,50,98,140, 2 04/10/98 141,142,170 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS ...
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... FEATURES ..........................................................................................................................2 1.0 PIN CONFIGURATION ...............................................................................................4 1.0 PIN DESCRIPTION ........................................................................................................................5 1.1 HOST INTERFACE .........................................................................................................................5 1.2 SERIAL PORT INTERFACE ...........................................................................................................7 1.3 MULTI-MODE PARALLEL PORT ..................................................................................................9 1.4 FDC INTERFACE..........................................................................................................................14 2.0 FDC FUNCTIONAL DESCRIPTION........................................................................16 2.1 W83877ATF FDC...........................................................................................................................16 2.2 REGISTER DESCRIPTIONS .........................................................................................................28 3.0 UART PORT................................................................................................................39 3.1 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART A, UART B)..................39 3.2 REGISTER ADDRESS...................................................................................................................40 3.3 INFRARED PORT .........................................................................................................................49 4.0 PARALLEL PORT.....................................................................................................82 4.1 PRINTER INTERFACE LOGIC .....................................................................................................82 4.2 ENHANCED PARALLEL PORT (EPP) .........................................................................................84 4 ...
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... UART/PARALLEL....................................................................................................................... 175 10.3 PARALLEL PORT ....................................................................................................................... 177 11.0 APPLICATION CIRCUITS....................................................................................183 11.1 PARALLEL PORT EXTENSION FDD ........................................................................................ 183 11.2 PARALLEL PORT EXTENSION 2FDD....................................................................................... 184 11.3 FOUR FDD MODE...................................................................................................................... 184 12.0 ORDERING INFORMATION ...............................................................................185 13.0 HOW OT READ THE TOP MARKING ...............................................................185 14.0 PACKAGE DIMENSIONS .....................................................................................186 Publication Release Date: July 1997 - II - W83877ATF Version 0.50 ...
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... W83877ATF also has auto power management to reduce power consumption. The Serial IRQ for PCI architecture is supported, ISA IRQs (IRQ1~IRQ15) can be cascaded into one IRQ pin. W83877ATF also features ISA bus IRQ sharing and allows two or more devices to share the same IRQ. ...
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... Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs MIDI compatible Fully programmable serial-interface characteristics 8-bit characters Even, odd or no parity bit generation/detection 1, 1 stop bits generation PC97 Hardware Design Guide TM driver - 2 - W83877ATF Publication Release Date: April 1998 Version 0.51 ...
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... All hardware power-on settings have internal pull-up or pull-down resistors as default value Full 16-bit address decode (UART B pin option) PNF pin (Printer-Not-Floppy pin) for distinguishing printer port connection --- FDD or Printer; unique for notebook application of external floppy through printer port Package: 100-pin QFP (W83877ATF), and also 100-pin TQFP (W83877ATD Windows 95 and Windows 98 ...
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... W83877ATF DSRB ...
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... System address bus bit 11, when 16-bit address decoder is set to logic 0 in which CR16.bit6 ( System address bus enable. t CPU I/O read signal. CPU I/O write signal. DMA acknowledge signal A. DMA request signal A. 8t DMA request signal B. 12t DMA acknowledge signal W83877ATF FUNCTION ). Publication Release Date: April 1998 Version 0.51 ...
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... Interrupt request signal E. 12t Interrupt request signal F. 12t Interrupt request signal G. 12t DMA request signal channel D. 12t IR module mode select 2. 12t PCI clock input when the serial IRQ function is selected W83877ATF FUNCTION CR16.bit7 Publication Release Date: April 1998 Version 0.51 ...
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... Data Carrier Detect. An active low indicates the modem or data t set has detected a data carrier. System address bus bit 14, when 16-bit address decoder is t selected. Ring Indicator. An active low indicates that a ring signal is being t received by the modem or data set W83877ATF FUNCTION FUNCTION Publication Release Date: April 1998 Version 0.51 ...
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... During power-on reset, this pin is pulled up internally and is t defined as PPNPCVS, which provides the power-on value for CR16 bit 2 (PNPCVS). A 4.7 k intending to pull down at power-on reset W83877ATF FUNCTION is recommended when is recommended when Publication Release Date: April 1998 Version 0.51 ...
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... This pin is for the Extension FDD B; its functions are the same as those of the DSB pin. EXTENSION 2FDD MODE: DSB2 12 This pin is for Extension FDD A and B; the function of this pin is the same as that of the DSB pin W83877ATF FUNCTION A 4 recommended when FUNCTION Publication Release Date: April 1998 Version 0.51 ...
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... EXTENSION FDD MODE: HEAD2 12 This pin is for Extension FDD B; its function is the same as that of the HEADpin. EXTENSION 2FDD MODE: HEAD2 12 This pin is for Extension FDD A and B; its function is the same as that of the HEAD pin W83877ATF FUNCTION Publication Release Date: April 1998 Version 0.51 ...
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... EXTENSION FDD MODE: RWC2 12 This pin is for Extension FDD B; its function is the same as that of the RWC pin. EXTENSION 2FDD MODE: RWC2 12 This pin is for Extension FDD A and B; its function is the same as that of the RWC pin W83877ATF FUNCTION Publication Release Date: April 1998 Version 0.51 ...
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... TRAK0 pin. This pin is pulled high internally. EXTENSION. 2FDD MODE: TRAK02 t This pin is for Extension FDD A and B; the function of this pin is the same as TRAK0 pin. This pin is pulled high internally W83877ATF FUNCTION Publication Release Date: April 1998 Version 0.51 ...
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... Parallel port data bus bit 5. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. EXTENSION FDD MODE: No Connection This pin is a tri-state output. EXTENSION 2FDD MODE: No Connection This pin is a tri-state output W83877ATF FUNCTION Publication Release Date: April 1998 Version 0.51 ...
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... Track 0. This schmitt input from the disk drive is active low when the head is positioned over the outermost track. This input pin is pulled up internally by an approximately 1K ohm resistor. The resistor can be disabled by bit 4 of CR6 (FIPURDWN W83877ATF FUNCTION FUNCTION Publication Release Date: April 1998 Version 0.51 ...
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... Head select. This open drain output determines which disk drive head is active. Logic 1 = side 0 Logic 0 = side 1 Direction of the head step motor. An open drain output. Logic 1 = outward motion Logic 0 = inward motion +5 power supply for the digital circuitry Ground - 15 - W83877ATF Publication Release Date: April 1998 Version 0.51 ...
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... FDC FUNCTIONAL DESCRIPTION 2.1 W83877ATF FDC The floppy disk controller of the W83877ATF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to compatible values. The FIFO provides better system performance in multi-master systems. The digital data separator supports up to data rate 1 M bits/sec bits/sec. ...
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... The perpendicular mode requires a 1 Mbps data rate for the FDC. At this data rate the FIFO eases the host interface bottleneck due to the speed of data transfer to or from the disk. disabled, and command parameters must be sent mode, a pseudo read is performed disks, and can also read and Publication Release Date: April 1998 - 17 - W83877ATF and , Version 0.51 ...
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... Tape Drive The W83877ATF supports standard tape drives (1 Mbps, 500 Kbps, 250 Kbps) and new fast tape drive (2M bps). 2.1.7 FDC Core The W83877ATF FDC is capable of performing twenty commands. Each command is initiated by a multi-byte transfer from the microprocessor. The result can also be a multi-byte transfer back to the microprocessor ...
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... R ---------------------- R ------------------------ R ---------------------- N ------------------------ HDS - 19 - W83877ATF D1 D0 REMARKS 1 0 Command codes DS1 DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: April 1998 ...
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... R ---------------------- R ------------------------ R ---------------------- N ------------------------ HDS - 20 - W83877ATF D1 D0 REMARKS 0 0 Command codes DS1 DS 0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: April 1998 ...
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... R ------------------------ R ---------------------- N ------------------------ HDS - 21 - W83877ATF D1 D0 REMARKS 1 0 Command codes DS1 DS0 Sector ID information prior to command execution Data transfer between the FDD and system; FDD reads contents of all cylinders from index hole to EOT Status information after ...
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... HDS MFM HDS - 22 - W83877ATF D1 D0 REMARKS 1 0 Command codes DS1 DS0 The first correct ID information on the cylinder is stored in Data Register Status information after command execution Disk status after the command has been completed D1 D0 ...
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... HDS - 23 - W83877ATF D1 D0 REMARKS 0 0 Command codes 0 0 Enhanced controller D1 D0 REMARKS 0 1 Command codes DS1 DS0 Sector ID information prior to Command execution Data transfer between the FDD and system Status information after ...
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... R ------------------------ R ---------------------- N ------------------------ HDS - 24 - W83877ATF D1 D0 REMARKS 0 1 Command codes DS1 DS0 Sector ID information prior to command execution Data transfer between the FDD and system Status information after command execution Sector ID information after command execution Publication Release Date: April 1998 ...
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... W83877ATF D1 D0 REMARKS 0 1 Command codes DS1 DS0 Bytes/Sector Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters Status information after command execution D1 D0 REMARKS 1 1 Command codes DS1 DS0 Head retracted to Track 0 ...
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... FIFOTHR ----| EFIFO POLL HDS - 26 - W83877ATF D1 D0 REMARKS 1 1 Command codes D1 D0 REMARKS 1 1 Command codes DS1 DS0 Head positioned over proper cylinder on diskette D1 D0 REMARKS 1 1 Configure information 0 0 Internal registers written ...
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... LOCK HDS W83877ATF D1 D0 REMARKS 1 0 Registers placed in FIFO GAP REMARKS 1 0 Command code GAP REMARKS 0 0 Command code REMARKS 0 0 Command code DS1 ...
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... Register Descriptions There are several status, data, and control registers in W83877ATF. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 base address + 5 base address + 7 2.2.1 Status Register A (SA Register) (Read base address + 0) This register is used to monitor several disk interface pins in PS/2 and Model 30 modes. In PS/2 ...
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... This bit indicates the complement of TRAK0 input. HEAD (Bit 3): This bit indicates the value of HEAD output. 0 side 1 1 side 0 INDEX (Bit 2): This bit indicates the complement of INDEX output DIR WP INDEX HEAD TRAK0 STEP F/F INIT PENDING - 29 - W83877ATF DRQ Publication Release Date: April 1998 Version 0.51 ...
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... MOT EN A (Bit 0) This bit indicates the complement of the MOA output pin. In PS/2 Model 30 mode, the bit definitions for this register are as follows W83877ATF MOT EN A MOT RDATA Toggle WDATA Toggle Drive SEL0 Publication Release Date: April 1998 Version 0.51 ...
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... DSD (Bit 1): 0 Drive D has been selected 1 Drive D has not been selected DSC (Bit 0): 0 Drive C has been selected 1 Drive C has not been selected W83877ATF DSC DSD WE F/F RDATA F/F WD F/F DSA DSB DRV2 Publication Release Date: April 1998 Version 0.51 ...
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... W83877ATF 01 select drive B 10 select drive C 11 select drive D Tape sel 0 Tape sel 1 Tape Sel 0 Tape Sel 1 Floppy boot drive 0 Floppy boot drive 1 Drive type ID0 Drive type ID1 Media ID0 Media ID1 Publication Release Date: April 1998 ...
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... DATA INPUT/OUTPUT, (DIO). If DIO= HIGH then transfer is from Data Register to the processor. If DIO = LOW then transfer is from processor to Data Register. Request for Master (RQM). A high on this bit indicates Data Register is ready to send or receive data to or from the processor W83877ATF None Publication Release Date: April 1998 Version 0 ...
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... PRECOMPENSATION DELAY 250K - 1Mbps Default Delays 41.67 nS 83.34 nS 125.00 nS 166.67 nS 208.33 nS 250.00 nS 125 nS 125 nS 125 nS 41. W83877ATF DRATE0 DRATE1 PRECOMP0 PRECOMP1 PRECOMP2 POWER DOWN S/W RESET 2 Mbps Tape drive Default Delays 20.8nS 41.17nS 62.5nS 83.3nS 104.2nS 125.00nS 0.00nS (disabled) Publication Release Date: April 1998 ...
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... This register stores data, commands, and status information. Data bytes are passed through the data register to program or obtain results after a command. In the W83877ATF, this register defaults to FIFO disabled mode after reset. The FIFO can change its value and enable its operation through the CONFIGURE command. ...
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... During execution of the read data or scan command 0 No error Not used. This bit is always W83877ATF US0 Unit Select 0 US1 Unit Select 1 HD Head Address TS Two-Side TO Track 0 RY Ready WP Write Protected FT Fault Publication Release Date: April 1998 Version 0.51 ...
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... Reserved for the hard disk controller x During a read of this register, these bits are in tri-state DSKCHG W83877ATF HIGH DENS DRATE0 DRATE1 DSKCHG DRATE0 DRATE1 NOPREC DMAEN DSKCHG Publication Release Date: April 1998 Version 0.51 ...
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... This bit indicates no precompensation. It has no function and can be set by software. DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC Reserved - 38 - W83877ATF 0 DRATE0 DRATE1 DRATE0 DRATE1 NOPREC Publication Release Date: April 1998 Version 0.51 ...
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... The UARTs have a FIFO mode to reduce the number of interrupts presented to the CPU. In each UART, there are 16-byte FIFOs for both receive and transmit mode. W83877ATF side, capability, and a processor interrupt system that may ...
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... CTS DSR RI Falling Toggling Toggling Edge (TCTS) (TDSR) (FERI) Bit 0 Bit 1 Bit 2 Bit 0 Bit 1 Bit 2 Bit 8 Bit 9 Bit W83877ATF Data RX Data RX Data Bit 3 Bit 4 Bit 5 TX Data TX Data TX Data Bit 3 Bit 4 Bit 5 HSR 0 0 Interrupt Enable ...
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... Data length select bit 0 (DLS0) Data length select bit 1(DLS1) Multiple stop bits enable (MSBE) Parity bit enable (PBE) Even parity enable (EPE) Parity bit fixed enable (PBFE) Set silence enable (SSE) Baudrate divisor latch access bit (BDLAB W83877ATF Publication Release Date: April 1998 Version 0.51 ...
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... RBR Data ready (RDR) Overrun error (OER) Parity bit error (PBER) No stop bit error (NSER) Silent byte detected (SBD) Transmitter Buffer Register empty (TBRE) Transmitter Shift Register empty (TSRE) RX FIFO Error Indication (RFEI) Publication Release Date: April 1998 - 42 - W83877ATF Version 0.51 ...
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... Bit 0: This bit controls the DTR output. The value of this bit is inverted and output to DTR . Data terminal ready (DTR) Request to send (RTS) Loopback RI input IRQ enable Internal loopback enable CTS, Loopback RI input ( bit 2 of HCR) DCD. Publication Release Date: April 1998 - 43 - W83877ATF Version 0.51 ...
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... Bit 0: TCTS. This bit indicates that the CTS pin has changed state after HSR was read by the CPU CTS toggling (TCTS) DSR toggling (TDSR) RI falling edge (FERI) DCD toggling (TDCD) Clear to send (CTS) Data set ready (DSR) Ring indicator (RI) Data carrier detect (DCD) Publication Release Date: April 1998 - 44 - W83877ATF modem, Version 0.51 ...
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... Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before other bits of UFR are programmed FIFO enable Receiver FIFO reset Transmitter FIFO reset DMA mode select Reserved Reserved RX interrupt active level (LSB) RX interrupt active level (MSB W83877ATF Publication Release Date: April 1998 Version 0.51 ...
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... RX FIFO. TBR empty 1. TCTS = 1 2. TDSR = 1 3. FERI = 1 4. TDCD = 1 Publication Release Date: April 1998 - 46 - W83877ATF Clear Interrupt - Read USR 1. Read RBR 2. Read RBR until FIFO data under active level Read RBR 1. Write data into TBR 2 ...
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... RBR data ready interrupt enable (ERDRI) TBR empty interrupt enable (ETBREI) UART receive status interrupt enable (EUSRI) Handshake status interrupt enable (EHSRI W83877ATF 16 -1. The output frequency of Publication Release Date: April 1998 Version 0.51 ...
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... Decimal divisor used to Percent error difference between generate 16X clock 2304 1536 1047 857 768 384 192 Note 1 4 Note 1 2 Note 1 1 Note 2 1 Publication Release Date: April 1998 - 48 - W83877ATF desired and actual ** ** 0.18% 0.099 0.53 Version 0.51 ...
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... UART Registers *Set 2~7 are Advanced UART Registers is, UART A and UART B. The second serial port, Also, a superior traditional UART B function can be All in one Reg to Select SSR Set 2 Set 3 Set 4 Set 5 Set 6 Set 7 Publication Release Date: April 1998 - 49 - W83877ATF Version 0.51 ...
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... D_CHSW (DMA Channel Swap, in Set2.Reg2.Bit3) is set and the TX/RX DMA channel is swapped. Note that two DMA channels are defined in config register disables DMA channel DMA channel is enabled and TX DMA channel is disabled, then the single DMA channel will be selected. W83877ATF (SSR), Sets Description Register Description ...
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... Bit 0: ERBRI - Enable RDR (Receiver Buffer Register) Interrupt Write to 1, enable receiver buffer register interrupt EHSRI ETXTHI EDMAI EHSRI Publication Release Date: April 1998 - 51 - W83877ATF EUSRI ETBREI ERDRI EUSRI/ ETBREI ERXTHI TXURI IR, are described Version 0.51 ...
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... Clear to 0 when this register is read. Remote Controller mode IID2 TXTH_I DMA_I HS_I are defaulted to inactive except set IR Handshake Status Publication Release Date: April 1998 - 52 - W83877ATF IID1 IID0 IP USR_I/ TXEMP_I RXTH_I FEND_I Version 0.51 ...
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... Bit 4 Bit TXF_RST RXF_RST EN_FIFO TXFTL1 TXFTL0 0 TXF_RST RXF_RST EN_FIFO (MSB) (LSB FIFO Threshold Level (FIFO Size: 16-byte) (FIFO Size: 32-byte Publication Release Date: April 1998 - 53 - W83877ATF Bit 2 Bit 1 Bit Version 0.51 ...
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... XLOOP EN_IRQ TX_WT Publication Release Date: April 1998 - 54 - W83877ATF Selected Set Set 0 Set1 Set 2 Set 3 Set 4 Set 5 Set 6 Set LP_RI RTS DTR EN_DMA RTS DTR 0 ...
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... TX FIFO. This is in order to avoid Underrun. Other modes: Not used. Selected Mode Advanced UART Low speed MIR (0.576M bps) Advanced ASK-IR Advanced SIR High Speed MIR (1.152M bps) FIR (4M bps) Consumer IR Reserved Publication Release Date: April 1998 - 55 - W83877ATF end,. In Version 0.51 ...
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... IrDA version 1.1. When this bit is set to 1, the decoder of receiver will be aborted, and a frame end signal is set TBRE SBD NSER TBRE MX_LEX PHY_ERR CRC_ERR Publication Release Date: April 1998 - 56 - W83877ATF PBER OER RDR OER RDR Version 0.51 ...
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... CTS TDCD DSR CTS TDCD Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit 3 RX_BSY/ LST_FE/ S_FEND RX_IP RX_PD Publication Release Date: April 1998 - 57 - W83877ATF FERI TDSR TCTS FERI TDSR TCTS Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit 0 0 LB_SF RX_TO Version 0 ...
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... Set to 1 that indicates one or more than one frame end still stay in receiver FIFO. MIR, FIR, Remote IR modes: Bit 0: RX_TO - Receiver FIFO or Frame Status FIFO time-out Set to 1 when receiver FIFO or frame status FIFO occurs time-out W83877ATF Publication Release Date: April 1998 - 58 - Version 0.51 ...
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... SIR/ASK-IR. 4.3.3.2 Set1.Reg 2~7 These registers are defined the same as the Set 0 registers. Register Description Advanced Mode Legacy Mode DIS_BACK=0 DIS_BACK=× Bit 7~5 Bit Bit 2, 3 Publication Release Date: April 1998 - 59 - W83877ATF - Bit Version 0.51 ...
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... If using signal DMA channel in MIR/FIR mode, then the DMA channel can be swapped. D_CHSW Write to 1 enables output data during the ALOOP=1. Register Description - Bit 5 Bit 4 Bit 3 EN_LOUT D_CHSW ALOOP DMA Channel Selected 0 Receiver (Default) 1 Transmitter - 60 - W83877ATF Bit 2 Bit 1 Bit 0 DMATHL DMA_F ADV_SL Publication Release Date: April 1998 Version 0.51 ...
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... No effect on DMA request. . Write it to select other register Set. Bit 5 Bit 4 Bit 3 SSR5 SSR4 SSR3 Bit 5 Bit 4 Bit 3 PR_DIV1 PR_DIV0 RX_FSZ1 RX_FSZ0 TX_FSZ1 TXFSZ0 W83877ATF RX FIFO Threshold (16/32-Byte Bit 2 Bit 1 Bit 0 SSR2 SRR1 SRR0 Bit 2 Bit 1 Bit Set1 ...
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... Max. Baud Rate 13.0 115.2K bps 1.625 921.6K bps 6.5 230.4K bps 1 1.5M bps RX FIFO Size 16-Byte 32-Byte Reserved TX FIFO Size 16-Byte 32-Byte Reserved Bit 5 Bit 4 Bit 3 TXFD5 TXFD4 TXFD3 Publication Release Date: April 1998 - 62 - W83877ATF Bit 2 Bit 1 Bit 0 TXFD2 TXFD1 TXFD1 Version 0.51 ...
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... Reg1 - Mapped UART Control Register (MP_UCR) Read only. Reading this register that returns UART Control Register value of Set 0. Bit 5 Bit 4 Bit 3 RXFD5 RXFD4 RXFD3 Register Description - - - - Publication Release Date: April 1998 - 63 - W83877ATF Bit 2 Bit 1 Bit 0 RXFD2 RXFD1 RXFD1 Version 0.51 ...
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... Write it to select other register Set. Bit 5 Bit 4 Bit 3 SSR5 SSR4 SSR3 Register Description Bit 5 Bit 4 Bit IR_MSL1 IR_MSL0 TMR_TST EN_TMR W83877ATF Bit 2 Bit 1 Bit 0 SSR2 SRR1 SRR0 ms. The Bit 2 Bit 1 Bit Publication Release Date: April 1998 Version 0.51 ...
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... Bit 5 Bit 4 Bit 3 SSR5 SSR4 SSR3 Bit 5 Bit 4 Bit 3 bit 5 bit 4 bit3 bit 12 bit W83877ATF Bit 2 Bit 1 Bit 0 SSR2 SRR1 SRR0 Bit 2 Bit 1 Bit 0 bit 2 bit 1 bit bit 10 bit 9 bit Publication Release Date: April 1998 ...
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... FCBLL/FCBHL is loaded to advanced baud rate divisor latch (ADBLL/ADBHL). Bit 5 Bit 4 Bit 3 bit 5 bit 4 bit bit 12 bit Register Description Publication Release Date: April 1998 - 66 - W83877ATF Bit 2 Bit 1 Bit 0 bit 2 bit 1 bit bit 10 bit 9 bit Version 0.51 ...
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... Bit 3 - FC_DSW Next Mode After Flow Control Occurred Receiver Channel Transmitter Channel Bit 5 Bit 4 Bit 3 SSR5 SSR4 SSR3 Publication Release Date: April 1998 - 67 - W83877ATF Bit 2 Bit 1 Bit 0 EN_FD EN_BRFC EN_FC Bit 2 Bit 1 Bit 0 SSR2 SRR1 SRR0 ...
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... Reset Value 0 0 Bit 5 Bit 4 Bit 3 FEND_M AUX_RX - Status FIFO Threshold Level 2 4 Bit 5 Bit 4 Bit 3 - MX_LEX PHY_ERR CRC_ERR RX_OV Publication Release Date: April 1998 - 68 - W83877ATF Bit 2 Bit 1 Bit 0 - IRHSSL IR_FULL Bit 2 Bit 1 Bit 0 FSF_OV Version 0.51 ...
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... RFLFH will pop-up another frame status and frame length if FSFDR=1 (Set5.Reg4.Bit7). Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit Bit 12 Bit Publication Release Date: April 1998 - 69 - W83877ATF Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit Bit 10 Bit 9 Bit Version 0.51 ...
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... SHDM_N - ASK-IR Demodulation Disable SHDM_N 0 1 Register Description - - - Bit 5 Bit 4 Bit 3 - INV_CRC DIS_CRC Modulation Mode SOUT modulate 500K Hz Square Wave Re-rout SOUT Demodulation Mode Demodulation 500K Hz Re-rout SIN Publication Release Date: April 1998 - 70 - W83877ATF Bit 2 Bit 1 Bit Version 0.51 ...
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... CRC 32-bit CRC Bit 5 Bit 4 Bit 3 - M_PW4 M_PW3 MIR Pulse Width MIR Output Width (1.152M bps 20.83 ns 41.66 (==20.83*2) ns 83.32 (==41.66*2) ns ... 20.83 ... 645 ns Publication Release Date: April 1998 - 71 - W83877ATF Bit 2 Bit 1 Bit 0 M_PW2 M_PW1 M_PW0 (0.576M bps 41.66 ns ... 41.66 ... 1290 ns Version 0.51 ...
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... UART 1.6 us 1.6 us Bit 5 Bit 4 Bit 3 SSR5 SSR4 SSR3 Bit 5 Bit 4 Bit 3 M_FG1 M_FG0 F_FL3 Publication Release Date: April 1998 - 72 - W83877ATF Bit 2 Bit 1 Bit 0 S_PW2 S_PW1 S_PW0 Bit 2 Bit 1 Bit 0 SSR2 SRR1 SRR0 Bit 2 Bit 1 ...
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... Beginning Flag Number Reserved 1 2 (Default Reserved Beginning Flag Number Reserved (Default Reserved Publication Release Date: April 1998 - 73 - W83877ATF Version 0.51 ...
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... Bit 4~0: RX_FSL4~0 - Receiver Frequency Select 4~0. Select the receiver operation frequency. Register Description Bit 5 Bit 4 Bit 3 RX_FR0 RX_FSL4 RX_FSL3 RX_FSL2 RX_FSL1 RX_FSL0 Publication Release Date: April 1998 - 74 - W83877ATF Bit 2 Bit 1 Bit Version 0.51 ...
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... Note that the other non-defined values are reserved. RX_FR2~0 (Low Frequency) 010 Max. Min. Max. 29.6 24.7 31.7 32.0 26.7 34.3 33.3 27.8 35.7 34.0 28.4 36.5 35.6 29.6 38.1 36.4 30.3 39.0 37.2 31.0 39.8 38.1* 31.7 40.8 39.0 32.5 41.8 41.0 34.2 44.0 42.1 35.1 45.1 43.2 36.0 46.3 45.7 38.1 49.0 47.1 39.2 50.4 48.5 40.4 51.9 50.0 41.7 53.6 51.6 43.0 55.3 55.2 46.0 59.1 57.1 47.6 61.2 61.5 51.3 65.9 RX_FR2~0 (High Frequency) 001 Min. 355.6 380.1 410.3 Publication Release Date: April 1998 - 75 - W83877ATF 011 Min. Max. 23.4 34.2 25.3 36.9 26.3 38.4 26.9 39.3 28.1 41.0 28.7 42.0 29.4 42.9 30.1 44.0 30.8 45.0 32.4 47.3 33.2 48.6 34.1 49.9 36.1 52n.7 37.2 54.3 38.3 56.0 39.5 57.7 40.7 59.6 43.6 63.7 45.1 65.9 48.6 71.0 Max. 457.1 489.8 527.4 Version 0.51 ...
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... Bit 5 Bit 4 Bit Low Frequency 10.6 s Low Frequency 30K Hz 31K HZ ... 56K Hz Publication Release Date: April 1998 - 76 - W83877ATF 101 110 685.6 384.0 738.5 Bit 2 Bit 1 Bit High Frequency 0.7 s 0.8 s 0.9 s 1.0 s Version 0.51 ...
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... Bit 4: Reserved, write 0. High Frequency 400K Hz 450K Hz 480K Hz Bit 5 Bit 4 Bit 3 RXCFS - TX_CFS (Number of bits Bit value Selected Frequency 30K ~ 56K Hz 400K ~ 480K Hz Publication Release Date: April 1998 - 77 - W83877ATF Bit 2 Bit 1 Bit 0 RX_DM TX_MM1 TX_MM0 Version 0.51 ...
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... Reserved. Bit 5 Bit 4 Bit 3 Bit 5 Bit 4 Bit Bit 5 Bit 4 Bit 3 - AIR_SL2 AIR_SL1 AIR_SL0 Publication Release Date: April 1998 - 78 - W83877ATF Bit 2 Bit 1 Bit 0 Bit 2 Bit 1 Bit Bit 2 Bit 1 Bit Version 0.51 ...
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... Bit 7 Bit 6 IRM_SL3 - LRC_SL2 LRC_SL1 LRC_SL0 default Value 0 0 Bit 5 Bit 4 Bit 3 FIR_SL1 FIR_SL0 - Bit 5 Bit 4 Bit Publication Release Date: April 1998 - 79 - W83877ATF Bit 2 Bit 1 Bit 0 MIR_SL2 MIR_SL1 MIR_SL0 Bit 2 Bit 1 Bit 0 HRC_SL2 HRC_SL1 HRC_SL0 Version 0.51 ...
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... Select function for IRRXH or IRSL0 because they share a common pin with different input/output direction. IRSL0_D 0 1 Bit 5 Bit 4 Bit 3 IRSL0D RXINV TXINV Receiver Pin selected IRRX (Low/High Speed) IRRXH (High Speed) Function IRRXH (I/P) IRSL0 (O/P) Publication Release Date: April 1998 - 80 - W83877ATF Bit 2 Bit 1 Bit Version 0.51 ...
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... TXINV - Transmitting Signal Invert Write to 1 inverts the transmitting signal. Bit 2~0: Reserved, write 0. AUX_RX High Speed Publication Release Date: April 1998 - 81 - W83877ATF Selected IR Pin IRRX IRRXH IRRX IRRXH IRRX Reserved IRRX Reserved Version 0.51 ...
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... Printer Interface Logic The parallel port of the W83877ATF makes possible the attachment of various devices that accept eight bits of parallel data at standard TTL level. The W83877ATF supports an IBM XT/AT compatible parallel port (SPP), bi-directional parallel port (BPP), Enhanced Parallel Port (EPP), Extended Capabilities Parallel Port (ECP), Extension FDD mode (EXTFDD), and Extension 2FDD mode (EXT2FDD) on the parallel port ...
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... TABLE 4-1-B Parallel Port Connector and Pin Definition for EXTFDD and EXT2FDD Modes HOST PIN NUMBER CONNECTOR OF W83877ATF ATTRIBUTE PIN SPP PIN EXT2FDD ATTRIBUTE O nSTB ...
Page 88
... Printer control swapper (Read) EPP address port (R/W) EPP data port 0 (R/W) EPP data port 1 (R/W) EPP data port 2 (R/W) EPP data port 2 (R/ TMOUT ERROR SLCT PE ACK BUSY - 84 - W83877ATF NOTE Publication Release Date: April 1998 Version 0.51 ...
Page 89
... Bit 0: A 0.5 microsecond minimum high active pulse clocks data into the printer. Valid data must be present for a minimum of 0.5 microseconds before and after the strobe pulse STROBE AUTO FD INIT SLCT IN IRQ ENABLE DIR Publication Release Date: April 1998 - 85 - W83877ATF Version 0.51 ...
Page 90
... CPU auses an EPP address write cycle to be performed, and the W83877ATF PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Publication Release Date: April 1998 Version 0.51 ...
Page 91
... PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 PD6 PD5 PD4 PD3 EPP DESCRIPTION is de-asserted. The current EPP cycle WAIT Publication Release Date: April 1998 - 87 - W83877ATF PD2 PD1 PD0 1 1 TMOUT INIT AUTOFD STROBE INIT AUTOFD STROBE PD2 PD1 ...
Page 92
... Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte repeated. The hardware support for compression is optional. For more information about the ECP Protocol, refer to the Extended Capabilities Port Protocol and ISA Interface Standard. W83877ATF Publication Release Date: April 1998 - 88 - Version 0.51 ...
Page 93
... ECP FIFO (Address) R All Status Register R/W All Control Register R/W 010 Parallel Port Data FIFO R/W 011 ECP FIFO (DATA) R/W 110 Test FIFO R 111 Configuration Register A R/W 111 Configuration Register B R/W All Extended Control Register DESCRIPTION Publication Release Date: April 1998 - 89 - W83877ATF FUNCTION Version 0.51 ...
Page 94
... Bit 2-0: These three bits are not implemented and are always logic one during a read Address or RLE Address/RLE nFault Select PError nAck nBusy Publication Release Date: April 1998 - 90 - W83877ATF PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 Version 0.51 ...
Page 95
... When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system Strobe Autofd nInit Select In AckInt En Direction Publication Release Date: April 1998 - 91 - W83877ATF Version 0.51 ...
Page 96
... IRQ10 100 IRQ11 101 IRQ14 110 IRQ15 111 IRQ5 Bit 2-0: These five bits are at high level during a read and can be written IRQx 0 IRQx 1 IRQx 2 intrValue compress IRQ resource - 92 - W83877ATF . Publication Release Date: April 1998 Version 0.51 ...
Page 97
... Bit 3: Read/Write 1 Enables DMA. 0 Disables DMA unconditionally Empty Full Service Intr DMA En nErrIntr En MODE MODE MODE lines, and reading the data register returns the value W83877ATF Publication Release Date: April 1998 Version 0.51 ...
Page 98
... PD5 PD4 PD3 PD2 PError Select nFault Directio ackIntEn SelectIn nInit nErrIntrEn dmaEn serviceIntr Publication Release Date: April 1998 - 94 - W83877ATF D1 D0 NOTE PD1 PD0 autofd strobe full empty Version 0.51 ...
Page 99
... ECP Mode. This signal sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to place the channel in the reverse direction. This signal is always deasserted in ECP mode. Publication Release Date: April 1998 - 95 - W83877ATF Version 0.51 ...
Page 100
... PeriphAck is low. The most significant bit of the command is always zero. Data Compression The W83877ATF supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Note that odd (RLE) compression in hardware is not supported. In order to transfer data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo ...
Page 101
... I/O will empty or fill the FIFO using the appropriate direction and mode. 4.4 Extension FDD Mode (EXTFDD) In this mode, the W83877ATF changes the printer interface pins to FDC input/output pins, allowing the user to install a second floppy disk drive (FDD B) through the DB-25 printer connector. The pin assignments for the FDC input/output pins are shown in Table 5-1 ...
Page 102
... PLUG AND PLAY CONFIGURATION A powerful new plug-and-play function has been built into the W83877ATF to help simplify the task of setting up a computer environment. With appropriate support from BIOS manufacturers, the system designer can freely allocate Winbond I/O devices (i.e., the FDC, PRT and UART ) in the PC's I/O space (100H - 3FFH) ...
Page 103
... SERIAL IRQ W83877ATF supports a serial IRQ scheme. This allows a signal line to be used to report the legacy ISA interrupt requests. Because more than one device may need to share the signal serial IRQ signal line, an open drain signal scheme is used. The clock source is the PCI clock. The serial interrupt is transfered on the IRQSER signal, one cycle consisting of three frames types: a start frame, several IRQ/Data frame, and one Stop frame ...
Page 104
... If the corresponding IRQ is inactive, then IRQSER must be left tri-stated. During the Recovery phase, the peripheral device drives the IRQSER high. During the Turn-around phase, the peripheral device left the IRQSER tri-stated. The IRQ/Data Frame has a number of specific order, as shown in Table 7-1. W83877ATF Publication Release Date: April 1998 - 100 - Version 0.51 ...
Page 105
... Start IRQ0 IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK INTA INTB INTC INTD Unassigned - 101 - W83877ATF Publication Release Date: April 1998 ...
Page 106
... MR = 1). A warm reset will not affect the configuration registers. 8.1 Extended Functions Enable Registers (EFERs) After a power-on reset, the W83877ATF enters the default operating mode. Before the W83877ATF enters the extended function mode, a specific value must be programmed into the Extended Function Enable Register (EFER) so that the extended function register can be accessed. The Extended Function Enable Registers are write-only registers ...
Page 107
... EFDR. The bit definitions for CR0 are as follows Bit 7-bit 4: Reserved. PRTMOD1 PRTMOD0 (Bit 3, 2): These two bits and PRTMOD2 (CR9 bit 7) determine the parallel port mode of the W83877ATF (as shown in the following Table 8-1). Table 8-1 PRTMODS2 PRTMODS1 (BIT 7 OF CR9) ...
Page 108
... Bit 1: Reserved. IPD (Bit 0): This bit is used to select the W83877ATF's legacy power-down functions. When the bit 0 is set to 1, the W83877ATF will stop its clock internally and enter power-down (IPD) mode immediately. The W83877ATF will not leave the power-down mode until either a system power-on reset from the MR pin occurs, or until this bit is reset program the chip back to power-on state ...
Page 109
... This bit selects the clock divide rate of UARTB. 0 Disables MIDI support, UARTB clock = 24 MHz divided by 13 (default) 1 Dnables MIDI support, UARTB clock = 24 MHz divided SUBMIDI SUAMIDI reserved reserved reserved EPPVER reserved reserved Publication Release Date: April 1998 - 105 - W83877ATF Version 0.51 ...
Page 110
... The output pins of UARTB will not be tri-stated when UARTB is in power-down mode. 1 The output pins of UARTB will be tri-stated when UARTB is in power-down mode URBTRI URATRI reserved PRTTRI URBPWD URAPWD reserved PRTPWD - 106 - W83877ATF Publication Release Date: April 1998 Version 0.51 ...
Page 111
... DSA , DSB , MOA and MOB output pins are encoded as show in Table 8-3 to select four drives ECPFTHR0 ECPFTHR1 ECPFTHR2 ECPFTHR3 reserved reserved reserved reserved reserved FDCTRI reserved FDCPWD FIPURDWM SEL4FDD reserved reserved - 107 - W83877ATF Publication Release Date: April 1998 Version 0.51 ...
Page 112
... MOB MOA Bit Publication Release Date: April 1998 - 108 - W83877ATF DRIVE DSB DSA SELECTED FDD FDD DRIVE DSB DSA SELECTED FDD A 0 ...
Page 113
... RWC = 0, selects 1.2 MB high-density FDD. RWC = 1, selects 1.44 MB high-density FDD Don't care RWC, selects 720 KB double-density FDD FDD A type 0 FDD A type 1 FDD B type 0 FDD B type 1 FDD C type 0 FDD C type 1 FDD D type 0 FDD D type 1 Publication Release Date: April 1998 - 109 - W83877ATF Version 0.51 ...
Page 114
... KB double-density FDD Floppy Boot Drive 0 Floppy Boot Drive 1 Media ID 0 Media ID 1 SWWP DISFDDWR reserved reserved - 110 - W83877ATF Publication Release Date: April 1998 Version 0.51 ...
Page 115
... This bit and PRTMODS1, PRTMODS0 (bits CR0) select the operating mode of the W83877ATF. Refer to the descriptions of CR0. LOCKREG (Bit 6): This bit enables or disables the reading and writing of all configuration registers. 0 Enables the reading and writing of CR0-CR45 1 Disables the reading and writing of CR0-CR45 (locks W83877ATF extension functions) EN3MODE (Bit 5): default = 0DH ...
Page 116
... CHIP ID 3, CHIP ID 2, CHIP ID 1, CHIP ID 0 (Bit 3-bit 0): These four bits are read-only bits that contain chip identification information. The value is 0DH for W83877ATF during a read. 8.2.11 Configuration Register A (CR0A), When the device is in Extended Function mode and EFIR is 0AH, the CRA register can be accessed through EFDR ...
Page 117
... FDD interface signals are active low 1 FDD interface signals are active high DRV2EN (Bit 0): PS/2 mode only When this bit is a logic 0, indicates a second drive is installed and is reflected in status register A. INTERFACE Model 30 mode PS/2 mode AT mode AT mode Publication Release Date: April 1998 - 113 - W83877ATF Version 0.51 ...
Page 118
... RX2INV reserved URIRSEL reserved HEFERE TURB TURA address and value write 88H to the location 250H write 89H to the location 250H (default) write 86H to the location 3F0H twice write 87H to the location 3F0H twice Publication Release Date: April 1998 - 114 - W83877ATF Version 0.51 ...
Page 119
... IRMODE0 (Bit 0): IR function mode selection bit IRMODE0 IRMODE1 IRMODE2 HDUPLX SIRRX0 SIRRX1 SIRTX0 SIRTX1 IRTX output on pin disabled IRTX1 (pin 43) IRTX2 (pin 95) disabled IRRX input on pin disabled IRRX1 (pin 42) IRRX2 (pin 94) disabled Publication Release Date: April 1998 - 115 - W83877ATF Version 0.51 ...
Page 120
... IRDA MUX 1 MUX IRMODE2 (CRD.bit2) TX2INV URIRSEL CRC.bit0 (CRC,bit3) Publication Release Date: April 1998 - 116 - W83877ATF IRRX high Demodulation into SINB Demodulation into SINB routed to SINB routed to SINB Demodulation into SINB Demodulation into SINB IRRX1 SIN2 01 00 +5V IRRX2 ...
Page 121
... GIO0AD4 GIO0AD5 GIO0AD6 GIO0AD7 GIO0AD8 GIO0AD9 GIO0AD10 reserved reserved reserved G0CADM0 G0CADM1 GIOP0 pin compare GIO0AD10-GIO0AD0 with SA10-SA0 compare GIO0AD10-GIO0AD1 with SA10-SA1 compare GIO0AD10-GIO0AD2 with SA10-SA2 compare GIO0AD10-GIO0AD3 with SA10-SA3 Publication Release Date: April 1998 - 117 - W83877ATF Version 0.51 ...
Page 122
... GIO1AD4 GIO1AD5 GIO1AD6 GIO1AD7 GIO1AD8 GIO1AD9 GIO1AD10 reserved reserved reserved G1CADM0 G1CADM1 GIOP1 pin compare GIO1AD10-GIO1AD0 with SA10-SA0 compare GIO1AD10-GIO1AD1 with SA10-SA1 compare GIO1AD10-GIO1AD2 with SA10-SA2 compare GIO1AD10-GIO1AD3 with SA10-SA3 Publication Release Date: April 1998 - 118 - W83877ATF Version 0.51 ...
Page 123
... GIO0AD10-0), the value of SD0 will be present on GIOP0 When (AEN = L) AND (NIOR = L) AND (SA10 GIO0AD10-0), the value of GIOP0 will be present on SD0 Chip Select pin, the pin will be active at (AEN = L) AND (SA10-0 = GIO0AD10-0) OR (NIOR = L) OR (NIOW = L) Publication Release Date: April 1998 - 119 - W83877ATF Version 0.51 ...
Page 124
... When the device is in Extended Function mode and EFIR is 15H, the CR15 register can be accessed through EFDR. The bit definitions are as follows GDA0IPI GDA0OPI GCS0IOW GCS0IOR GIO0CSH GIOP0MD0 GIOP0MD1 GIOP0MD2 Publication Release Date: April 1998 - 120 - W83877ATF Version 0.51 ...
Page 125
... GIO1AD10-0), the value of SD1 will be present on GIOP1 When (AEN = L) AND (NIOR = L) AND (SA10 GIO1AD10-0), the value of GIOP1 will be present on SD1 Chip Select pin, the pin will be active at (AEN = L) AND (SA10-0 = GIO1AD10-0) OR (NIOR = L) OR (NIOW = L) Publication Release Date: April 1998 - 121 - W83877ATF Version 0.51 ...
Page 126
... Bit 3: Reserved. PNPCVS (bit 2): 0 PnP-related registers (CR20, CR23-29) reset to be all 0s. 1 default settings for these registers. default = 04H HEFRAS reserved PNPCVS reserved G0IQSEL G1IQSEL reserved reserved Publication Release Date: April 1998 - 122 - W83877ATF SD1, inverse Version 0.51 ...
Page 127
... Bit 7-bit 5: Reserved. PNPCVS = 0 FCH 00H DEH 00H FEH 00H BEH 00H 23H 00H 05H 00H 43H 00H 60H 00H DSUBLGRQ DSUALGRQ DSPRLGRQ DSFDLGRQ PRIRQOD reserved reserved reserved - 123 - W83877ATF must Publication Release Date: April 1998 Version 0.51 ...
Page 128
... This register is used to select whether these interrupt request pins are in the IRQ sharing mode. While in the IRQ sharing mode, the corresponding pin is low active for 200ns for the interrupt request and keeps tri-stated otherwise SHARA SHARB SHARC SHARD SHARE SHARF SHARG SHARH Publication Release Date: April 1998 - 124 - W83877ATF Version 0.51 ...
Page 129
... IRQ_C in the IRQ sharing mode. SHARB(Bit 1): 0 pin IRQ_B in the legacy ISA IRQ mode. 1 pin IRQ_B in the IRQ sharing mode. SHARA (Bit 0): 0 pin IRQ_A in the legacy ISA IRQ mode. 1 pin IRQ_A in the IRQ sharing mode. W83877ATF Publication Release Date: April 1998 - 125 - Version 0.51 ...
Page 130
... FDCAD7-FDCAD2 (Bit 7-bit 2): match A[9:4]. Bit and bit disable this decode. Bit 1-bit 0: Reserved, fixed at zero. 8.2.27 Configuration Register 23 (CR23 FASTB FASTA reserved reserved reserved reserved reserved reserved reserved reserved FDCAD2 FDCAD3 FDCAD4 FDCAD5 FDCAD6 FDCAD7 Publication Release Date: April 1998 - 126 - W83877ATF Version 0.51 ...
Page 131
... EFDR. Default = BEH if CR16 bit default = 00H if CR16 bit The bit definitions are as follows PRTAD0 PRTAD1 PRTAD2 PRTAD3 PRTAD4 PRTAD5 PRTAD6 PRTAD7 reserved URAAD1 URAAD2 URAAD3 URAAD4 URAAD5 URAAD6 URAAD7 Publication Release Date: April 1998 - 127 - W83877ATF Version 0.51 ...
Page 132
... Bit 7- bit4, Bit 3 - bit 0 0000 0001 0010 0011 reserved URBAD1 URBAD2 URBAD3 URBAD4 URBAD5 URBAD6 URBAD7 PRTDQS0 PRTDQS1 PRTDQS2 PRTDQS3 FDCDQS0 FDCDQS1 FDCDQS2 FDCDQS3 DMA selected None DMA_A DMA_B DMA_C Publication Release Date: April 1998 - 128 - W83877ATF Version 0.51 ...
Page 133
... IRQ pin 0000 0001 0010 0011 0100 0101 0110 0111 1000 PRTIQS0 PRTIQS1 PRTIQS2 PRTIQS3 reserved ECPIRQx0 ECPIRQx1 ECPIRQx2 IRQ resource None IRQ_A IRQ_B IRQ_C IRQ_D IRQ_E IRQ_F IRQ_G IRQ_H Publication Release Date: April 1998 - 129 - W83877ATF Version 0.51 ...
Page 134
... URBIQS3-URBIQS0 (Bit 3-bit 0): Allocate interrupt resource for UART B. None IRQ1 SMI IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 URBIQS0 URBIQS1 URBIQS2 URBIQS3 URAIQS0 URAIQS1 URAIQS2 URAIQS3 Publication Release Date: April 1998 - 130 - W83877ATF Version 0.51 ...
Page 135
... DMA channel is used, or act as RX/TX DMA channel selection if single DMA channel is used The bit definitions are as follows IRRXDRQSL0 IRRXDRQSL1 IRRXDRQSL2 IRRXDRQSL3 IRTXDRQSL0 IRTXDRQSL1 IRTXDRQSL2 IRTXDRQSL3 Publication Release Date: April 1998 - 131 - W83877ATF IQNIQS0 IQNIQS1 IQNIQS2 IQNIQS3 FDCIQS0 FDCIQS1 FDCIQS2 FDCIQS3 Version 0.51 ...
Page 136
... PIN93FUN0 PIN93FUN1 PIN3FUN0 PIN3FUN1 PIN2FUN0 PIN2FUN1 PIN1FUN0 PIN1FUN1 PIN1FUN0 Pin 2 0 nCS 1 A11 0 Reserved 1 Reserved Pin 3 0 PDCIN 1 nDACK_D 0 IRSL1 1 IRRXH/IRSL0 Publication Release Date: April 1998 - 132 - W83877ATF Pin 1 IRQ_G Reserved DRQ_D IRSL2 PCICLK Version 0.51 ...
Page 137
... Reserved Reserved CLKINSEL ENBNKSEL APEDCRC PIN91FUN0 PIN91FUN1 PIN91FUN2 PIN91FUN1 PIN91FUN0 is, a IRQ mode selection. Publication Release Date: April 1998 - 133 - W83877ATF Pin 93 IRQIN DRQ_D IRSL2 IRRXH/IRSL0 PNF Pin 91 IRQ_H Reserved IRSL2 Reserved DACK_D SERIRQ Version 0.51 ...
Page 138
... DRATE1 DRATE0 134 - W83877ATF , the CR2D register can be 16 operational data rate MFM FM 1M --- 500K 250K 300K 150K 250K 125K 1M --- 500K 250K 500K 250K 250K 125K 1M --- 500K 250K 2M --- ...
Page 139
... Disable 16-bit address decoder in the ISA bus. INVRD (Bit 2): 0 Disable inverting RDATA from floppy disk input signal. (Default) 1 Enable inverting RDATA from floppy disk input signal nEN16SA ENPNF INVRD EN24X2M DIS_BST Reserved Reserved Reserved Publication Release Date: April 1998 - 135 - W83877ATF Version 0.51 ...
Page 140
... In Serial IRQ mode, the definition of SCIIQS3-SCIIQS0 (bit 7-bit follows: SCIIQS3-SCIIQS0 (bit 7-bit 4): Select the IRQ/Data sampling period on the SERIRQ pin reserved reserved IRQMODS reserved SCIIRQ0 SCIIRQ1 SCIIRQ2 SCIIRQ3 Mapped IRQ pin Publication Release Date: April 1998 - 136 - W83877ATF Version 0.51 ...
Page 141
... Bit 3: Reserved. IRQMODS (Bit 2): IRQ mode seleection. The W83877ATF supports: (1) legacy ISA IRQ mode or ISA IRQ sharing mode. (2) Serial IRQ mode used in the PCI bus. In the legacy ISA IRQ sharing mode, the selected IRQ pin for the device's IRQ is defined in the configuration registers CR27 - CR29. In the ISA IRQ sharing mode, configuration register CR18 indicates which IRQ pin is in the IRQ sharing mode ...
Page 142
... CHIPPME (Bit 7): W83877ATF chip power management enable. 0 disable the ACPI/Legacy and the auto power management functions. 1 enable the ACPI/Legacy and the auto power management functions. Bit 6 - bit 4: Reserved. PRTPME (Bit 3): Printer port power management enable. 0 disable the auto power management function. ...
Page 143
... W83877ATF reserved reserved PM1AD2 PM1AD3 PM1AD4 PM1AD5 PM1AD6 PM1AD7 reserved GPEAD1 GPEAD2 GPEAD3 GPEAD4 GPEAD5 GPEAD6 GPEAD7 Publication Release Date: April 1998 Version 0 ...
Page 144
... URBPME=1 (CR32 bit 0), (2). If the register is set to 00H, UART B will remain in the current state (working or sleeping URACNT0 URACNT1 URACNT2 URACNT3 URACNT4 URACNT5 URACNT6 URACNT7 URBCNT0 URBCNT1 URBCNT2 URBCNT3 URBCNT4 URBCNT5 URBCNT6 URBCNT7 Publication Release Date: April 1998 - 140 - W83877ATF Version 0.51 ...
Page 145
... PRTPME=1 (CR32 bit 3), (2). If the register is set to 00H, the printer port will remain in the current state (working or sleeping FDCCNT0 FDCCNT1 FDCCNT2 FDCCNT3 FDCCNT4 FDCCNT5 FDCCNT6 FDCCNT7 PRTCNT0 PRTCNT1 PRTCNT2 PRTCNT3 PRTCNT4 PRTCNT5 PRTCNT6 PRTCNT7 Publication Release Date: April 1998 - 141 - W83877ATF Version 0.51 ...
Page 146
... If this register is set to 0, the power down function will be invalid. The time resolution of this register value is minute or second, which is defined by the TMIN_SEL bit of CR3A. Note that (1). This register is valid when the CHIPPME = 1 (CR32 bit 7), and (2) If the register is set to 00H, W83877ATF chip will remain in the current state (working or sleeping). ...
Page 147
... These bits indicate that the individual device's idle timer expires due to no I/O access, IRQ, and external input to the device respectively. These 4 bits are controlled by the printer port, FDC, UART A, and UART B power down machines individually. The bits are set/cleared by W83877ATF automatically. Writing a 1 can also clear this bit, and writing a 0 has no effect. ...
Page 148
... The device's idle timer reloads the initial count value from CR35-CR39, depending on which device wakes up. These 4 bits are controlled by the printer port, FDC, UART A, and UART B power down machines individually. The bits are set/cleared by W83877ATF automatically. Writing a 1 can also clear this bit, and writing a 0 has no effect. ...
Page 149
... When the device is in Extended Function mode and EFIR is 42H, the CR42 register can be accessed through EFDR. The bit definitions are as follows Bit 7 - bit 4 : Reserved, fixed at 0. Bit 3 - bit 0 : Device's IRQ status . URBIRQSTS URAIRQSTS FDCIRQSTS PRTIRQSTS reserved reserved reserved reserved Publication Release Date: April 1998 - 145 - W83877ATF Version 0.51 ...
Page 150
... EFDR. The bit definitions are as follows Bit 7 - bit 4 : Reserved, fixed at 0. Bit 3 - bit 0 : Enable bits of the SMI generation due to the device's IRQ URBIRQEN URAIRQEN FDCIRQEN PRTIRQEN reserved reserved reserved reserved Publication Release Date: April 1998 - 146 - W83877ATF Version 0.51 ...
Page 151
... SMI interrupt due to the UART A's IRQ. URBIRQEN (Bit 0): 0 disable the generation of an SMI interrupt due to the UART B's IRQ. 1 enable the generation of an SMI interrupt due to the UART B's IRQ. W83877ATF Publication Release Date: April 1998 - 147 - or Version 0.51 ...
Page 152
... GIO0AD6 GIO0AD5 GIO0AD4 0 0 GIO1AD6 GIO1AD5 GIO1AD4 0 0 GIOP0MD0 GIO0CSH GIOP1MD0 GIO1CSH 0 G1IQSEL G0IQSEL 0 0 PRIRQOD SHARG SHARF SHARE 148 - W83877ATF PRTMODS1 PRTMODS0 SUAMIDI PRTTRI 0 URATRI ECPFTHR3 ECPFTHR2 ECPFTHR1 FDCPWD 0 FDCTRI FDD B T1 FDD B T0 ...
Page 153
... PRTCNT5 PRTCNT4 GSBCNT5 GSBCNT4 0 TMIN_SEL 149 - W83877ATF FDCAD3 FDCAD2 0 PRTAD3 PRTAD2 PRTAD1 URAAD3 URAAD2 URAAD1 URBAD3 URBAD2 URBAD1 PRTDQS3 PRTDQS2 PRTDQS1 PRTIQS3 PRTIQS2 PRTIQS1 URBIQS3 URBIQS2 URBIQS1 IQNIQS3 IQNIQS2 IQNIQS1 IRRXDSL3 IRRXDSL2 ...
Page 154
... ACPI Registers Features W83877ATF supports both the ACPI and legacy power managements. The switch logic of the power managment block generates an SMI interrupt in the legacy mode and an SCI interrupt in the ACPI mode. For the legacy mode, the SMI_EN bit is used set, it routes the power management events from the SMI interrupt logic to the SMI output pin ...
Page 155
... Writing GBL_RLS has no effect. Writing BIOS_STS clears it to logic 0 and also clears GBL_RLS to logic 0; writing BIOS_STS has no effect. For the bus master to raise an event to the ACPI software, BM_CNTRL, BM_RLD, and BM_STS bits are involved. Both BM_RLD and BM_STS are controlled by the ACPI software. If BM_CNTRL is set W83877ATF clear GBL_STS set ...
Page 156
... Those status bits which have no respective enable bit are read for special purposes. Reserved or un-implemented enable bits always return zero, and writing to these bits should have no effect. TMR_STS 24 bit counter Bits (23-0) 24 TMR_EN TMR_VAL Publication Release Date: April 1998 - 152 - W83877ATF To SCI Logic Version 0.51 ...
Page 157
... Reserved. These bits always return a value of zero. to 11,1111,0000 ,i.e., 100H ~ 3F0H, where bit 1 and bit 11,1111,1000 ,i.e., 100H ~ 3F8H, where bit 0 of the base Description - 153 - W83877ATF TMR_STS Reserved Reserved Reserved BM_STS GBL_STS Reserved Reserved Publication Release Date: April 1998 Version 0.51 ...
Page 158
... System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits Reserved Reserved Reserved Reserved Reserved Reserved Reserved WAK_STS Description TMR_EN Reserved Reserved Reserved GBL_EN Reserved Reserved Reserved Publication Release Date: April 1998 - 154 - W83877ATF Version 0.51 ...
Page 159
... Reserved. These bits always return a value of zero. 8.4.5 Power Management 1 Control Register 1 (PM1CTL1) Register Location: <CR33>+4H System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Publication Release Date: April 1998 - 155 - W83877ATF Version 0.51 ...
Page 160
... Bit Name 0-7 Reserved Reserved. These bits always return a value of zero SCI_EN BM_RLD GBL_RLD Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Publication Release Date: April 1998 - 156 - W83877ATF Version 0.51 ...
Page 161
... Bit Name 0-7 Reserved Reserved. These bits always return a value of zero Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Publication Release Date: April 1998 - 157 - W83877ATF Version 0.51 ...
Page 162
... System I/O Space Default Value: 00h Attribute: Read only Size: 8 bits TMR_VAL0 TMR_VAL1 TMR_VAL2 TMR_VAL3 TMR_VAL4 TMR_VAL5 TMR_VAL6 TMR_VAL7 Description TMR_VAL8 TMR_VAL9 TMR_VAL10 TMR_VAL11 TMR_VAL12 TMR_VAL13 TMR_VAL14 TMR_VAL15 Publication Release Date: April 1998 - 158 - W83877ATF Version 0.51 ...
Page 163
... The TMR_STS bit is set any time the last bit of the timer (bit 23) goes from from the TMR_EN bit is set, the setting of the TMR_STS bit will generate an SCI interrupt. Description TMR_VAL16 TMR_VAL17 TMR_VAL18 TMR_VAL19 TMR_VAL20 TMR_VAL21 TMR_VAL22 TMR_VAL23 Description Publication Release Date: April 1998 - 159 - W83877ATF Version 0.51 ...
Page 164
... PRT SCI status, which is set by the printer port IRQ. 4-7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description URBSCISTS URASCISTS FDCSCISTS PRTSCISTS Reserved Reserved Reserved Reserved Description Publication Release Date: April 1998 - 160 - W83877ATF Version 0.51 ...
Page 165
... SCI logic output = (URBSCIEN and URBSCISTS) or (URASCIEN and URASCISTS) or (FDCSCIEN and FDCSCISTS) or (PRTSCIEN and PRTSCISTS Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description URBSCIEN URASCIEN FDCSCIEN PRTSCIEN Reserved Reserved Reserved Reserved - 161 - W83877ATF Publication Release Date: April 1998 Version 0.51 ...
Page 166
... System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description BIOS_STS Reserved Reserved Reserved Reserved Reserved Reserved Reserved - 162 - W83877ATF Publication Release Date: April 1998 Version 0.51 ...
Page 167
... System I/O Space Default Value: 00h Attribute: Read/write Size: 8 bits 7 6 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description 163 - W83877ATF BIOS_EN TMR_ON Reserved Reserved Reserved Reserved Reserved Reserved Publication Release Date: April 1998 Version 0.51 ...
Page 168
... SCI interrupt is generated. Writing a 1 sets BM_CNTRL to 1 and also sets BM_STS. Writing a 0 has no effect. Writing BM_STS clears BM_STS and also clears BM_CNTRL. 2-7 Reserved Reserved. Description BIOS_RLS BM_CNTRL Reserved Reserved Reserved Reserved Reserved Reserved Description - 164 - W83877ATF Publication Release Date: April 1998 Version 0.51 ...
Page 169
... 165 - W83877ATF GBL_RLS BM_RLD TMR_VAL3 TMR_VAL2 TMR_VAL1 TMR_VAL11 TMR_VAL10 TMR_VAL9 TMR_VAL19 TMR_VAL18 ...
Page 170
... MIN. TYP. MAX. -0.5 0.3xV IL 0.7xV V +0 0.4 2.4 +10 -10 -0.5 0.8 IL 2 0.4 2.4 +10 -10 -0.5 0.8 IL 2 0.4 2.4 +10 -10 - 166 - W83877ATF UNIT UNI CONDITIONS - ...
Page 171
... LIL V 0.3xV 0.7xV +10 LIH I -10 LIL V 1.3 1.5 1 3..2 3 +10 LIH I -10 LIL - 167 - W83877ATF UNIT CONDITIONS - ...
Page 172
... CL = 100 100 MCY 260/430 AA /510 168 - W83877ATF TYP. MAX. UNIT (NOTE 360/570 nS /675 360/570 nS /675 Publication Release Date: April 1998 ...
Page 173
... Programmable from 2 mS through increments. TEST MIN. CONDITIONS 135/220 TC /260 1.8/3/3. RST 5 0.5/0.9 IDX /1.0 1.0/1.6 DST /2.0 24/40/48 STD 6.8/11.5 STP /13.8 Note 2 SC 100/185 /225 100/138 /225 - 169 - W83877ATF TYP. MAX. UNIT (NOTE 1) 6/12 S /20/ 7/11.7 7.2/11.9 S /14 /14.2 Note 2 Note 2 S 125/210 150/235 S /250 /275 125/210 150/235 ...
Page 174
... Loading MWO T SIM T RIM T 100 pF Loading IAD T 100 pF Loading IID N 100 pF Loading SYM. MIN. TYP 200 t5 Publication Release Date: April 1998 - 170 - W83877ATF MIN. MAX. UNIT 9/16 Baud Rate 1 S 1/16 8/16 Baud Rate 175 nS 9/16 16/16 Baud Rate 1/2 Baud Rate 250 nS 200 ...
Page 175
... Command Deasserted to PD Hi-Z WAIT Deasserted to PD Drive WRITE Deasserted to Command PBDIR Set to Command PD Hi-Z to Command Asserted Asserted to Command Asserted WAIT Deasserted to Command Deasserted Time out WAIT PD Valid to Deasserted WAIT PD Hi-Z to Deasserted W83877ATF SYM. MIN ...
Page 176
... Deasserted to Deasserted and PD invalid Parallel Port FIFO Timing Parameters PARAMETER DATA Valid to nSTROBE Active nSTROBE Active Pulse Width DATA Hold from nSTROBE Inactive BUSY Inactive to PD Inactive BUSY Inactive to nSTROBE Active nSTROBE Active to BUSY Active W83877ATF SYM. MIN ...
Page 177
... Asserted to BUSY Asserted BUSY Asserted to nSTROBE Deasserted ECP Parallel Port Reverse Timing Parameters PARAMETER PD Valid to nACK Asserted nAUTOFD Deasserted to PD Changed nAUTOFD Asserted to nACK Asserted nAUTOFD Deasserted to nACK Deasserted nACK Deasserted to nAUTOFD Asserted PD Changed to nAUTOFD Deasserted W83877ATF SYMBOL MIN ...
Page 178
... TMR (IOR) WD TRA TDH TDF INDEX TR TC TWA TWD TDW RESET TWI DIR TAA TDST STEP Publication Release Date: April 1998 - 174 - W83877ATF Write Date TWDD Index TIDX TIDX Terminal Count TTC Reset TRST Drive Seek operation TSTP TSTD TSC Version 0.51 ...
Page 179
... BUFFER REGISTER) SERIAL OUT STAR (SOUT) THRS IRQ3 or IRQ4 THR IOW TSI (WRITE THR) IOR (READ TIR) Receiver Timing DATA BITS (5-8) PARITY STOP TSINT Transmitter Timing DATA (5-8) PARITY STOP (1-2) THR Publication Release Date: April 1998 - 175 - W83877ATF TRINT STAR TSTI TIR Version 0.51 ...
Page 180
... Printer Interrupt Timing ¢x ¢x ¢x ¢ ¢x ¡ö TLAD ¢x ¢x ¢x ¢x ¢x ¢ ¢x ¢x - 176 - W83877ATF ¢x ¢x ¢x ¡÷ ¡ö TMWO ¢x ¢ ¢x ¢x ¢x ¢x ¢ TSIM ¢x ¢x ¢x ¢ ...
Page 181
... Parallel Port Parallel Port Timing IOW INIT, STROBE AUTOFD, SLCTIN PD<0:7> ACK IRQ (SPP) IRQ (EPP or ECP) nFAULT (ECP) ERROR (ECP) IRQ Publication Release Date: April 1998 - 177 - W83877ATF t3 t4 Version 0.51 ...
Page 182
... EPP Data or Address Read Cycle (EPP Version 1.9) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t21 t22 t23 t24 ADDRSTB DATASTB WAIT t18 t19 t25 t27 t26 Publication Release Date: April 1998 - 178 - W83877ATF t15 t20 t28 Version 0.51 ...
Page 183
... EPP Data or Address Write Cycle (EPP Version 1.9) A10-A0 SD<0:7> t1 IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT t22 PBDIR t10 t11 t13 t15 t16 t17 t18 t19 t20 - 179 - W83877ATF t12 t14 t21 Publication Release Date: April 1998 Version 0.51 ...
Page 184
... EPP Data or Address Read Cycle (EPP Version 1.7) A<0:10> t1 IOR SD<0:7> t5 IOCHRDY t10 t13 t14 WRITE t16 t17 PD<0:7> t21 t22 t23 ADDRSTB t24 DATASTB WAIT t18 t19 t25 t26 t27 Publication Release Date: April 1998 - 180 - W83877ATF t15 t20 t28 Version 0.51 ...
Page 185
... SD<0:7> t1 IOW IOCHRDY WRITE PD<0:7> DATAST ADDRSTB WAIT Parallel Port FIFO Timing PD<0:7> nSTROBE BUSY t10 t11 t13 t15 t16 t17 t18 t19 t20 t1 t2 > >| t6 >| - 181 - W83877ATF t22 t22 t4 >| t3 >| t5 >| Publication Release Date: April 1998 Version 0.51 ...
Page 186
... ECP Parallel Port Forward Timing nAUTOFD PD<0:7> nSTROBE BUSY ECP Parallel Port Reverse Timing PD<0:7> nACK t5 nAUTOFD Publication Release Date: April 1998 - 182 - W83877ATF Version 0.51 ...
Page 187
... RDD2/PD3 5 17 STEP2/SLIN 4 WP2/PD2 16 DIR2/INIT 3 TRK02/PD1 15 HEAD2/ERR 2 IDX2/PD0 14 RWC2/AFD 1 STB PRINTER PORT Parallel Port Extension FDD Mode Connection Diagram W83877ATF DCH2 HEAD2 RDD2 WP2 TRK02 WE2 WD2 STEP2 DIR2 MOB2 DSB2 IDX2 RWC2 Publication Release Date: April 1998 - 183 - JP 13A ...
Page 188
... WE2 WD2 STEP2 DIR2 MOB2 DSA2 DSB2 MOA2 IDX2 RWC2 74LS139 7407(2) G1 1Y0 A1 1Y1 B1 1Y2 1Y3 2Y0 2Y1 G2 2Y2 2Y3 A2 B2 Publication Release Date: April 1998 - 184 - W83877ATF JP 13A ...
Page 189
... W83877ATF 732AC27242968 1st line: Winbond logo 2nd line: the type number: W83877ATF 3rd line: the tracking code: 732 7242968 732: packages made in '97, week 19 A: assembly house ID; A means ASE, S means SPIL ... etc C: IC revision; B means version B, C means version C ...
Page 190
... PACKAGE DIMENSIONS W83877ATF (100-pin QFP 100 See Detail F y Seating Plane Detail F - 186 - W83877ATF Dimension in inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A 0.130 3.30 A 0.004 0. 0.107 0.112 ...
Page 191
... Detail F Winbond Electronics (H.K.) Ltd. Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064 - 187 - W83877ATF Dimension in inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. A 0.05 0.10 A 0.002 0.004 0.006 ...