MT90812AL Zarlink Semiconductor, MT90812AL Datasheet
MT90812AL
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MT90812AL Summary of contents
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... Ordering Information MT90812AP 68 Pin PLCC MT90812AL 64 Pin MQFP MT90812APR 68 Pin PLCC MT90812AP1 68 Pin PLCC* MT90812AL1 64 Pin MQFP* MT90812APR1 68 Pin PLCC* *Pb Free Matte Tin Description By integrating key functions needed in voice telecom application, the Integrated Digital Switch (IDX) provides a solution-on-a-chip for key telephone systems, PBX applications or CTI designs. Figure 2 shows a typical confi ...
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MT90812 Advance Information STi0 Serial to STi1 Parallel M Converter EST1 U X Conference FSK and Tone Generation D-channel TX/RX Microprocessor CPU Interface C.O. 2B+D 2B+D Trunks 2B+D CODEC MPU Interface - D-channel - Chip control Figure 2 - System ...
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IC 10 VBUF 11 VSSA 12 VDDA 13 F4o 14 C2o 15 C4o 16 C10o 17 68 PIN PLCC VSS3 ...
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MT90812 Advance Information Pin Description Pin # Name 64 Pin 68 Pin MQFP PLCC 1 25- Connect . Ground 2-11 27- Address 0 - 9(Input) . When non-multiplexed CPU bus is selected, these lines provide ...
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Pin Description (continued) Pin # Name 64 Pin 68 Pin MQFP PLCC 33-34 59- Connect . Ground 35 62 VSS2 Ground . 36-37 63-64 STi0-1 Serial TDM input streams 0 and 1 (Input) . Serial data input streams ...
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MT90812 Advance Information Pin Description (continued) Pin # Name 64 Pin 68 Pin MQFP PLCC 54 14 F4o Frame Pulse for 4.096 MHz (Output) . This KHz output frame pulse that indicates the start of the active ...
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Functional Description The functional block diagram of Fig. 1 depicts the main operations performed by the MT90812. The integrated digital switch has three TDM streams. The two local TDM serial streams, STi/o0 and STi/o1, operate at 2048kbit/s and are ...
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MT90812 Advance Information multiplexed bus specifications. The MT90812 can operate in either register as specified in section “Control Register (CTL)” on page 54. 2.0 Local TDM Streams There are two local serial Time Division Multiplexed (TDM) streams. These streams at ...
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Each of the 32 channels of the 8 streams connecting the DX and IDX devices can be switched to any outgoing channel and stream. This provides switching across all eight of the MT90812 devices. 3.2 IDX Link Mode In IDX ...
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MT90812 Advance Information 4.0 Switching The switching function of the MT90812 is described in four parts: • How incoming data from the Local TDM streams are transferred to Data Memory. • How incoming data from the Expansion Bus is transferred ...
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Control Register and the use of Connection Memory • Connect Memory Configurations for Expansion Bus Modes Each will be described below. A full description of addressing memory in the MT90812 is given in “Address Memory Map” starting on page ...
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MT90812 Advance Information 5.0 Address Memory Map The MT90812 memory is accessed via the microport. The microport can operate in multiplexed or non- multiplexed mode as described in “Microprocessor Port” on page 49 The access to the MT90812 memory for ...
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A6-A0, give access to the Control Registers if A9,A8,A7=111, or depending on the high order bits A9,A8,A7, to the High or Low sections of the Connection Memory the Data Memory, as shown in Table 1. 5.2 ...
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MT90812 Advance Information Address Local Data Memory A6-A0 40-59 DTMF Tones(26) 59-5A Tone Ringer or DTMF 5B-5E Tones(4) 5F FSK or DTMF 60-6E CONFout(15) 6F unused 70 DCHout(1) 71-7F unused(14) 5.3 Connection Memory use in Conferencing, Gain Control and specifying ...
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Channels can be transferred from Data Memory in either Minimum or Constant Delay to the Energy Detect and DBRT blocks as specified in CMH. CMH Message Mode and Output Enable bits are ignored for locations 70-72 of CM. In addition, ...
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MT90812 Advance Information FP Expansion Bus EST0 Data Memory Hex A6-A0 DM EST1 00 EA1 01 EA2 - - 1F EA32 20 EB1 21 EB2 - - 3F EB32 40 EC1 41 EC2 - - 5F EC32 60 ED1 61 ...
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FP EST0 . Expansion Bus Data EST1 Memory Hex 00 A6 EA1 01 EA2 - - 1F EA32 20 EB1 21 EB2 - - 3F EB32 40 EC1 41 EC2 - - 5F EC32 60 ED1 61 ...
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MT90812 Advance Information timeslots, where IDX A can either write to EST0 and EST1 during these channels or place EST0 or EST1 in high impedance. FP EST0 . Expansion Bus EST1 Data Memory Hex DM A6-A0 00 EA1 01 EA2 ...
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Channels that can be included in a conference include; the 64 channels of STi0 and STi1, and the channels of the four expansion bus blocks. In fact any location in Local or Expansion Data Memory can be specifi ...
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MT90812 Advance Information Data Memory Incoming Channel Incoming Data 60-6E H* Conference Output Control Registers Conf Party Control 30-3E CID,ST,IT,GCout HEX Figure 15 - Conference Control with Conference Party Control Registers and Connect Memory 6.1 Channel Attenuation Channel Attenuation is ...
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Conference Overflow A peak clipping indicator identifies the conference causing conference bridge overflow whenever a 14-bit two 1 complement overflow occurs . Once a conference bridge overflow occurs an interrupt is asserted, the Conference Overflow bit in the Interrupt ...
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MT90812 Advance Information (OE) bit of Local (or Expansion depending on the output stream number) Connect Memory High must be set order to put the output driver of the corresponding stream into high-impedance state during the selected ...
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Source and Destination Streams Sti0/1 -> Sto0/1 Est0/1 -> Est0/1 Sti0/1 -> Est0/1 Est0/1 -> Sto0/1 Table 6 - Output Channels for Minimum Delay The output channel number m, specified for minimum delay in these four cases account for there ...
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MT90812 Advance Information Constant Delay Mode (CST bit=1) 8.2 In Constant Delay mode, channel integrity is maintained by making use of a multiple Data Memory buffer technique. The input channels written in any of the buffers during frame N will ...
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Multiple IDX systems are supported by allowing the IDX to either drive or receive an 8.192 MHz clock. The master IDX in the system may supply C8 while the slave IDX derive their timing from the master multi- ...
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MT90812 Advance Information The MT90812 defaults to C8P input clock reference when reset. When C8P is selected as the input clock reference the clock oscillator pins C8P_C16 and OSC can be used with an external 8.192 MHz crystal or pin ...
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The MT90812 generates C4o, F4o, C8, and F8 signals in either ST-Bus or GCI formats as selected by the FPO bit in the Timing Control Register (TC). This selection is independent of the incoming frame synchronization used. 9.2.5 Selecting Timing ...
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MT90812 Advance Information 9.3.1 Master and Slave PLL Modes The PLL Master/Slave (PMS) bit in the TC register selects the PLL mode. In Master mode the PLL loop filter is selected to minimize the magnitude of any one clock correction. ...
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C8P Pin Timing Source The MT90812 can use either a clock or crystal, connecting to pins C8P_C16i and OSCo reference timing source. 9.5.1 Clock Oscillator Fig. 19 shows a 8.192MHz clock oscillator, with 32 ppm tolerance, directly ...
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MT90812 Advance Information MT90812 1uH inductor: may improve stability and is optional 10.0 D-Channel Signalling Support The MT90812 can support communications over the D-channel in one of the following methods: • Basic Receive Transmit Method • Shared HDLC Resource Method ...
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Interrupt Mode name Mode Message oriented MLIM Message oriented with parity MLIM Unframed FLIM Byte oriented FLIM Byte oriented with parity FLIM *X = don’t care ST MLIM* Message Oriented ST MLIM* Message Oriented with Parity ...
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MT90812 Advance Information will specify whether the received data will have a parity bit and consequently the receiver will perform a parity check on the received data. In FLI Mode, the start and stop bits and the parity bit can ...
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The stop bit was not detected (RX stop bit error). • The status of the received parity bit did not equate to the calculated parity (RX parity bit error). 12.0 Transmitter Operation Fig. 23 illustrates the data flow for ...
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MT90812 Advance Information 12.1 Transmitter Interrupt Handling In either MLI or FLI modes interrupts are generated on TX FIFO empty or 3/4 empty, or end of transmission. The TX FIFO Interrupt Select (IS) and Interrupt Level (IL) bits in the ...
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Dedicated Receive Mode • Multiplexed Receive Mode • CTS Generation • Receive Packet Termination • RX Channel Auto-hunt • Auto-hunt Monitoring • Circumstances When Monitoring a Channel is Stopped Refer to the HDLC control and status registers starting on ...
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MT90812 Advance Information The MT90812 output C2o is a 2.048 MHz clock provided for the MT8952 HDLC controller bit rate clock input. 13.2.2 Connection to MT9171/72B DNIC The DNIC, as mentioned earlier, is used in dual-port mode. The B1 and ...
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D0 D7 Micro processor R/W MRDY IRQ Figure 24 - Typical Application Using the HDLC Resource Allocator 13.3 TX Control The TX circuit performs the following functions: • generate TxCEN to enable the HDLC transmitter. • handle ...
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MT90812 Advance Information the MT90812 microport. TxCEN output signal is enabled for one to eight bits per channel per frame, depending upon the selected baud rate. The desired active channel is selected by the system via a write to the ...
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Merging of D and C-channels. The HRA block multiplexes the D-channel, originating at the HDLC Protocol Controller, and the C-channels into a common output stream. C-channel and D-channel information destined for the line circuit are also fed through a ...
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MT90812 Advance Information 14.1.1 Generation of RxCEN The RX circuit performs two functions. As with the TX circuit, it must generate the proper HDLC receive clock enable signal (RxCEN). This signal has the same characteristics as TxCEN. The RxCEN signal ...
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In multiplexed operation, the receiver obtains the next RX channel (NRX) number from the RX channel Auto- hunt circuit. Three conditions must be met before the RX circuitry will initiate receiving a packet: • The Auto-hunt circuit must have detected ...
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MT90812 Advance Information The second condition occurs if the Auto-hunt circuit manages to cycle back to monitor a peripheral which is already the currently active receive channel. Because the peripheral continues to during the time when it is being acknowledged ...
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A further 9 other standard tones are available for use as call progress and supervisory tones. Also available are 7 programmable tones, which may be single or dual frequency. This totals 32 available tone outputs. The composite signal output level ...
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MT90812 Advance Information Addr Frequency(Hz) Application 00 697+1209 DTMF digits 1 01 697+1336 DTMF digit 2 02 697+1477 DTMF digit 3 03 697+1633 DTMF digit A 04 770+1209 DTMF digit 4 05 770+1336 DTMF digit 5 06 770+1477 DTMF digit ...
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NA 32 242. 4000.00 33 235. 2666.67 34 228. 2000.00 35 222. 1600.00 36 216. 1333.33 37 210. 1142.86 38 205.13 70 ...
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MT90812 Advance Information Data Memory 5F H Control Registers Uport Write 07 FSKM FSK modulator that generates two output frequencies, representing the ‘marks’ and ‘spaces’. Start and Stop bits are added to each byte FSK ...
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Subsequently the interrupt occur once every 8 bits (53 1/3 frames). Wait until the desired number of channel seizure bits have been sent. • Transmit Mark 3. Switch to mark as the idle state. Again use end of transmission interrupt ...
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MT90812 Advance Information For a continuous signal, such as dial tone, where there is no off time, an interrupt occurs when the counter reaches a maximum count of 508 msec. When a maximum count of 508 msec is reached the ...
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Microprocessor Port The MT90812 provides a parallel microprocessor interface for non-multiplex or multiplexed bus structures. This interface is compatible with Motorola non-multiplexed/multiplexed and Intel/National multiplexed buses. If the IM input pin is low or not connected, the device assumes ...
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MT90812 Advance Information 21.0 Connection Memory Bits Locations in the Connection Memory are associated with the local TDM output streams and the Expansion Bus streams. It also determines whether individual output channels are in Message Mode, allows individual output channel ...
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At locations 60 to 6E, Connect Memory High is used to specify the Conference incoming channel attenuation and Noise Suppression. For these locations bits 7-3 are used as incoming channel attenuation, bits 1-0 are used for Noise Suppression bits and ...
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MT90812 Advance Information 22.0 Detailed Register Descriptions The first page of 128 locations of memory contains the control registers. The control registers are accessed independent of the setting of the memory select bits when in multiplexed mode by setting external ...
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Hex Address Name A6-A0 50 HC1 51 HC2 52 HC3 53 HLO1 54 HLO2 55 HS1 56 HS2 57 HS3 58 HS4 59-5F unused 60 reserved 61 reserved 62-7F unused Test Register 1 and 2 are at locations 60 22.1 ...
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MT90812 Advance Information 22.2 Control Register (CTL) The Control register (CTL) selects Data/Connection Memory and defines Expansion bus position. Read/Write Address is: 001 H Reset Value is Bit Name 7 - Unused. 6 Serial Output enable ...
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Timing Control Register (TC) The timing control register is configured as follows: Read/Write Address is: 002 H Reset Value is Bit Name 7 WDE Watchdog Enable. When 0, disables the Clock Watchdog Circuit. When 1, the Clock ...
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MT90812 Advance Information 22.4 Output Clocking Control Register (OCC) The register is configured as follows: Read/Write Address is: 003 H Reset Value is PCOS Bit Name 7 PCOS PLL Clock Output Select. With PE=1, when PCS = ...
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Read Address is: 004 H Reset Value is DRXE DRX Bit Name 1 CFS Overflow status of the conference accumulators. 0 C8F C8 input not present. This register is a read only register, which would generally be ...
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MT90812 Advance Information 22.7 Ringer and FSK Control Register (RFC) The Ringer and FSK Control register (RFC) controls the Ringing Source and FSK Transmitter. The Ringer and FSK control register is configured as follows: Read/Write Address is: 006 H Reset ...
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FSK Transmit Memory (FSKM) The register is configured as follows: Write Address is: 007 H Reset Value is Bit Name 7-0 D7-D0 TX FIFO buffer the MSB. A system write to the TX ...
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MT90812 Advance Information 22.10 Conference Control Register (CC) The Conference Control register is used in conjunction with the Conference Party Control registers for setting up conferences. The CC register is configured as follows: Read/Write Address is: 009 H Reset Value ...
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Tone Generation and Energy Detect Control Register (TEDC) The Tone Generation and Energy Detect register controls the two tone ringers and both A and B energy detect modules. The TEDC register is configured as follows: Read/Write Address is: 010 ...
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MT90812 Advance Information 22.12 Energy Detect A - Low Threshold (EDALT) The EDALT register is configured as follows: Read/Write Address is: 011 H Reset Value is Bit Name 7 Unused 6-0 Low Threshold Energy Detect Low ...
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The SSCA register is used to store the cadence information for Energy Detect block A. Refer to “Supervisory Signal Detection and Cadence Measurement” on page 47. The counter is used to time the cadence of the signal. When the signal ...
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MT90812 Advance Information 22.17 Supervisory Signal Cadence Register B (SSCB) Read Address is: 016 H Reset Value is Bit Name 7 p Position with respect to high and low thresholds above high threshold. 0 ...
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The coefficient is an integer value from 0 to 255 single tone is desired then one of the registers is programmed to zero. A tone output is disabled if both low and high coefficient registers are programmed to ...
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MT90812 Advance Information The IT bit will be set for the duration of the tone added to the conference. Reading any of the CPC registers in a particular conference, will show the IT bit set for that time. Channel Attenuation ...
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D-Channel RX Control (DRXC) The register is configured as follows: Read/Write Address is: 41H Reset Value is TXBO RXBO Bit Name 7 TXBO Transmitter Bit Order. When ‘0’ the first bit transmitted on the TDM channel ...
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MT90812 Advance Information 22.23 D-Channel BR Status (DRXS) The register is configured as follows: Read Address is Reset Value is Bit Name 7-3 - Unused Overrun Error. Gets set when writing ...
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A system write to the TX FIFO buffer is performed by addressing location bytes can be written to the FIFO. The length of the message is determined by the number of bytes written to the FIFO. ...
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MT90812 Advance Information 22.27 HRA CTRL Register 1(HC1) The register is configured as follows: Read/Write Address is Reset Value is SFLAG PRXSEL Bit Name 7 SFLAG Software Controlled Flag Detect (SFLAG). SFLAG is used ...
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HRA CTRL Register 2 (HC2) The register is configured as follows: Read/Write Address is Reset Value is SREOP RECTS Bit Name 7 SREOP Software Controlled RX End Of Packet (SREOP). The system can ...
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MT90812 Advance Information 22.29 HRA CTRL Register 3 (HC3) The register is configured as follows: Read/Write Address is Reset Value is Bit Name 7-4 unused Unused. 3-0 NTX4-1 Next TX Channel Number. ...
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HRA Status 1 (HS1) The register is configured as follows: Read Address is Reset Value is RXCHNL RXACT Bit Name 7 RXCHNL Receive Channel Latched (RXCHNL). When this bit is high it indicates ...
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MT90812 Advance Information 22.33 HRA Status 2 (HS2) The register is configured as follows: Read Address is Reset Value is TXCHNL TXACT Bit Name 7 TXCHNL TX Channel Number Latched (TXCHNL). The next TX channel ...
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HRA Status 4 (HS4) The register is configured as follows: Read Address is Reset Value is Bit Name 7-4 - Unused. 3-0 PTX4-1 Present Transmit Channel (PTX). The current transmit channel ...
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MT90812 Advance Information 23.0 Applications 23.1 Local TDM Channel Assignment Fig. 28 shows the channel assignment for the local TDM streams used to support the stations, trunks and analog ports for a typical configuration. There are 8 stations supported by ...
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In DN, Dual Port mode, the DNIC receives a D-Channel on CDSTi while transmitting a D-Channel on CDSTo. Fifteen channel times later (halfway through the frame) a C-Channel is received on CDSTi while a C-Channel is transmitted on CDSTo. The ...
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MT90812 Advance Information 24.0 AC/DC Electrical Characteristics Absolute Maximum Ratings* Parameter Voltage on any pin I/O (other than supply pins) 3 Current at any pin other than supply pins 4 Package power dissipation ...
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AC Electrical Characteristics - Timing Parameter Measurement Voltages Levels Characteristics TTL reference level CMOS reference level Input HIGH level Input LOW level Rise/Fall HIGH meas. pt. Rise/Fall LOW meas. pt. AC Electrical Characteristics - Input Clock Parameters Characteristics C4i clock ...
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MT90812 Advance Information AC Electrical Characteristics - 8.192 MHZ Master Clock Input Characteristics Tolerance Duty cycle † See "Notes" following AC Electrical Characteristics tables. 2.0V C4o 0.8V 3.0V C10o 2.0V * The relative phase between these two clocks is not ...
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F4i C4i c8od F4o t c4od 1 C4o t c2od 1 C2o Figure 31 - C4/F4 Input Clock Reference - ST-Bus Notes: 1. CMOS ...
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MT90812 Advance Information F8i F4o 1 C4o 1 C2o Figure 33 - C8/F8 Input Clock Reference - ST-Bus Notes: 1. CMOS output 2. TTL input ...
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C8P c8od F4o t c4od 1 C4o t c2od 1 C2o Figure 35 - C8P Input Clock Reference - ST-Bus (Timing Control, FPO bit =0) Notes: 1. CMOS output ...
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MT90812 Advance Information C16 c8od F4o t c4od 1 C4o t c2od 1 C2o Figure 37 - C16/F8 Input Clock Reference - ST-Bus ...
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VH F4i2 C4i C16 F4o 1 C4o 1 C2o Figure 39 - C16 HMVIP Input Clock Reference Notes: 1. CMOS output 2. TTL input 24.1 Timing References for ...
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MT90812 Advance Information TDM and Clock Control Data Rate Mode C8/F8, C8P C16 C8/F8, C8P, C16 EBUS 8Mb/s C4/F4 C8/F8, C8P C16/F8 C16/HMVIP C8/F8, C8P, C16 Table 22 - Timing References for TDM Streams * Clock Rate/Data Rate=1, however the ...
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FPW FPS FPH CLK stod 1 STo/EST0 V H STi/EST1 Figure GCI Timing for Local TDM Bus at 2.048 ...
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MT90812 Advance Information t FPW FPS FPH C4i C16 stod 1 EST0 EST1 V L Figure 44 - ...
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AC Parameters Referenced to Incoming Clock Signals AC parameters are either measured with respect to incoming or outgoing clock signals. A list of the Clock Control Modes for the Local or Expansion Bus streams where the AC parameters are ...
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MT90812 Advance Information AC Electrical Characteristics - Output Delay Parameters Referenced to Input Clock Signals Characteristics Output Driver Enable Delay (2.048, 4.096, 8.192 Mb/s) STo delay, active to active, High active, active to High-Z 2.048 Mb/s 4.096 Mb/s ...
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AC Parameters Referenced to Outgoing Clock Signals AC parameters are either measured with respect to incoming or outgoing clock signals. A list of the Clock Control Modes for the Local or Expansion Bus streams where the ...
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MT90812 Advance Information 24.4 HRA Timing V H F82 FPis FPih V H C82 V L F4o1 t C4od C4o1 t C2od C2o1 V H TEOP2 V L TxCEN1 V H REOP2 V L RxCEN1 V ...
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AC Electrical Characteristics - PLL Typical Intrinsic Jitter Characteristics Intrinsic jitter at C2o (2.048 MHz) Intrinsic jitter at C4o (4.096 MHz) Intrinsic jitter at C8 (8.192 MHz) Intrinsic jitter at C10o (10.24 MHz) ‡ Typical figures are at 25˚C and ...
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MT90812 Advance Information AC Electrical Characteristics - PLL Typical Input to Output Jitter Transfer for Slave Mode Characteristics Jitter at output for Input Jitter Frequency at 0.09UIpp ‡ Typical figures are at 25˚C and are for design aid only: not ...
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AC Electrical Characteristics - PLL Typical Input Jitter Tolerance for C10o 40/60 Duty ‡ Cycle Characteristics Input Jitter Tolerance for C10o 40/60 Duty Cycle ‡ Typical figures are at 25˚C and are for design aid only: not guaranteed and not ...
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MT90812 Advance Information AC Electrical Characteristics - Intel/National - HPC Multiplexed Bus Mode Characteristics 1 ALE pulse width 2 Address setup from ALE falling 3 Address hold from ALE falling 4 RD active after ALE falling 5 Data setup from ...
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AC Electrical Characteristics - Motorola Multiplexed Bus Mode Characteristics 1 AS pulse width 2 Address setup from AS falling 3 Address hold from AS falling 4 Data setup from DTA Low on Read 5 CS hold after DS falling 6 ...
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MT90812 Advance Information AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics setup from DS falling 1 2 R/W setup from DS falling 1 3 Address setup from DS falling 1 4 Address hold after DS falling ...
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Notes: Voltages are with respect to ground (Vss) unless otherwise stated. Supply Voltage and operating temperature are as per Recommended Operating Conditions. Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels 1: Measured with respect ...
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MT90812 Advance Information Dim D 100 (lead coplanarity) A Notes ...
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Index Pin 1 44-Pin Dim Min Max A - 0.096 (2.45)) A1 0.009 - (0.25) A2 0.076 0.083 (1.95) (2.10) b 0.01 0.018 (0.30) (0.45) D 0.547 BSC (13.90 BSC) D 0.394 ...
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