ATMEGA128 ATMEL Corporation, ATMEGA128 Datasheet

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ATMEGA128

Manufacturer Part Number
ATMEGA128
Description
Manufacturer
ATMEL Corporation
Datasheet

Specifications of ATMEGA128

Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Features
High-performance, Low-power AVR
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 Compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltages
Speed Grades
– 133 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers + Peripheral Control Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-chip 2-cycle Multiplier
– 128K Bytes of In-System Self-programmable Flash program memory
– 4K Bytes EEPROM
– 4K Bytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Up to 64K Bytes Optional External Memory Space
– Programming Lock for Software Security
– SPI Interface for In-System Programming
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface
– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
– Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and
– Real Time Counter with Separate Oscillator
– Two 8-bit PWM Channels
– 6 PWM Channels with Programmable Resolution from 2 to 16 Bits
– Output Compare Modulator
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Dual Programmable Serial USARTs
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with On-chip Oscillator
– On-chip Analog Comparator
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
– Software Selectable Clock Frequency
– ATmega103 Compatibility Mode Selected by a Fuse
– Global Pull-up Disable
– 53 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF
– 2.7 - 5.5V for ATmega128L
– 4.5 - 5.5V for ATmega128
– 0 - 8 MHz for ATmega128L
– 0 - 16 MHz for ATmega128
Capture Mode
and Extended Standby
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
8 Single-ended Channels
7 Differential Channels
2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
®
8-bit Microcontroller
(1)
8-bit
Microcontroller
with 128K Bytes
In-System
Programmable
Flash
ATmega128
ATmega128L
Summary
Rev. 2467PS–AVR–08/07

Related parts for ATMEGA128

ATMEGA128 Summary of contents

Page 1

... Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Operating Voltages – 2.7 - 5.5V for ATmega128L – 4.5 - 5.5V for ATmega128 • Speed Grades – MHz for ATmega128L – MHz for ATmega128 ® 8-bit Microcontroller (1) 8-bit Microcontroller with 128K Bytes In-System Programmable ...

Page 2

... PE5 Note: Overview The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. ...

Page 3

... GENERAL PURPOSE REGISTERS ALU STATUS REGISTER DATA REGISTER DATA DIR. PORTB REG. PORTB PORTB DRIVERS PB0 - PB7 ATmega128(L) PC0 - PC7 PORTC DRIVERS DATA REGISTER DATA DIR. PORTC REG. PORTC 8-BIT DATA BUS CALIB. OSC INTERNAL OSCILLATOR OSCILLATOR WATCHDOG TIMER OSCILLATOR ...

Page 4

... ATmega103, all I/O locations present in ATmega103 have the same location in Compatibility ATmega128. Most additional I/O locations are added in an Extended I/O space starting from $60 to $FF, (i.e., in the ATmega103 internal RAM space). These locations can be reached by using LD/LDS/LDD and ST/STS/STD instructions only, not by using IN and OUT instructions. The relo- cation of the internal RAM space may still be a problem for ATmega103 users ...

Page 5

... As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega128 as listed on 74. Port C (PC7..PC0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...

Page 6

... PG3 and PG4 are oscillator pins. ATmega128(L) 6 The ATmega128 is by default shipped in ATmega103 compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode is disabled. ...

Page 7

... By holding this pin low during a Power-on Reset, the device will enter the SPI Serial Pro- gramming mode. PEN has no function during normal operation. 2467PS–AVR–08/07 , even if the ADC is not used. If the ADC is used, it should be connected ATmega128(L) Table 19 on page CC 7 ...

Page 8

... A comprehensive set of development tools, application notes, and datasheets are available for download on http://www.atmel.com/avr. Note: Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ATmega128( 2467PS–AVR–08/07 ...

Page 9

... PORTG4 PORTG3 – – DDG4 DDG3 – – PING4 PING3 PORTF6 PORTF5 PORTF4 PORTF3 ATmega128(L) Bit 2 Bit 1 Bit 0 – – – – – – – – – – – – UCSZ11 UCSZ10 UCPOL1 UPE1 U2X1 ...

Page 10

... RXCIE0 $09 ($29) UBRR0L $08 ($28) ACSR ACD $07 ($27) ADMUX REFS1 $06 ($26) ADCSRA ADEN $05 ($25) ADCH $04 ($24) ADCL $03 ($23) PORTE PORTE7 $02 ($22) DDRE DDE7 ATmega128(L) 10 Bit 6 Bit 5 Bit 4 Bit 3 DDF6 DDF5 DDF4 DDF3 – – – – SP14 SP13 SP12 SP11 ...

Page 11

... I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. 2467PS–AVR–08/07 Bit 6 Bit 5 Bit 4 Bit 3 PINE6 PINE5 PINE4 PINE3 PINF6 PINF5 PINF4 PINF3 ATmega128(L) Bit 2 Bit 1 Bit 0 PINE2 PINE1 PINE0 PINF2 PINF1 PINF0 Page ...

Page 12

... Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared ATmega128(L) 12 Operation Flags Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← Z,C,N,V,H Rd ← ...

Page 13

... Clear Zero Flag SEI Global Interrupt Enable CLI Global Interrupt Disable SES Set Signed Test Flag CLS Clear Signed Test Flag 2467PS–AVR–08/07 ATmega128(L) Operation Flags then PC ← None then PC ← None Rd ← Rr None Rd+1:Rd ← Rr+1:Rr None Rd ← ...

Page 14

... Clear T in SREG SEH Set Half Carry Flag in SREG CLH Clear Half Carry Flag in SREG MCU CONTROL INSTRUCTIONS NOP No Operation SLEEP Sleep WDR Watchdog Reset BREAK Break ATmega128(L) 14 Operation Flags V ← ← ← ← ← ← 0 ...

Page 15

... Ordering Code Package ATmega128L-8AC 64A ATmega128L-8MC 64M1 ATmega128L-8AI 64A (2) ATmega128L-8AU 64A ATmega128L-8MI 64M1 (2) ATmega128L-8MU 64M1 ATmega128-16AC 64A ATmega128-16MC 64M1 ATmega128-16AI 64A (2) ATmega128-16AU 64A ATmega128-16MI 64M1 (2) ATmega128-16MU 64M1 Package Type ATmega128(L) (1) Operation Range Commercial Industrial Commercial ...

Page 16

... JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATmega128( PIN 1 IDENTIFIER ...

Page 17

... Option A Triangle 2 3 Option B Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 64M1, 64-pad 1.0 mm Body, Lead Pitch 0.50 mm, 5.40 mm Exposed Pad, Micro Lead Frame Package (MLF) ATmega128(L) C SEATING PLANE A1 A 0.08 C SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX NOTE SYMBOL A ...

Page 18

... Errata The revision letter in this section refers to the revision of the ATmega128 device. ATmega128 Rev. M • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer • Stabilizing time needed when changing XDIV Register • ...

Page 19

... Timer2 Control Register, TCCR2, or Output Compare Register, OCR2 2467PS–AVR–08/07 If ATmega128 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...

Page 20

... If ATmega128 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...

Page 21

... Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg- ister triggers an unexpected EEPROM interrupt request. Problem Fix / Workaround Always use OUT or SBI to set EERE in EECR. ATmega128 Rev. I • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer • ...

Page 22

... If ATmega128 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...

Page 23

... The behavior follows errata number 3., and the same Fix / Workaround is applicable on this errata. 2467PS–AVR–08/07 ; clear global interrupt enable XDIV, temp ; set new prescale value ; no operation ; no operation ; no operation ; no operation ; no operation ; no operation ; no operation ; no operation ; clear global interrupt enable ATmega128(L) , the first Analog Comparator conversion will CC 23 ...

Page 24

... ATmega128( ATmega128 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...

Page 25

... If ATmega128 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...

Page 26

... ATmega128 Rev. F • First Analog Comparator conversion may be delayed • Interrupts may be lost when writing the timer registers in the asynchronous timer • Stabilizing time needed when changing XDIV Register • Stabilizing time needed when changing OSCCAL Register • IDCODE masks data from TDI input • ...

Page 27

... Always use OUT or SBI to set EERE in EECR. 2467PS–AVR–08/07 If ATmega128 is the only device in the scan chain, the problem is not visible. Select the Device ID Register of the ATmega128 by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain ...

Page 28

... Updated Rev. 2467N-03/06 3. Updated 4. Updated 5. Updated 6. Updated 7. Updated 8. Updated Features in 9. Added note in 10. Updated ATmega128(L) 28 “Features” on page 1. “Data Retention” on page 8. Table 60 on page 134 and Table 95 on page “C Code Example(1)” on page Figure 114 on page 238. ...

Page 29

... Memory Interface” on page “Device Identification Register” on page “Electrical Characteristics” on page “ADC Characteristics” on page “ATmega128 Typical Characteristics” on page “Ordering Information” on page “Errata” on page 18. “Calibrated Internal RC Oscillator” on page “XTAL Divide Control Register – XDIV” on page “ ...

Page 30

... When using external clock there are some limitations regards to change of frequency. This is descried in Drive,” on page 6. Added a sub section regarding OCD-system and power consumption in the section “Minimizing Power Consumption” on page ATmega128(L) 30 18. Figure 52 on page Table 124 on page 292 “Filling the Temporary Buffer (Page Loading)” on page 280 “ ...

Page 31

... Table 22 on page 57 with typical WDT Time-out. “ADC Control and Status Register A – ADCSRA” 244. 241. 280, and “Performing a Page Write” on page ATmega128(L) 318. “ATmega128 Typical Characteristics” Table 68 on page 158, Table 102 on page 23. 38, Table 9 and Table 10 on page Table 16 on page 43 ...

Page 32

... Added Calibrated RC Oscillator “ATmega128 Typical Characteristics” on page 13. Updated “Two-wire Serial Interface” section. More details regarding use of the TWI Power-down operation and using the TWI as master with low TWBRR values are added into the data sheet. Added the note at the end of the “ ...

Page 33

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2007 Atmel Corporation. All rights reserved. Atmel marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...

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