K6R4004C1D-JC10 Samsung, K6R4004C1D-JC10 Datasheet
K6R4004C1D-JC10
Specifications of K6R4004C1D-JC10
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K6R4004C1D-JC10 Summary of contents
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... K6R4004C1D Document Title 1Mx4 Bit High Speed Static RAM(5.0V Operating). Operated at Commercial and Industrial Temperature Ranges. Revision History Rev No. History Rev. 0.0 Initial release with Preliminary. Rev. 0.1 Change Icc. Isb and Isb1 Item I CC(Commercial) I CC(Industrial SB1 1. Correct AC parameters : Read & Write Cycle mA Rev ...
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... K6R4004C1D 4Mb Async. Fast SRAM Ordering Information Org. Part Number K6R4004C1D-J(K)C( K6R4004V1D-J(K)C(I) 08/10 K6R4008C1D-J(K,T,U)C(I) 10 512K x8 K6R4008V1D-J(K,T,U)C(I) 08/10 K6R4016C1D-J(K,T,U,E)C(I) 10 256K x16 K6R4016V1D-J(K,T,U,E)C(I,L,P) 08/10 VDD(V) Speed ( ns ) PKG 32-SOJ K : 32-SOJ(LF) 3.3 8/ 36-SOJ K : 36-SOJ(LF 44-TSOP2 3.3 8/ 44-TSOP2(LF 44-SOJ K : 44-SOJ(LF 44-TSOP2 U : 44-TSOP2(LF) 3.3 8/ 48-TBGA - 2 - PRELIMINARY CMOS SRAM Temp. & Power ...
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... The K6R4004C1D is a 4,194,304-bit high-speed Static Random Access Memory organized as 1,048,576 words by 4 bits. The K6R4004C1D uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for high-speed circuit technology ...
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... K6R4004C1D ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative Voltage on V Supply Relative Power Dissipation Storage Temperature Operating Temperature Commercial Industrial * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... Chip Selection to Power Up Time Chip Selection to Power DownTime * The above parameters are also guaranteed at industrial temperature range 70°C, V =5.0V±10%, unless otherwise noted.) CC Output Loads(B) for 50Ω 1.5V L 30pF* K6R4004C1D-10 Symbol Min ...
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... (Address Controlled CS=OE (WE OLZ t LZ(4, 50% (Max.) is less than PRELIMINARY CMOS SRAM K6R4004C1D-12 Min Max WE Valid Data t HZ(3,4,5) t OHZ t DH Valid Data ...
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... K6R4004C1D TIMING WAVEFORM OF WRITE CYCLE(1) Address Data in Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address CS WE Data in Data out TIMING WAVEFORM OF WRITE CYCLE(3) Address CS WE High-Z Data in High-Z Data out (OE= Clock CW(3) t AS(4) High-Z t OHZ(6) (OE=Low Fixed CW(3) t AS(4) ...
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... K6R4004C1D NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high ...
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... K6R4004C1D PACKAGE DIMENSIONS 32-SOJ-400 #32 11.18 ±0.12 0.440 ±0.005 #1 +0.10 0.43 -0.05 0. +0.004 0.017 0.0375 -0.002 #17 #16 21.36 MAX 0.841 20.95 ±0.12 0.825 ±0.005 +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 - 9 - PRELIMINARY CMOS SRAM Units:millimeters/Inches 9.40 ±0.25 0.370 ±0.010 0.20 0.008 0.69 MIN 0.027 1. 0.051 0.10 3.76 MAX MAX 1.30 0.004 0.148 ( ) 0.051 Rev. 2.0 July 2004 +0 ...