MCM6343TS12 Freescale Semiconductor, Inc, MCM6343TS12 Datasheet

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MCM6343TS12

Manufacturer Part Number
MCM6343TS12
Description
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
256K x 16 Bit 3.3 V Asynchronous
Fast Static RAM
262,144 words of 16 bits. Static design eliminates the need for external clocks
or timing strobes.
enable (G) pins, allowing for greater system flexibility and eliminating bus con-
tention problems. Separate byte enable controls (LB and UB) allow individual
bytes to be written and read. LB controls the lower bits DQ0 to DQ7, while UB
controls the upper bits DQ8 to DQ15.
and a 44–lead TSOP Type II package.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
REV 2
2/10/98
MOTOROLA FAST SRAM
UB
LB
W
G
A
E
The MCM6343 is a 4,194,304–bit static random access memory organized as
The MCM6343 is equipped with chip enable (E), write enable (W), and output
The MCM6343 is available in a 400 mil, 44–lead small–outline SOJ package
Motorola, Inc. 1998
Single 3.3 V
Fast Access Time: 12/15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Data Byte Control
Fully Static Operation
Power Operation: 250/240/230 mA Maximum, Active AC
Commercial and Standard Industrial Temperature Option: – 40 to + 85 C
18
ADDRESS
BUFFERS
OUTPUT
BUFFER
BUFFER
BUFFER
ENABLE
BUFFER
ENABLE
ENABLE
ENABLE
WRITE
BYTE
CHIP
0.3 V Power Supply
9
9
DECODER
BLOCK DIAGRAM
ROW
256K x 16
MEMORY
ARRAY
BIT
HIGH BYTE WRITE ENABLE
LOW BYTE WRITE ENABLE
DECODER
COLUMN
HIGH BYTE OUTPUT ENABLE
LOW BYTE OUTPUT ENABLE
16
SENSE
AMPS
8
8
8
8
OUTPUT
OUTPUT
BUFFER
BUFFER
DRIVER
DRIVER
WRITE
WRITE
HIGH
BYTE
HIGH
BYTE
BYTE
BYTE
LOW
LOW
8
8
8
8
A0 – A17
E
W
G
UB
LB
DQ0 – DQ15
V DD
V SS
NC
. . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . .
DQ0
DQ1
DQ2
DQ3
V DD
V SS
DQ4
DQ5
DQ6
DQ7
MCM6343
. . . . . . . . . . . . . . . . .
PIN ASSIGNMENT
W
A
A
A
A
A
E
A
A
A
A
A
. . . . . . . . . .
PIN NAMES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+ 3.3 V Power Supply
Order this document
CASE 924A–02
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
TS PACKAGE
TSOP TYPE II
Data Input/Output
YJ PACKAGE
CASE 919–01
400 MIL SOJ
No Connection
Output Enable
by MCM6343/D
Address Input
Write Enable
A
A
A
G
UB
LB
DQ15
DQ14
DQ13
DQ12
V SS
V DD
DQ11
DQ10
DQ9
DQ8
NC
A
A
A
A
A
Chip Enable
Upper Byte
Lower Byte
MCM6343
Ground
1

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MCM6343TS12 Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Product Preview 256K x 16 Bit 3.3 V Asynchronous Fast Static RAM The MCM6343 is a 4,194,304–bit static random access memory organized as 262,144 words of 16 bits. Static design eliminates the need for external clocks ...

Page 2

TRUTH TABLE (X = Don’t Care Output Disabled Output Disabled ...

Page 3

DC OPERATING CONDITIONS AND CHARACTERISTICS ( 3 – for Industrial Temperature Offering) RECOMMENDED OPERATING CONDITIONS Parameter Power Supply Voltage Input High Voltage Input Low Voltage * V IL (min) ...

Page 4

AC OPERATING CONDITIONS AND CHARACTERISTICS ( 3 – for Industrial Temperature Offering) Logic Input Timing Measurement Reference Level Logic Input Pulse Levels . . . . . . . ...

Page 5

A (ADDRESS) Q (DATA OUT) PREVIOUS DATA VALID A (ADDRESS) E (CHIP ENABLE) G (OUTPUT ENABLE) LB, UB (BYTE ENABLE) Q (DATA OUT) MOTOROLA FAST SRAM READ CYCLE 1 (See Note 8) t AVAV t AXQX t AVQV READ CYCLE ...

Page 6

WRITE CYCLE 1 (W Controlled; See Notes 1, 2, and 3) Parameter P Write Cycle Time Address Setup Time Address Valid to End of Write Address Valid to End of Write (G High) Write Pulse Width Write Pulse Width (G ...

Page 7

WRITE CYCLE 2 (E Controlled; See Notes 1, 2, and 3) Parameter P Write Cycle Time Address Setup Time Address Valid to End of Write Address Valid to End of Write (G High) Enable to End of Write Enable to ...

Page 8

WRITE CYCLE 3 (E Controlled; See Notes 1, 2, and 3) Parameter P Write Cycle Time Address Setup Time Address Valid to End of Write Address Valid to End of Write (G High) Byte Pulse Width Byte Pulse Width (G ...

Page 9

... 44X MCM6343TS12 MCM6343TS15 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, TIE BAR BURRS AND GATE BURRS. MOLD FLASH, TIE BAR BURRS AND GATE BURRS SHALL NOT EXCEED 0.006 PER END. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH ...

Page 10

42X É É É É c É É É É É É É É SECTION A–A 40 PLACES Motorola reserves the right to make changes without ...

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