MT90220 Zarlink Semiconductor, MT90220 Datasheet
MT90220
Available stocks
Related parts for MT90220
MT90220 Summary of contents
Page 1
This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ ...
Page 2
... RX External Static RAM Utopia I/F CTRL Utopia Level 2 BUS Utopia FiFo Processor I/F Figure 1 - MT90220 Block Diagram with Built-in IMA functions for 4 IMA Groups over links Octal IMA/UNI PHY Device DS5036 Ordering Information MT90220AL -40 ° +85 ° C • Provides Header Error Control (HEC) verifi ...
Page 3
... T1/E1 rates, the MT90220 device is compliant with the ATM FORUM IMA specifications for controlling IMA groups trunks in a single chip. The MT90220 can be configured to operate in different modes to facilitate the implementation of the IMA function at both CPE and Central Office sites. For ...
Page 4
... De-Scrambling and ATM Cell Filtering ..................................................................................................... 16 3.3 ATM Receive Path in IMA Mode .............................................................................................................. 16 3.3.1 ICP Cell Processor........................................................................................................................... 17 3.3.1.1 IMA Frame Synchronization...................................................................................................... 17 3.3.1.2 Link Information......................................................................................................................... 18 3.3.1.3 RX OAM Label .......................................................................................................................... 18 3.3.2 Out of IMA Frame (OIF) Condition ................................................................................................... 18 3.3.3 Link Out Of IMA Frame (LIF) Synchronization ................................................................................. 18 3.3.4 Filler Cell Handling ........................................................................................................................... 18 3.3.5 Stuff Cell Handling ........................................................................................................................... 18 3.3.6 Received ICP Cell Buffer .................................................................................................................. 18 Table of Contents MT90220 i ...
Page 5
... MT90220 3.3.7 Rate Recovery ................................................................................................................................. 19 3.3.8 Cell Buffer/RAM Controller............................................................................................................... 19 3.3.9 Cell Sequence Recovery ................................................................................................................. 19 3.3.10 Delay Between Links ....................................................................................................................... 20 3.3.10.1 RX Recombiner Delay Value .................................................................................................... 20 3.3.10.2 RX Maximum Operational Delay Value..................................................................................... 20 3.3.10.3 Link Out of Delay Synchronization (LODS)............................................................................... 20 3.3.10.4 Negative Delay Values.............................................................................................................. 21 3.3.10.5 Measured Delay Between Links................................................................................................ 21 3.3.10.6 Incrementing/Decrementing the Recombiner Delay ................................................................. 21 3.3.11 RX IMA Group Start-Up ................................................................................................................... 21 3 ...
Page 6
... RX ICP Cell Registers Description ........................................................................................................... 57 7.6 External SRAM Register Description ....................................................................................................... 60 7.7 RX Delay Registers Description ............................................................................................................... 62 7.8 RX Recombiner Registers Description..................................................................................................... 65 7.9 TX/RX and PLL Control Registers Description......................................................................................... 67 7.10 Counter Registers Description ................................................................................................................ 73 7.11Interrupt Registers Description................................................................................................................. 75 7.12 Miscellaneous Registers Description ...................................................................................................... 78 8.0 Application Notes......................................................................................................................................... 79 8.1 Connecting the MT90220 to Various T1/E1 Framers............................................................................... 79 9.0 AC/DC Characteristics................................................................................................................................. 85 Table of Contents MT90220 iii ...
Page 7
... MT90220 Packaging Information...................................................................................................................................... 100 List of Changes.................................................................................................................................................. 102 List of Abbreviations and Acronyms............................................................................................................... 104 ATM Glossary .................................................................................................................................................... 104 iv Table of Contents ...
Page 8
... Figure 4 - Functional Block Diagram of the Transmitter in UNI Mode ................................................................... 14 Figure 5 - Cell Delineation State Diagram ............................................................................................................ 15 Figure 6 - SYNC State Block Diagram ................................................................................................................. 15 Figure 7 - The MT90220 Receiver Circuit in IMA Mode ....................................................................................... 17 Figure 8 - Example of UNI Mode Operation ......................................................................................................... 23 Figure 9 - PCM Mode 2 and 6: ST-BUS Interface for T1 (Spaced Mapping) ....................................................... 25 Figure 10 - PCM Mode 2 and 6: ST-BUS Interface for T1 (Grouped Mapping) ................................................... 26 Figure 11 - PCM Mode 4 and 8: ST-BUS Interface for E1 ...
Page 9
... MT90220 Pin Description ....................................................................................................................................................... 4 Pinout Summary ..................................................................................................................................................... 7 Table 1 - IDCR Integration Register Value ........................................................................................................... 12 Table 2 - ICP Cell Description .............................................................................................................................. 13 Table 3 - Cell Acquisition Time............................................................................................................................. 16 Table 4 - Differential Delay for Various Memory Configuration ............................................................................ 19 Table 5 - Conversion Factors Time/Cell (msec) ................................................................................................... 20 Table 6 - PCM Modes........................................................................................................................................... 24 Table 7 - PCM Clock and Mapping Options ......................................................................................................... 24 Table 8 - T1Channel Mapping Using 3 Channels Every 4 Channels ................................................................... 25 Table Channel Mapping Using 24 Consecutive Channels ...
Page 10
... Table Sync. Status Register................................................................................................................... 71 Table Sync. Status Register ................................................................................................................... 72 Table Clock Disabled Status................................................................................................................... 72 Table 89 - PLL REF Clock Disabled Status/Device Rev ..................................................................................... 72 Table 90 - Counter Byte Number 3 Register ....................................................................................................... 73 Table 91 - Counter Byte Number 2 Register ....................................................................................................... 73 Table 92 - Counter Byte Number 1 Register ....................................................................................................... 73 List of Tables MT90220 vii ...
Page 11
... MT90220 Table 93 - Select Counter Register ..................................................................................................................... 74 Table 94 - Counter Transfer Command Register ................................................................................................. 74 Table 95 - IRQ Master Status Register ................................................................................................................ 75 Table 96 - IRQ Master Enable Register .............................................................................................................. 75 Table 97 - IRQ Link Status Registers .................................................................................................................. 75 Table 98 - IRQ Link Enable Registers ................................................................................................................. 76 Table 99 - IRQ IMA Group Overflow Status Register.......................................................................................... 76 Table 100 - IRQ IMA Group Overflow Enable Register....................................................................................... 76 Table 101 - IRQ IMA Overflow Status Registers ...
Page 12
... PIN MQFP Figure 2 - Pin Connections MT90220 104 VSS TXCKIO_2 102 VDD TXCKIO_3 100 VSS DSTO_3 98 TXSYNCIO_3 DSTO_4 96 TXSYNCIO_4 VSS ...
Page 13
... Transmit Address .Five bit wide true data driven from the ATM to the PHY layer to 37, 38 [4:0] poll and select the appropriate MT90220. TxAddr[4] is the MSB. Each MT90220 keeps its addresses. The value for the Tx and Rx portions of the MT90220 can be different ATM Output Port Signals (UTOPIA Receive Interface) (see Note 1) 205, 206, RxData O UTOPIA Receive Data Bus ...
Page 14
... O Static Memory Read/Not Write . If low, data is written from the MT90220 to the memory. If high, data is read from the memory to the MT90220. 198, 199 sr_cs_1 Static Memory Chip Control Signal . 44, 45, 46, up_d I/O Processor Data Bus ...
Page 15
... I Receive line 8KHz Frame Pulse 7-0 . This signal represents the 8 KHz reference 126, 133, [7:0] received from the incoming line. The MT90220 can be programmed to 135, 142, accept different 8 KHz pulse formats at this input. 144, 150 1. For ST-BUS applications low going pulse (F0), which delimits the 32 channel frame of ST-BUS interface at DSTi and DSTo lines ...
Page 16
... Pin Description (continued) Pin # Name I/O 74 Clk I System Clock (25 MHz nominal the MT90220, this clock is used for all internal operations of the device. 76 Test1 I Test1. This signal should be high for normal operation. The signal should be pulled up for normal operation. 54 Reset I System Reset. This is an active low input signal. It causes the device to enter the initial state ...
Page 17
... Link Addition, Removal or Restoration The addition, removal or restoration of a link is controlled by software using the various control registers in the MT90220 and in the framers. Decisions are based on the MT90220 and framers status registers. 1.1.4 Interrupt The MT90220 provides numerous registers and counters to implement a polling and/or interrupt mechanism for tracking link and IMA Group status ...
Page 18
... Static RAM • various performance monitoring counters • 8-bit microprocessor interface (adaptable to Intel or Motorola interfaces) The MT90220 can be separated into four major independent blocks and three support blocks. The four major independent blocks are: • the ATM Transmit Path • the ATM Receive Path • ...
Page 19
... UNI Filler cell (in IMA mode) to the line. The default values for the Idle and the Filler cells comply with the ATM IMA Specification and are pre- loaded in the MT90220 following a reset. The TX Cell RAM Control register can be used to re-initialize the + used to TX Cell RAM ...
Page 20
... Idle Cell used in UNI mode The remaining 58 cells can be assigned to any of the 20 TX FIFOs. The TX FIFOs are divided UTOPIA FIFOs and 8 TX Link FIFOs.The MT90220 implements one TX UTOPIA FIFO for each link when used in UNI and one for each IMA Group for a total UTOPIA FIFOs ...
Page 21
... ICP Cell Generator Once per IMA frame, an ICP cell is transmitted on each link of the IMA Group. The content of the ICP cell is controlled both by MT90220 and software. The software content of the ICP cell bytes is stored in buffer RAM. A copy of the ICP cell for each group is kept in the internal Transmitter Cell RAM ...
Page 22
... ICP cell into the internal Cell RAM area and to start using this new ICP cell. The MT90220 uses a flag (status bit) to indicate that this transfer is underway. Changes should not be made to the content of the ICP cell in the buffer area until the transfer to the internal memory is complete ...
Page 23
... IMA Group. LID should not be changed when a group is operational. Ensure each link that is part of an IMA group has a unique LID (note that the MT90220 does not verify LIDs). • Write the ICP Cell Offset value to TX ICP Cell Offset registers. This value depends on the value of M ...
Page 24
... The ATM Receive Path The receive path corresponds to the cell flow from the T1/E1 interfaces to the ATM UTOPIA Interface. The MT90220 provides cell delineation and optional cell filtering to discard Unassigned or Idle cells on each link. The incoming cells are stored in the external RAM required in IMA mode to perform cell recovery due to delay variation between the links introduced by the network ...
Page 25
... Incoming Idle and Unassigned cells can be detected and dropped automatically. 3.3 ATM Receive Path in IMA Mode The block diagram at Figure 7 illustrates the MT90220 IMA mode receive path. The receiver must rearrange the incoming bit streams from N-links (1 ≤ N ≤ 8) into a single UTOPIA cell stream ...
Page 26
... S/P Delineation DSTi [7] Link Info Registers Figure 7 - The MT90220 Receiver Circuit in IMA Mode 3.3.1 ICP Cell Processor In IMA mode, the transmitter inserts special ICP cells in the various outgoing streams every M ATM cells to comply with the IMA specification. The receive block is using these ICP cells to synchronize with the Far End transmit side and to reconstruct the ATM cell original sequence ...
Page 27
... LIF status bit to determine when the condition is cleared. 3.3.4 Filler Cell Handling The MT90220 scans each incoming cell received for the Filler Cell Indication code. Filler cells are written to external RAM to keep the IMA frame aligned. They are automatically discarded after being read from the external RAM by the recombiner ...
Page 28
... ICP cell and has room for up to three new ICP cells. 3.3.7 Rate Recovery The MT90220 computes the internal RX IMA Data Cell Rate (IDCR) for each IMA Group. The cell rate of the reference link is integrated over a programmable period of time. Software must specify the reference ...
Page 29
... Cell Delay Variation (CDV). To provide an optimal recombiner delay, the MT90220 adds a guardband delay to the current worst case recombination delay when the IMA Group is first started up. Guardband delay is programmable and minimizes the number of disruptions that would otherwise occur in accommodating link delays exceeding the current worst case ...
Page 30
... Guardband/Delta Delay register and then a command to increase the delay is issued (using the Increment/Decrement Delay Control register). The MT90220 device stops the recombiner process for the amount of time specified and then resumes the recombiner process. No cells are lost but there is an effect on the CDV. The increment ...
Page 31
... IMA group or to UNI Mode. 3.4 The ATM Receive Path in UNI Up to eight incoming T1/E1 lines can be connected to the MT90220 receiver and forwarded to the UTOPIA L2 interface served by an external ATM- Layer device. Figure 8 illustrates four of the eight possible UTOPIA ports that can be addressed through the UTOPIA Interface. The size of the RX UTOPIA FIFO is fi ...
Page 32
... Transmit PCM blocks are independent from the Receive PCM blocks. The TX port of a framer can be connected to any of the MT90220 TX UTOPIA Input ports and the RX port of a framer can be connected to any of the MT90220 RX UTOPIA Output ports. 4.1 Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters Each T1/E1 link has a S/P and P/S unit assigned ...
Page 33
... MT90220 from the TXCK and is independent from (not aligned with) the RXSYNC or other TXSYNC signals. 4.2 PCM System Interface Modes There are 8 major modes of operation for the PCM interface. The only difference between modes and modes the direction of the TXCK and TXSYNC signals. In the PCM modes the direction is the opposite of what is defi ...
Page 34
... In the PCM Mode 6, the TXCK and TXSYNC pins are defined as outputs. The source for the TXCK is selected using TX PCM Link Control register number 2 and can be any of the eight RXCK or four external REFCK clocks. As there is no PLL inside the MT90220, the source frequency has valid ST ...
Page 35
... TXCK is selected using TX PCM Link Control register number 2 and can be any of the eight RXCK or four external REFCK clocks. As there is no PLL inside the MT90220, the source frequency has valid ST-BUS Clock signal (i.e., 4.096 MHz). The TXSYNC signal is generated by the MT90220 and meets the ST-BUS format ...
Page 36
... This allows the MT90220 to operate with the majority of available off-the-shelf T1 framers. When operating in the generic PCM system Interface at 1.544 MHz, the MT90220 does not use the first bit ... Channel 0 bit 7 Channel 0 bit 0 Unused or Unused or ...
Page 37
... The edge of the RXCK and TXCK signals that is used to sample the incoming, and transmit the outgoing, data is fully programmable on a per link basis. This allows the MT90220 to operate with the majority of off-the-shelf E1 framers. The MT90220 does not use timeslots 0 and 16 to perform the G.804 transmission function (see Figure 13) ...
Page 38
... TX Cell FIFO RXCK 0-7 REFCK 0-3 RXCK 0-7 Figure 14 - TXCK and TXSYNC Output Pin Source Options Channel 0 bit 0 Channel 1 bit 7 ... Unused or ... High Impedance ... ... ... ... Channel 16 bit 0 Channel 17 bit 7 ... Unused or ... High Impedance ... ... ... ... Cell Delineation S/P P/S MT90220 ... ... Bit Cell ... ... ... ... ... Bit Cell ... ... ... ... DSTi RXCK RXSYNC TXSYNC DSTo TXCK PLLREF0 PLLREF1 29 ...
Page 39
... TXClav and/or RXClav signal will be driven High or Low. When the address does not correspond to any enabled PHY address inside the MT90220, the TXClav and RXClav signal are in High impedance mode. The use of an external pull-down may be required for the proper operation of the Utopia bus in MPHY mode ...
Page 40
... HEC counter is not incremented. 5.2 ATM Output Port The MT90220 supports a 53 byte cell stream via the ATM output port. Cells received at the ATM output port are stored in the RX UTOPIA FIFO before being processed by the UTOPIA Interface. The output of the UTOPIA Interface can be stopped by the ATM Layer device by de-asserting the RxEnb* signal ...
Page 41
... RX UTOPIA FIFO. 5.6 UTOPIA Operation in IMA Mode In IMA mode eight MT90220s, with up to four UTOPIA ports each (one port per IMA Group), can be served by an external UTOPIA L2 ATM-Layer device. This provides different logical IMA- channels ...
Page 42
... ATM Layer Device Figure 17 - ATM Mixed-Mode Interface to One MT90220 6.0 Support Blocks 6.1 Counter Block The MT90220 includes 112 24-bit counters to provide statistical information on the device’s operation. All the counters are cleared by a hardware reset. A maskable interrupt can be generated when the counter overflows. ...
Page 43
... IRQ and ’xxx00010’ disables (masks) it. 6.2 Interrupt Block The MT90220 can generate interrupts from many sources. All interrupt sources can be enabled or disabled. Write action is required to clear the source of interrupt. Interrupts are grouped on a per link basis, with six sub-categories for each link and two special types for the IMA Group confi ...
Page 44
... ICP Cell or the occurrence of the end of an IMA frame. The Frame status bits are cleared by writing 0 to the bit. The Ready bit is set to 1 when the transfer is complete. Bit latched bit in the IRQ Link 0 Status register and is cleared by overwriting it with 0. MT90220 interrupt sources are enabled 35 ...
Page 45
... RX UTOPIA FIFO associated with an IMA Group. This is the RX UTOPIA IMA Group FIFO Overflow Enable register. 6.3 Register and Memory Map 6.3.1 Access to the Various Registers Since the MT90220 and microprocessor operate from two different clock sources, access to a MT90220 register is asynchronous. synchronized ...
Page 46
... Direct Access Direct access registers can be written or read directly by the microprocessor, without having to use otherregisters. Upon a write access to the MT90220 internal registers, the data is stored in an internal latch and transferred to the destination register within 2.5 system clock cycles (100 nsec at 25 MHz). ...
Page 47
... MT90220 7.0 Register Descriptions Reset Address Access Value (Hex) Type (Hex) 000 - 007 D 00 008 - 00B D 00 00C D 00 00D D 00 00E D 00 040 - 047 D 00 048 - 04B D 00 04C D 00 04D D 00 205 D 00 221 D 00 140 D 00 150 D 00 14A ...
Page 48
... Enable Recombination Status 79 RX Reference Link Control Registers 80 RX IDCR Integration Register 81 TX PCM Link Control Register # PCM Link Control Register # PCM Link Control Register 84 PLL Reference Control register 85 Clock Activity Register 86 RX Sync. Status Register Table 11 - Register Summary MT90220 Description 39 ...
Page 49
... MT90220 Reset Address Access Value (Hex) Type (Hex) 09E D 00 09C D 00 09D D 10 214 S 00 215 S 00 216 S 00 217 S 00 207 S 00 232 D 00 218 D 00 222 - 229 D 00 219 - 220 D 00 235 D 00 204 D 00 210 - 213 D 00 ...
Page 50
... Enable UTOPIA PHY address of link enables the PHY port Address. UNI mode. 1 R/W Enable UTOPIA PHY address of link enables the PHY port Address. UNI mode. 0 R/W Enable UTOPIA PHY address of link enables the PHY port Address. UNI mode. Table 14 - UTOPIA Input Link PHY Enable Register Description Description Description MT90220 . 41 ...
Page 51
... MT90220 Address (Hex): 00D Direct access 1 register to enable the IMA Groups. The TxClk signal must be active for correct register operation Reset Value (Hex): 00 Bit # Type 7-4 R/W Reserved. Write all 0’s. 3 R/W Enable UTOPIA PHY address of IMA Group enables the PHY port Address. ...
Page 52
... Enable UTOPIA PHY address of IMA Group enables the PHY port Address. 1 R/W Enable UTOPIA PHY address of IMA Group enables the PHY port Address. 0 R/W Enable UTOPIA PHY address of IMA Group enables the PHY port Address. Table 20 - UTOPIA Output Group PHY Enable Register Description Description Description MT90220 43 ...
Page 53
... MT90220 Address (Hex): 205 Direct access 1 register to enable interrupts from IMA Groups. The RxClk signal must be active for correct register operation Reset Value (Hex): 00 Bit # Type 7-4 R Unused. Read all 0’s. 3 R/W When set to 1, the corresponding bit in the Overflow Status register can generate an interrupt ...
Page 54
... TX FIFO Length Link 1. 3:0 R/W TX FIFO Length Link 0. Table FIFO Length Definition Register 1 Address (Hex): 14B Direct access Reset Value (Hex): 33 Bit # Type 7:4 R/W TX FIFO Length Link 3. 3:0 R/W TX FIFO Length Link 2. Table FIFO Length Definition Register 2 Description Description Description Description MT90220 45 ...
Page 55
... MT90220 Address (Hex): 14C Direct access Reset Value (Hex): 33 Bit # Type 7:4 R/W TX FIFO Length Link 5. 3:0 R/W TX FIFO Length Link 4. Table FIFO Length Definition Register 3 Address (Hex): 14D Direct access Reset Value (Hex): 33 Bit # Type 7:4 R/W TX FIFO Length Link 7. 3:0 R/W TX FIFO Length Link 6. ...
Page 56
... Defines the ICP cell offset of link N. The value of M determines which significant bits are used as follows: M=256; bits 7-0 are used, M=128; bits 6-0 are used; M=64; bits 5-0 are used; M=32; bits 4-0 are used. Table ICP Cell Offset Registers Description Description Table Link ID Registers Description MT90220 47 ...
Page 57
... MT90220 Address (Hex): 200 - 203 Direct access 1 register per TX IMA Group Reset Value (Hex): 05 Bit # Type 7:4 R Unused. Read all 0’s. 3-0 R/W Defines the integration period for an IMA Group: 1111: Reserved, do not use 1110: 2 1101: 2 1100: 2 1011: 2 1010: 2 1001: 2 1000: 2 0111: 2 0110: 2 0101: 2 ...
Page 58
... Link 4 is not in IMA mode means Link 3 is not in IMA mode means Link 2 is not in IMA mode means Link 1 is not in IMA mode means Link 0 is not in IMA mode. Table IMA Mode Status Register Description Description MT90220 49 ...
Page 59
... MT90220 7.3 TX ICP Register Description Tables describe the TX ICP registers. Address (Hex): 148 Direct access Controls the transfer of TX ICP cells and frame pulse indication Reset Value (Hex): 0F Bit # Type 7 R/W When 1 indicates the end of a frame was detected in IMA Group #3. Cleared by writing 0. ...
Page 60
... R/W HEC is always calculated and inserted by the MT90220 R/W OAM, should be set to 0x01 7 06 R/W Cell ID, Link ID. The bit 7 (Cell ID) is controlled by the MT90220, the Link ID is provided by the TX Link ID Register R/W IMA Frame Sequence Number. Inserted by the MT90220 R/W ICP Cell Offset. Inserted by the MT90220 based on the Link Offset register info ...
Page 61
... MT90220 7.4 RX Registers Description Tables describe the Receive registers. Address (Hex): 100 -107 Direct access 1 register per link Reset Value (Hex): 0C Bit # Type 7 R/W A Value of 0 select to count the number of Stuff cells received by the physical link. A value of 1 selects to count the total number of cells received by the link. ...
Page 62
... An OIF state was detected on the physical link 2. Cleared by writing R/W An OIF state was detected on the physical link 1. Cleared by writing R/W An OIF state was detected on the physical link 0. Cleared by writing a 0. Description Description Table OAM Label Register Description Table OIF Status Register MT90220 53 ...
Page 63
... MT90220 Address (Hex): 116 Direct access 1 register for the 8 RX links Reset Value (Hex): 00 Bit # Type 7 R/W Write clear the OIF counter for physical link 7. 6 R/W Write clear the OIF counter for physical link 6. 5 R/W Write clear the OIF counter for physical link 5. ...
Page 64
... The value is updated on completion of the write action in the RX Load Values register Reset Value (Hex): 00 Bit # Type 7:0 R Content of the OIF counter for the link selected in the RX Load Values/Link Select register. Table Link OIF Counter Value Register Description Description Description Description MT90220 55 ...
Page 65
... MT90220 Address (Hex): 11D Direct access The value is updated on completion of the write action in the RX Load Values register Reset Value (Hex): 20 Bit # Type 7 R LIF state of the link selected in the RX Load Values/Link Select register LCD state of the link selected in the RX Load Values/Link Select register. ...
Page 66
... These 2 bits select the type of cells stored in the RX ICP Cell buffer for physical link 0. 00: valid RX ICP Cells with changes. 01: All valid RX ICP Cells. 10: All valid RX Cells. 11: No cell written into RX buffer. Table ICP Cell Type RAM Register 1 Description MT90220 57 ...
Page 67
... MT90220 Address (Hex): 1C1 Direct access Access for RX link 7-4 Reset Value (Hex): 00 Bit # Type 7:6 R/W These 2 bits select the type of cells stored in the RX ICP Cell buffer for physical link 7. 00: valid RX ICP Cells with changes. 01: All valid RX ICP Cells. 10: All valid RX Cells. ...
Page 68
... External SRAM Test Mode is disabled, 1: External SRAM Test Mode is enabled. 6 R/W Reserved, write 0 for normal operation. 5 R/W Reserved, write 0 for normal operation. 4 R/W Reserved, write 0 for normal operation. 3 R/W Reserved, write 0 for normal operation. 2:0 R/W Reserved, write 0’s for normal operation. Table 60 - Test Mode Enable Register Description Description MT90220 59 ...
Page 69
... MT90220 7.6 External SRAM Register Description Tables describe the External SRAM registers. Address (Hex): 292 Direct access Defines the external SRAM configuration Reset Value (Hex): 08 Bit # Type 7 R/W Write reset the receiver. 0 means no action. 6 R/W Write reset the transmitter. 0 means no action. ...
Page 70
... Synchronized access Set address before the transfer is initiated with the RX External SRAM Control register Reset Value (Hex): 00 Bit # Type 7:5 R Unused. Read all 0’s 4 R/W Reserved, write 0 for normal operation. 3:0 R/W RX External SRAM Read/Write Address bit 19:16. Table External SRAM Read/Write Address 2 Description MT90220 61 ...
Page 71
... R Toggle Bit. 5 R/W Write 0 to initiate a transfer from the MT90220 registers to the external RAM. Write 1 to initiate a transfer from the external RAM to the MT90220 registers. 4 R/W Reserved, write 0 for normal operation. 3 R/W When Test Mode bit is 1; write 1 to enable the direct addressing mode to the External SRAM ...
Page 72
... Number of the physical link associated with the value in the RX Delay register. This value is not valid when reading the Maximum Delay over time value is read. Table Delay Link Number Register Description Description Table Delay MSB Register Description Table Delay LSB Register Description MT90220 63 ...
Page 73
... MT90220 Address (Hex): 288, 28A, 28C, 28E Direct access 1 value for each IMA Group to use for start-up and adding/removing delay (value in number of cells) Reset Value (Hex): 04 Bit # Type 7:0 R/W LSB of the Guardband/Delay value Bits 7:0. Table Guardband/Delta Delay LSB Register Address (Hex): ...
Page 74
... A 1 enables the circuitry to wait for the first User cells to be received before adding the link 0 to the recombiner process will include the link 0 in the recombiner as soon enabled in the RX Recombiner register. Table Recombiner Delay Control Registers Description Table Recombiner Registers Description MT90220 65 ...
Page 75
... MT90220 Address (Hex): 29F Direct access Reset Value (Hex): 00 Bit # Type 7:0 R/W Each bit reports the recombination status for a link means that the recombination is enabled. The bit 7 reports for link 7 and forth. Do not write to this register. Table 78 - Enable Recombination Status ...
Page 76
... These 4 bits are used to select the source for the TXCK for the link: The valid combinations are: 0000: RXCK0 0001: RXCK1 0010: RXCK2 0011: RXCK3 0100: RXCK4 0101: RXCK5 0110: RXCK6 0111: RXCK7 1000: REFCK0 1001: REFCK1 1010: REFCK2 1011: REFCK3 Table PCM Link Control Register Number 2 Description MT90220 67 ...
Page 77
... MT90220 Address (Hex): 088 - 08F Direct access 1 reg. per TX link Reset Value (Hex): 00 Bit # Type 7 R/W PCM port tri-state control. TXCLK, TXSYNC and DSTO outputs are active when the bit is 1. The outputs of the Port is in tri-state if the bit is 0. 6:5 R/W 00: T1, Generic Mode, 1.544MHz or 2.048 MHz Clk, (Mode 01: T1, ST-BUS Mode, 4 ...
Page 78
... RX Clock polarity: Falling edge is used to sample data at DST if bit is 1. Rising edge of RXCK is used to sample data at DSTi if bit is 0. Valid in Generic PCM mode only 0 R/W RX frame pulse polarity. Positive if bit is 1. Negative if bit is 0. Valid in Generic PCM mode only. Table PCM Link Control Register Description MT90220 69 ...
Page 79
... MT90220 Address (Hex): 098 Direct access Reset Value (Hex): 00 Bit # Type 7 R/W Writing a 1 forces the deselecting of the selected clock when it failed. 6 R/W Reserved. Set to 0 for normal operation. 5:3 R/W These 3 bits are used to select the source for the signal at PLLREF1: The valid combinations are: ...
Page 80
... PCM RX Sync signal faulty on link 3. Cleared by writing ’0’. 2 R/W PCM RX Sync signal faulty on link 2. Cleared by writing ’0’. 1 R/W PCM RX Sync signal faulty on link 1. Cleared by writing ’0’. 0 R/W PCM RX Sync signal faulty on link 0. Cleared by writing ’0’. Table Sync. Status Register Description Table 85 - Clock Activity Register Description MT90220 71 ...
Page 81
... MT90220 Address (Hex): 09E Direct access 1 reg. for all 8 RX links Reset Value (Hex): 00 Bit # Type 7 R/W PCM TX Sync signal faulty on link 7. Cleared by writing ’0’. 6 R/W PCM TX Sync signal faulty on link 6. Cleared by writing ’0’. 5 R/W PCM TX Sync signal faulty on link 5. Cleared by writing ’0’. ...
Page 82
... Reset Value (Hex): 00 Bit # Type 7:0 R/W A read accesses the byte #1 (Least Significant Byte) of the Counter that was selected in the Select Counter register. A write will hold the value to be written to the selected counter. Table 92 - Counter Byte Number 1 Register Description Description Description MT90220 73 ...
Page 83
... MT90220 Address (Hex): 217 Synchronized access The value in this register is used for internal access to the counter when the transfer command is issued Reset Value (Hex): 00 Bit # Type 7:4 R/W The valid bit combinations are: 1011: UTOPIA Input, counter of all cells for link 1010: UTOPIA Input, counter of Idle cells for link ...
Page 84
... Bit 7 is present only for Link 0. In all other Link Status Registers, this bit is set Bit 6 is present only for Link 0. In all other Link Status Registers, this bit is set to 0. Description Table 95 - IRQ Master Status Register Description Table 96 - IRQ Master Enable Register Description Table 97 - IRQ Link Status Registers MT90220 75 ...
Page 85
... MT90220 Address (Hex): 219 - 220 Direct access 1 Enable register per link Status reg Reset Value (Hex): 00 Bit # Type 7:0 R/W Each bit set to ’1’ will enable the generation of the interrupt when the corresponding bit in the IRQ Link Status register is set. Address (Hex): ...
Page 86
... This bit is set when the RX PCM Link counter for HEC Errored Cells associated with a link overflows. 0 R/W This bit is set when the RX PCM Link counter for bad ICP Cells associated with a link overflows. Table 103 - IRQ Link UNI Overflow Status Registers Description Description MT90220 77 ...
Page 87
... MT90220 7.12 Miscellaneous Registers Description Tables 104 to 106 describe the General Status and Test Register. Address (Hex): 206 Direct access Reset Value (Hex): 10 Bit # Type 7:4 R Device Revision Number: reads 0001. 3 R/W Set when the UTOPIA output clock is missing or too slow. This latched bit is cleared by writing a 0 ...
Page 88
... ATM cells in a round-robin fashion and sends them over grouped T1/E1 lines in a logical connection (on public or private networks) and recombines the cells to recover the original high- bandwidth stream at the receiving end. Zarlink’s MT90220 is ideally suited to implement the IMA function. 8.1 Connecting the MT90220 to Various T1/E1 Framers ...
Page 89
... MT90220 UTOPIA BUS DSTo[0:7] DSTi[0:7] ATM LAYER BUS MT90220 DEVICE TXCK[0-7] RXCK[0-7] TXSYNC[0-7] RXSYNC[0-7] Clock Recovery and Dejitter Figure 19 - PCM MODE 2 AND 4: Synchronous ST-BUS Mode (Using ST-BUS/2.048 Mbps Backplane Compatible Framers) 80 TDM Back-Plane ST-BUS (ST-BUS) I/F DATA Data Lines ST-BUS I/F DATA ...
Page 90
... TXCK[7] RXSYNC[7] TXSYNC[7] DSTo[7] Note: The MT9074 #1 is configured in Line Sync. mode and all other MT9074s are configured in Bus Master mode. Figure 20 - PCM MODE 2 and 4 CTC Mode (Using MT9074 T1/E1 Single Chip Transceivers) MT90220 MT9074/#1 DSTo C4b F0b DSTi 20 MHz +/-50 PPM MT9074#N ...
Page 91
... MT90220 DSTi[0] RXCK[0] TXCK[0] RXSYNC[0] TXSYNC[0] DSTo[0] UTOPIA MT90220 LEVEL 2 DEVICE BUS DSTi[7] RXCK[7] TXCK[7] RXSYNC[7] TXSYNC[7] DSTo[7] Note: All MT9074 are configured in Line Sync. mode (Using Zarlink MT9074 T1/E1 Single Chip Transceivers) 82 MT9074 DSTo C4b F0b DSTi MT9074 DSTo C4b F0b ...
Page 92
... Applications with Asynchronous Lines) PCM Data 1.544 or 2.048 MHz 8 kHz [T7] 1.544 or 2.048 MHz 8 kHz [R7] PCM Data PCM Data 1.544 or 2.048 MHz 8 kHz [T7] 1.544 or 2.048 MHz 8 kHz [R7] External Source MT90220 T1/E1 Legacy Trunks Framers at 1 Mbps Legacy Trunks T1/ Mbps Framers Legacy Trunks at 1 Mbps T1/E1 Framers 83 ...
Page 93
... Note: The PM4388 is configured in Clock Master, full DS1 mode Figure 23 - PCM MODE 5 and 7: Asynchronous Operations 84 TXCKi[0] TXSYNCo[0] DSTo[0] DSTi[0] RXSYNC[0] RXCKi[0] TXCKi[7] TXSYNCo[7] DSTo[7] DSTi[7] RXSYNC[7] RXCKi[7] MT90220 (Using Octal T1 Framer) TLCLK0 EFP0 TLD0 ED0 ID0 IFP0 RLD0 ICLK0 RLCLK0 TLCLK7 EFP7 TLD7 ED7 ...
Page 94
... IL µA 35 115 222 2 0 µA 6 MT90220 Min Max -0.3 3.9 -1.0 6.5 I -10 10 -40 125 Units Test Conditions 85 ˚C 3.6 V Test Conditions System Clock 25 MHz. PCM clock @ 2.048MHz For pins DSTi[7:0], REFCK[3:0], TXCKio[7:0], TXSYNC[7:0], ...
Page 95
... MT90220 DC Electrical Characteristics* - Characteristics Sym 13 Output Low Current I OL (Digital Outputs) 14 Output Pin C Capacitance 15 High Impedance I OZ Leakage (Digital I/ Electrical Characteristics are over recommended temperature and supply voltage ° ‡ Typical figures are =3.3V, and for design aid only: not guaranteed and not subject to production testing ...
Page 96
... PCM Bit Bit Cell Stream TXSYNC 0-7/ RXSYNC 0-7 t TXCK 0-7/ RXCK 0-7 DSTi0-7 t SOD DSTo0 Figure 25 - ST-BUS Timing Diagram Bit Cell Bit Cell t FPH FPS SIH t SIS MT90220 t 4cyc ...
Page 97
... MT90220 AC Electrical Characteristics Characteristic 1 TXCK/RXCK Clock period for T1, 1.544 MHz mode for E1, 2.048 MHz mode 2 TXCK/RXCK Clock Width High or Low for T1, 1.544 MHz mode for E1, 2.048 MHz mode 3 Frame Pulse Setup 4 Frame Pulse hold 5 DSTi 0-7 Serial Input Setup 6 DSTi 0-7 Serial Input Hold ...
Page 98
... I t FPD t t FPH FPS t SIH t SIS t FPS I t FPSH t FPD MT90220 Positive Polarity Selected CYC Bit Sampled With Falling Edge Positive Polarity Selected CYC Bit Transmitted With Rising Edge Negative Polarity Selected Rising Edge Bit Sampled With Negative Polarity Selected ...
Page 99
... MT90220 AC Electrical Characteristics - Utopia Interface Transmit Timing Signal name TxClk TxData[7:0], TxSOC, TxEnb*, TxAddr[4:0] TxClav[0] AC Electrical Characteristics - Receive Timing Signal name RxClk RxEnb*, RxAddr[4:0] RxData[7:0], RxSOC, RxClav[0] Note 1 - The RXCLK signal needs to be synchronous with the system clock refer to paragraph 5.2. 90 DIR ...
Page 100
... Figure 28 - Setup and Hold Time Definition Clock Signal Valid Signal tT11 Signal Going Low Impedance From Clock Figure 29 - Tri-State Timing tT6, tT8 Input Hold From Clock Signal Going High Impedance t 1 T10 tT12 Signal Going High Impedance From Clock MT90220 91 ...
Page 101
... MT90220 AC Electrical Characteristics - External Memory Interface Timing - Read Access Item Description t MT90220 System Clock Period CLK t Read Cycle Time RC t Address Setup Time AVRS t Address Hold Time AVRH t Chip Select Setup Time CSRS t Chip Select Hold Time CSRH t Write Enable* Setup Time ...
Page 102
... Note: The SR_WE signal stays LOW until a READ cycle performed Figure 31 - External Memory Interface Timing - Write Cycle Min clk t avws Address Valid csws cswh t wews t wds Data Valid MT90220 Typ Max -10 ns CLK avwh t wewh t wdh 93 ...
Page 103
... MT90220 pre-load register on the rising edge of the UP_CS* signal. In Intel timing mode, the data is clocked into MT90220 pre-load register on the rising edge of the UP_R/W* signal. Right after that transition, the data is transferred to the MT90220’s internal register. ...
Page 104
... UP_D low impedance after falling edge of UP_OE UP_OE UP_CS t ws UP_R/W UP_AD[9:0] UP_D[7:0] Figure 32 - CPU Interface Timing - Read Access Sym Min Typ Max ACC 2 Address Valid t oe Data Valid t acc MT90220 Units Test Conditions ...
Page 105
... MT90220 AC Electrical Characteristics - CPU Interface Motorola Timing - Write Cycle Characteristics 1 UP_R/W* set-up time to UP_CS* falling edge 2 Address and Data set up before rising edge of UP_CS* 3 UP_AD and Data hold time after UP_CS rising edge 4 UP_R/W low after rising edge or UP_CS 5 UP_CS* high before next UP_CS low Note 1 - For internal synchronization purposes, 2 system clock cycles are required between a write access and the next valid access ...
Page 106
... UP_A[9:0] UP_D[7:0] Figure 34 - CPU Interface Intel Timing - Write Access Sym Min Typ Max ADH t 1 CSH (see Note 1) t csh t adh ADDRESS VALID t su DATA VALID MT90220 Units Test Conditions cycle system clock ...
Page 107
... MT90220 AC Electrical Characteristics - JTAG Port and RESET Pin Timing Parameter TCK period width TCK period width LOW TCK period width HIGH TDI setup time to TCK rising TDI hold time after TCK rising TMS setup time to TCK rising TMS hold time after TCK rising ...
Page 108
... RESET pulse width CLK RESET Symbol Min Typ TCLK t 20 TCLKL t 20 TDKH t CLKR t CLKF t 10 RST t t clkrl clklf t rst Figure 36 - System Clock and Reset MT90220 Max Units Test Conditions clk period t tclk t t tclkl tclkh 99 ...
Page 109
... MT90220 Pin # Notes: 1) Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) 4) JEDEC Standard 2.6mm Footprint MS-29 5) MQFP-208 Package complies to JEDEC Standard MS-29 Figure 37 - Metric Quad Flat Package - 208 Pin 100 D D1 See Detail θ2 θ1 θ3 θ ...
Page 110
... Metric Quad Flat Package Dimensions 208-Pin Min 0.01 (0.25) .126 (3.20) .007 (0.18) .007 (0.18) .003 (0.076) .003 (0.076) 1.197 (30.40) 1.098 (27.90) .020 BSC (0.5 BSC) 1.197 (30.40) 1.098 (27.90) .018 (0.45) .051 REF (1.30 REF MT90220 Max .161 (4.10) .142 (3.60) .011 (0.28) .009 (0.28) .008 (0.20) .006 (0.152) 1.212 (30.80) 1.106 (28.10) 1.212 (30.80) 1.106 (28.10) .030 (10.76 101 ...
Page 111
... MT90220 List of Changes Page Numbers Newer Older ...
Page 112
... Replaced: “decreases” With: “decreases or” “5 ” With: “6 ” “used.” With: “used for any MT90220 port.” “The cell available satus line (…” “port. ” With: “port in MPHY mode. ” “In this mode, the bit …” ...
Page 113
... MT90220 List of Abbreviations and Acronyms AAL ATM Adaptation Layer ATM Asynchronous Transfer Mode CBR Constant Bit Rate CDV Cell Delay Variation CPE Customer Premises Equipment CRC Cyclic Redundancy Check CTC Common Transmit Clock DSU Data Service Unit FE Far End GSM Group State Machine ...
Page 114
... OCD anomaly persists for the period of time specified in ITU-T Recommendation I.432(30)¸. The LCD defect is cleared when the OCD anomaly has not been detected for the period of time specified in ITU-T Recommendation I.432. MT90220 ICP ‘Stuff‘ - The ...
Page 115
... MT90220 LCD Remote Failure Indication (LCD-RFI) - The LCD-RFI is reported to the FE when a link defect is locally detected. The LCD-RFI defect is not always required on the link interface. Link Delay Synchronization (LDS) - The LDS is an event indicating that the link is synchronized with the other links within the IMA Group with respect to differential delay ...
Page 116
... Notes: MT90220 107 ...
Page 117
... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...