AT17LV256A ATMEL Corporation, AT17LV256A Datasheet

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AT17LV256A

Manufacturer Part Number
AT17LV256A
Description
Manufacturer
ATMEL Corporation
Datasheet

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Features
1. Description
The AT17A series FPGA configuration EEPROMs (Configurators) provide an easy-to-
use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17A series device is packaged in the 8-lead PDIP
TQFP, see
cedure to configure one or more FPGA devices. The user can select the polarity of the
reset function by programming four EEPROM bytes.These devices also support a
write-protection mechanism within its programming mode.
Note:
The AT17A series configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1.
Package
8-lead
PDIP
20-lead
PLCC
32-lead
TQFP
EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1- and
2,097,152 x 1-bit Serial Memories Designed to Store Configuration Programs for
Altera
Available as a 3.3V (±10%) and 5.0V (±5% Commercial, ±10% Industrial) Version
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX, APEX
Devices, ORCA
Motorola MPA1000 FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Very Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available 8-lead PDIP, 20-lead PLCC and 32-lead TQFP Packages (Pin Compatible
Across Product Family)
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Low-power Standby Mode
High-reliability
Green (Pb/Halide-free/RoHS Compliant) Package Options Available
– Endurance: 100,000 Write Cycles
– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for
Commercial Parts (at 70°C)
®
1. The 8-lead LAP, PDIP and SOIC packages for the AT17LV65A/128A/256A do not
FLEX
have an A label. However, the 8-lead packages are pin compatible with the 8-lead
package of Altera’s EEPROMs, refer to the AT17LV65/128/256/512/010/002/040
datasheet available on the Atmel web site for more information.
Table
®
AT17A Series Packages
and APEX
AT17LV128A/
AT17LV256A
AT17LV65A/
®
1-1. The AT17A series configurator uses a simple serial-access pro-
FPGAs, Xilinx
Yes
Yes
FPGAs (Device Selection Guide Included)
®
XC3000, XC4000, XC5200, Spartan
AT17LV512A
Yes
Yes
AT17LV010A
(1)
, 20-lead PLCC and 32-lead
Yes
Yes
Yes
®
, Virtex
AT17LV002A
Yes
Yes
FPGAs,
FPGA
Configuration
EEPROM
Memory
AT17LV65A
AT17LV128A
AT17LV256A
AT17LV512A
AT17LV010A
AT17LV002A
3.3V and 5V
System Support
2322G–CNFG–03/06

Related parts for AT17LV256A

AT17LV256A Summary of contents

Page 1

... Yes PLCC 32-lead – TQFP ® , Virtex (1) , 20-lead PLCC and 32-lead AT17LV512A AT17LV010A Yes Yes Yes Yes – Yes ™ FPGAs, FPGA Configuration EEPROM Memory AT17LV65A AT17LV128A AT17LV256A AT17LV512A AT17LV010A AT17LV002A 3.3V and 5V System Support AT17LV002A – Yes Yes 2322G–CNFG–03/06 ...

Page 2

Pin Configuration Figure 2-1. Figure 2-2. Figure 2-3. Notes: AT17LV65A/128A/256A/512A/002A 2 8-lead PDIP DATA DCLK (1) (WP ) RESET/OE nCS 20-lead PLCC DCLK 4 (2) WP1 (1) (WP ) RESET/OE 8 32-lead TQFP NC ...

Page 3

Figure 2-4. Block Diagram SER_EN (2) WP1 OSCILLATOR CONTROLL (3) OSCILLATOR POWER ON RESET DCLK READY Notes: 1. This pin is only available on AT17LV65A/128A/256A devices. 2. This pin is only available on AT17LV512A/010A/002A devices. 3. The nCASC feature is ...

Page 4

... DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset. This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document will describe RESET/OE. 4. Pin Description AT17LV65A/ AT17LV128A/ AT17LV256A 20 Name I/O PLCC DATA I/O ...

Page 5

DATA Three-state DATA output for configuration. Open-collector bi-directional pin for programming. 4.2 DCLK Clock output or clock input. Rising edges on DCLK increment the internal address counter and present the next bit of data to the DATA pin. The ...

Page 6

READY Open collector reset state indicator. Driven Low during power-on reset cycle, released when power-up is complete. (recommended 4.7 kΩ pull-up on this pin if used). 4.11 SER_EN Serial enable must be held High during FPGA loading operations. Bringing ...

Page 7

AT17A Series Reset Polarity The AT17A series configurator allows the user to program the polarity of the RESET/OE pin as either RESET/OE or RESET/OE. This feature is supported by industry-standard programmer algorithms. 9. Programming Mode The programming mode is ...

Page 8

... Supply Current, Standby Mode CCS1 AT17LV65A/128A/256A/512A/002A 8 AT17LV65A/ AT17LV128A/ AT17LV256A Min 2 -2.5 mA) 2.4 Commercial = +3 mA mA) 2.4 Industrial = +3 mA GND) - Commercial Industrial AT17LV65A/ AT17LV128A/ AT17LV256A Min 2 -2.5 mA) 3.7 Commercial = +3 mA mA) 3.6 Industrial = +3 mA GND) - Commercial Industrial AT17LV512A/ AT17LV010A AT17LV002A Max Min Max Min V 2 ...

Page 9

AC Waveforms nCS RESET/OE DCLK T CE DATA 16. AC Waveforms when Cascading RESET/OE nCS DCLK T CDF LAST BIT DATA T OCK nCASL 2322G–CNFG–03/06 AT17LV65A/128A/256A/512A/002A T SCE CAC T OCE T ...

Page 10

AC Characteristics V = 3.3V ± 10% CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC T Data Hold from CE, OE, or CLK ...

Page 11

AC Characteristics ± 5% Commercial ± 10% Industrial CC CC Symbol Description ( Data Delay OE ( Data Delay CE (1) T CLK to Data Delay CAC ...

Page 12

... Thin Plastic Quad Flat Package 32A (TQFP) 44J Plastic Leaded Chip Carrier (PLCC) Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site. 2. Airflow = 0 ft/min. AT17LV65A/128A/256A/512A/002A 12 (1) AT17LV65A/ AT17LV128A/ AT17LV256A θ [°C/W] JC θ (2) [°C/W] JA θ [°C/ θ ...

Page 13

Ordering Information (1) Figure 22-1. Ordering Code Voltage 3.3V Nominal to 5V Nominal Note: 1. The 8-lead LAP and SOIC packages for the AT17LV65A/128A/256A do not have an A label. However, the 8-lead packages are pin compatible with the ...

Page 14

... AT17LV002A devices use a 2-wire serial interface for in-system programming. 7. For operating voltage of 5V ±10%, please refer to the 5V ±10% AC and DC Characteristics. AT17LV65A/128A/256A/512A/002A 14 (1) Ordering Code AT17LV65A-10JC AT17LV65A-10JI AT17LV128A-10JC AT17LV128A-10JI AT17LV256A-10JC AT17LV256A-10JI AT17LV512A-10JC AT17LV512A-10PI AT17LV512A-10JI AT17LV010A-10JC AT17LV010A-10PI AT17LV010A-10JI AT17LV010A-10QI AT17LV002A-10JC AT17LV002A-10JI AT17LV002A-10QI Ordering Code ...

Page 15

Packaging Information 23.1 8P3 – PDIP Top View PLCS Side View Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L ...

Page 16

PLCC 1.14(0.045) X 45˚ B 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...

Page 17

TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 ...

Page 18

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2006. All rights reserved. Atmel and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations ...

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