ATF20V8B-25JC ATMEL Corporation, ATF20V8B-25JC Datasheet
ATF20V8B-25JC
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ATF20V8B-25JC Summary of contents
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... Supply Active TSSOP Top View CLK/ VCC GND 12 13 OE/IN DIP/SOIC PLCC Top View High- Performance EE PLD ATF20V8B Rev. 0407E–05/98 1 ...
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... Description The ATF20V8B is a high performance CMOS (Electrically Erasable) Programmable Logic Device (PLD) which utilizes Atmel’s proven electrically erasable Flash memory technol- ogy. Speeds down to 7.5 ns and power dissipation as low are offered. All speed ranges are specified over the full 5V ...
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DC Characteristics Symbol Parameter Condition Input or I/O Low Leakage Current Input or I/O High I 3.5 IH Leakage Current V Power Supply Current, Standby Outputs Open V Clocked Power Outputs Open, Supply Current ...
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... Enable — Product Term Input to Output t ER Disable —Product Term t OE pin to Output Enable PZX t OE pin to Output Disable PXZ Note: 1. See ordering information for valid part numbers and speed grades. ATF20V8B 4 -7 Min Max 8 outputs switching 3 7.5 1 output switching ...
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... Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. Power Up Reset The registers in the ATF20V8Bs are designed to reset dur- ing power up point delayed slightly from all registers will be reset to the low state result, RST the registered output state will always be high on power-up ...
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... ATF20V8B architecture. Eight configurable macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input. The ATF20V8B can be configured in one of three different modes. Each mode makes the ATF20V8B look like a dif- ferent device. Most PLD compilers can choose the right mode automatically. The user can also force the selection by supplying the compiler with a mode selection ...
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... P20V8 Tango-PLD G20V8 Note: 1. Only applicable for version 3.4 or lower. ATF20V8B Registered Mode PAL Device Emulation / PAL Replacement The registered mode is used if one or more registers are required. Each macrocell can be configured as either a reg- istered or combinatorial output or I/ input. For a registered output or I/O, the output is enabled by the OE pin, and the register is clocked by the CLK pin ...
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... Registered Mode Logic Diagram ATF20V8B 8 ...
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... Complex Mode Operation ATF20V8B Simple Mode PAL Device Emulation / PAL Replacement In the Simple Mode, 8 product terms are allocated to the sum term. Pins 15 and 16 (center macrocells) are perma- nently configured as combinatorial outputs ...
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... Complex Mode Logic Diagram ATF20V8B 10 ...
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Simple Mode Logic Diagram 11 ...
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... ATF20V8B 12 ...
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... ATF20V8B 14 ...
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... ATF20V8B-7SC ATF20V8B-7XC 7 ATF20V8B-10JC ATF20V8B-10PC ATF20V8B-10SC ATF20V8B-10XC ATF20V8B-10JI ATF20V8B-10PI ATF20V8B-10SI ATF20V8B-10XI ATF20V8B-15JC ATF20V8B-15PC ATF20V8B-15SC ATF20V8B-15XC ATF20V8B-15JI ATF20V8B-15PI ATF20V8B-15SI ATF20V8B-15XI ATF20V8B-25JC ATF20V8B-25PC ATF20V8B-25SC ATF20V8B-25XC ATF20V8B-25JI ATF20V8B-25PI ATF20V8B-25SI ATF20V8B-25XI Package Type Package Operation Range 28J Commercial 24P3 ( 24S 24X 28J Commercial 24P3 ...
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... Wide, Plastic Thin Shrink Small Outline (TSSOP) ATF20V8B 16 Ordering Code ATF20V8BQ-10JC ATF20V8BQ-10PC ATF20V8BQ-10XC ATF20V8BQL-15JC ATF20V8BQL-15PC ATF20V8BQL-15SC ATF20V8BQL-15XC ATF20V8BQL-25JC ATF20V8BQL-25PC ATF20V8BQL-25SC ATF20V8BQL-25XC ATF20V8BQL-25JI ATF20V8BQL-25PI ATF20V8BQL-25SI ATF20V8BQL-25XI Package Type Package Operation Range 28J Commercial 24P3 ( 24X 28J Commercial 24P3 ...
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Packaging Information 28J, 28-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AB .045(1.14) X 30° - 45° .045(1.14) X 45° PIN NO. 1 IDENTIFY .456(11.6) .450(11.4) .032(.813) .026(.660) .495(12.6) .485(12.3) .050(1.27) TYP .300(7.62) REF ...