CS51313GDR16 Cherry Semiconductor Corporation, CS51313GDR16 Datasheet

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CS51313GDR16

Manufacturer Part Number
CS51313GDR16
Description
Synchronous SPU buck controller capable of implementing multiple linear regulators
Manufacturer
Cherry Semiconductor Corporation
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS51313GDR16
Manufacturer:
ON/安森美
Quantity:
20 000
Rev. 3/11/99
The CS51313 is a synchronous dual
NFET Buck Regulator Controller. It is
designed to power the core logic of the
latest high performance CPUs. It uses the
V
fastest possible transient response and
best overall regulation. It incorporates
many additional features required to
ensure the proper operation and protec-
tion of the CPU and Power system. The
CS51313 provides the industry’s most
highly integrated solution, minimizing
external component count, total solution
size, and cost.
V
Pentium is a registered trademark of Intel Corporation.
Capable of Implementing Multiple Linear Regulators
2
2
TM
is a trademark of Switch Power, Inc.
control method to achieve the
51K
1%
VID2
VID4
VID1
VID3
OVP
VID0
100K
V
18K
1%
1µF
REF
+12
3
2
1%
+
-
+12V
GND
100K
V
LM358A
LM358A
1%
CC
1
Synchronous CPU Buck Controller
1200µF/10V
680pF
1µF
5
6
+
-
GATEH
GATEL
V
V
PWRGD
COMP
C
FB
OUT
OFF
IRL3103S
22.1K
Description
Application Diagram
1%
7
102K
1%
0.1
µF
0.01
+3.3V
µF
+3.3V
1200µF/10V
FS70VSJ-03
FS70VSJ-03
TIP 31
100Ω
0.1µF
10K
47µF
The CS51313 is specifically designed to
power Intel’s Pentium
includes the following features: 5-bit
DAC with 1.2% tolerance, Power-Good
output, overcurrent hiccup mode protec-
tion, over voltage protection, V
tor, Soft Start, adaptive voltage position-
ing and adaptive FET non-overlap time.
A precision reference trimmed to 1% is
also externally available for use by other
regulators. The CS51313 will operate
over an 8.4V to 14V range and is avail-
able in 16 lead narrow body surface
mount package.
1200µF/ 10V
+5V
x 2
1.2µH
510Ω
CS51313
1200µF/10V
x3
3.3mΩ
510Ω
1
1200µF/10V
®
II processor and
x5
PWRGD
1.5V@3A
VGTL+
V
2.0V@19A
VCLOCK
2.5V@1A
CORE
CC
moni-
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Synchronous Switching
Dual N-Channel MOSFET
V
200ns Transient Loop Response
5-bit DAC with 1.2% Tolerance
Hiccup Mode Overcurrent
40ns Gate Rise and Fall Times
65ns Adaptive FET Non-overlap
Adaptive Voltage Positioning
Power-Good Output Monitors
V
OVP Output Monitors Regulator
Enable Through use of the
+1.23V Reference Voltage
Cherry Semiconductor Corporation
Web Site: www.cherry-semi.com
2
CC
Regulator Controller for CPU
V
Synchronous Buck Design
Protection
(3.3nF load)
Time
Regulator Output
Voltage Lockout
Output
COMP pin
Available Externally
TM
Email: info@cherry-semi.com
Package Options
V
CORE
VID0
VID1
VID2
VID3
V
VID4
Monitor Provides Under
Control Topology
V
OUT
REF
16 Lead SO Narrow
FB
Features
1
A
COMP
C
PWRGD
OVP
GATE(L)
Gnd
GATE(H)
V
OFF
CC
®
Company

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CS51313GDR16 Summary of contents

Page 1

... Available Externally Package Options 16 Lead SO Narrow VID0 COMP 1 VID1 C OFF VID2 PWRGD VID3 OVP V GATE(L) REF Gnd VID4 V GATE( OUT CC Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com A Company ® ...

Page 2

Operating Junction Temperature, T Lead Temperature Soldering Reflow (SMD styles only ...

Page 3

Electrical Characteristics: 0˚C < T 2.0V DAC Code ( ID4 ID3 ID2 PARAMETER Error Amplifier V Bias Current 0.2V ≤V FB COMP Source Current V COMP Sink Current V Open Loop Gain C Unity Gain Bandwidth C ...

Page 4

Electrical Characteristics: 0˚C < T 2.0V DAC Code ( ID4 ID3 ID2 PARAMETER Line Regulation Input Threshold Input Pull-up Resistance Pull-up Voltage Bandgap Reference Voltage V REF GATE(H) and GATE(L) High Voltage at 100mA Low Voltage at ...

Page 5

Electrical Characteristics: 0˚C < T 2.0V DAC Code ( ID4 ID3 ID2 PARAMETER General Electrical Specifications V Monitor Start Threshold CC V Monitor Stop Threshold CC Hysteresis V Supply Current CC Note 1: All pins are rated ...

Page 6

Figure 1: Gate(H) and Gate(L) Falltime vs. Load Capacitance. 150 V = 12V 125 25°C A 100 2000 4000 6000 8000 Load Capacitance (pF) Figure 2: Gate(H) and Gate(L) Risetime vs. Load ...

Page 7

TM The V control method is illustrated in Figure 6. The out- put voltage is used to generate both the error signal and the ramp signal. Since the ramp signal is simply the output voltage affected by ...

Page 8

In this case, it will be 1. for Figure 7 the ratio of resistor R1 to resistor R2 is CLOCK ( where ...

Page 9

Duty Cycle = V 0.27V / 3.54V = 7% ≈ 5.2% Figure 10: Pulse-by-Pulse Regulation during Soft Start (2µs/div). Channel 1 - Regulator Output Voltage (0.2V/div) Channel 2 – Inductor Switching Node (5V/div) Channel (10V/div) CC Channel ...

Page 10

Slope Compensation 2 TM The V control method uses a ramp signal, generated by the ESR of the output capacitors, that is proportional to the ripple current through the inductor. To maintain regula tion, the V control loop ...

Page 11

The CPU V tolerance can be affected by any or all CC(CORE) of the following reasons: 1) buck regulator output voltage setpoint accuracy; 2) output voltage change due to discharging or charging of the bulk decoupling capacitors during a load ...

Page 12

The total change in output voltage as a result of a load cur- rent transient can be verified by the following formula: = ∆V + ∆V ∆V OUT ESR ESL Step 3: Selection of the Duty Cycle, Switching Frequency, Switch ...

Page 13

The designer must also verify that the inductor value yields reasonable inductor peak and valley currents (the inductor current is a triangular waveform L(PEAK) OUT where I = inductor peak current; L(PEAK load current; ...

Page 14

(dI/dt) MAX where L = input inductor value; IN ∆V = voltage seen by the input inductor during a full load swing; (dI/dt) = maximum allowable input current slew MAX rate (0.1A/µs for a Pentium® II ...

Page 15

I = maximum switching MOSFET RMS current; RMS( inductor peak current; L(PEAK inductor valley current; L(VALLEY Duty Cycle. Once the RMS current through the switch is known, the switching MOSFET conduction losses can ...

Page 16

P = upper MOSFET gate driver (IC) losses; GATE( total upper MOSFET gate charge; GATE( switching frequency upper MOSFET gate voltage. GATE(H) The lower (synchronous) MOSFET gate driver (IC) losses are: P ...

Page 17

V DAC(MIN DROOP(TYP) 1+R DROOP(TOLERANCE) ® Example: for a 450MHz Pentium II, the DC accuracy spec is 1.93 < V < 2.07V, and the AC accuracy spec is CC(CORE) 1.9V < V < 2.1V. The CS51313 DAC output ...

Page 18

For most PCBs the copper thickness 35µm (1.37 mils) for one ounce copper; ρ = 717.86µΩ-mil. For a CPU load of 16A the resistance needed to create a 50mV drop at full load is: 50mV 50mV R = ...

Page 19

Keep the inductor switching node small by placing the output inductor, switching and synchronous FETs close together. 7) The MOSFET gate traces to the IC must be as short, straight, and wide as possible. 8) Use fewer, but larger ...

Page 20

... PACKAGE DIMENSIONS IN mm (INCHES) Lead Count Metric Max 16L SO Narrow 10.00 1.27 (.050) 0.40 (.016) REF: JEDEC MS-012 Ordering Information Part Number Description CS51313GD16 16L SO Narrow CS51313GDR16 16L SO Narrow (tape & reel) Rev. 3/11/99 Package Specification D Thermal Data English R Min Max Min ΘJC 9.80 .394 .386 R Θ ...

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