W25P022AD-6 Winbond, W25P022AD-6 Datasheet
![no-image](/images/manufacturer_photos/0/7/712/winbond_sml.jpg)
W25P022AD-6
Specifications of W25P022AD-6
Available stocks
Related parts for W25P022AD-6
W25P022AD-6 Summary of contents
Page 1
GENERAL DESCRIPTION The W25P022A is a high-speed, low-power, synchronous-burst pipelined CMOS static RAM organized as 65,536 32 bits that operates on a single 3.3-volt power supply. A built-in two-bit burst address counter supports both Pentium executed is controlled by ...
Page 2
PIN CONFIGURATION NC I/O 17 I/O 18 VDDQ VSSQ I/O 19 I/O 20 I/O 21 I/O 22 VSSQ VDDQ I/O 23 I/O 24 /FT VDD NC VSS I/O 25 I/O 26 VDDQ VSSQ I/O 27 I/O 28 I/O 29 I/O ...
Page 3
PIN DESCRIPTION SYMBOL TYPE Input, Synchronous A0 A15 I/O, Synchronous I/O1 I/O32 CLK Input, Clock Input, Synchronous CE1 , CE2, CE3 Input, Synchronous GW Input, Synchronous BWE Input, Synchronous BW1 BW4 Input, Asynchronous OE Input, Synchronous ADV Input, Synchronous ADSC ...
Page 4
TRUTH TABLE ADDRESS CE1 CYCLE USED Unselected No Unselected No Unselected No Unselected No Unselected No Begin Read External Begin Read External Continue Read Next X Continue Read Next X Continue Read Next Continue Read Next Suspend Read Current X ...
Page 5
FUNCTIONAL DESCRIPTION The W25P022A is a synchronous-burst pipelined SRAM designed for use in high-end personal computers. It supports two burst address sequences for Intel be controlled by the LBO pin. The burst cycles are initiated by ADSP or ADSC and ...
Page 6
Write Table, continued READ/WRITE FUNCTION Write byte 4, byte 2 Write byte 4, byte 2, byte 1 Write byte 4, byte 3 Write byte 4, byte 3, byte 1 Write byte 4, byte 3, byte 2 Write all bytes I/O1 ...
Page 7
OPERATING CHARACTERISTICS / ( 3.15V to 3.6V 0V DDQ SS SSQ PARAMETER SYM. Input Low Voltage V IL Input High Voltage V IH Input Leakage Current I LI Output Leakage I LO Current ...
Page 8
AC TEST LOADS AND WAVEFORM ohm VL = 1.5V OUTPUT ohm AC TIMING CHARACTERISTICS ( 3.15V to 3.6V 0V DDQ SS SSQ PARAMETER Add. Setup Time Add. ...
Page 9
AC Timing Characteristics, continued PARAMETER Clock Cycle Time Clock High Pulsh Width Clock Low Pulse Width Clock to Output Valid Clock to Output High-Z Clock to Output Low-Z Clock to Output Invalid Output Enable to Output Valid Output Enable to ...
Page 10
TIMING WAVEFORMS Read Cycle Timing Single Read CLK T T ADSS ADSH ADSP ADSC T ADVS ADV A[15:0] RD1 BWE BW[4: CES CEH CE1 T T CES CEH CE2 ...
Page 11
Timing Waveforms, continued Write Cycle Timing Single Write CLK T T ADSS ADSH ADSP T ADCS ADSC T ADVS ADV ADV must be inactive for ADSP write A[15:0] WR1 BWE T ...
Page 12
Timing Waveforms, continued Read/Write Cycle Timing Single Read CLK T T ADSS ADSH ADSP T ADSC T T ADVS ADVH ADV A[15:0] RD1 BWE BW[4: ...
Page 13
Timing Waveforms, continued ZZ and RD Timing Single Read CLK T T ADSS ADSH ADSP ADSC T ADVS ADV A[15:0] RD1 BWE T WS BW[4: CES CEH CE1 T ...
Page 14
Timing Waveforms, continued Dual-bank Burst Read Cycle CLK Select Bank 0 ADSP ADSC ADV A[31:3] GW BWE BW[4:1] CE1 CE[3:2] Active Bank 0 CE[3:2] Non- Bank 1 Active OE D[63:0] Bank 0 D[63:0] Bank 1 DON'T CARE UNDEFINED Select Bank ...
Page 15
... PART NO. ACCESS TIME (nS) W25P022AF-6 6 W25P022AF-7 7 W25P022AD-6 6 W25P022AD-7 7 Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. ...
Page 16
PACKAGE DIMENSIONS 100-pin QFP See Detail F Seating Plane y 100-pin TQFP See Detail F Seating Plane ...
Page 17
... No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2730 Orchard Parkway, San Jose, CA 95134, U ...