MCM69F536CTQ10 Motorola, MCM69F536CTQ10 Datasheet

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MCM69F536CTQ10

Manufacturer Part Number
MCM69F536CTQ10
Description
32K x 36 bit flow-through burstRAM synchronous fast static RAM
Manufacturer
Motorola
Datasheet

Specifications of MCM69F536CTQ10

Dc
0007
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
32K x 36 Bit Flow–Through
BurstRAM Synchronous
Fast Static RAM
vide a burstable, high performance, secondary cache for the 68K Family,
PowerPC , 486, i960 , and Pentium microprocessors. It is organized as 32K
words of 36 bits each. This device integrates input registers, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced parts
count in cache data RAM applications. Synchronous design allows precise cycle
control with the use of an external clock (K). BiCMOS circuitry reduces the overall
power consumption of the integrated functions for greater reliability.
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through
positive–edge–triggered noninverting registers.
addresses can be generated internally by the MCM69F536C (burst sequence
operates in linear or interleaved mode dependent upon the state of LBO) and
controlled by the burst address advance (ADV) input pin.
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
synchronous write enable SW are provided to allow writes to either individual
bytes or to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa
controls DQa, SBb controls DQb, and so on. Individual bytes are written if the
selected byte writes SBx are asserted with SW. All bytes are written if either SGW
is asserted or if all SBx and SW are asserted.
from the memory array.
outputs are LVTTL compatible.
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
i960 and Pentium are trademarks of Intel Corp.
REV 3
2/18/98
MOTOROLA FAST SRAM
Motorola, Inc. 1998
The MCM69F536C is a 1M–bit synchronous fast static RAM designed to pro-
Addresses (SA), data inputs (DQx), and all control signals except output
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
Write cycles are internally self–timed and are initiated by the rising edge of the
Synchronous byte write (SBx), synchronous global write (SGW), and
For read cycles, a flow–through SRAM allows output data to simply flow freely
The MCM69F536C operates from a 3.3 V power supply and all inputs and
MCM69F536C–8.5 = 8.5 ns Access / 12 ns Cycle
MCM69F536C–9 = 9 ns Access / 12 ns Cycle
MCM69F536C–10 = 10 ns Access / 15 ns Cycle
MCM69F536C–12 = 12 ns Access / 16.6 ns Cycle
Single 3.3 V + 10%, – 5% Power Supply
ADSP, ADSC, and ADV Burst Control Pins
Selectable Burst Sequencing Order (Linear/Interleaved)
Internally Self–Timed Write Cycle
Byte Write and Global Write Control
5 V Tolerant on all Pins (Inputs and I/Os)
100–Pin TQFP Package
MCM69F536C
Order this document
CASE 983A–01
TQ PACKAGE
by MCM69F536C/D
MCM69F536C
TQFP
1

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MCM69F536CTQ10 Summary of contents

Page 1

... V Tolerant on all Pins (Inputs and I/Os) 100–Pin TQFP Package The PowerPC name is a trademark of IBM Corp., used under license therefrom. i960 and Pentium are trademarks of Intel Corp. REV 3 2/18/98 MOTOROLA FAST SRAM Motorola, Inc. 1998 Order this document by MCM69F536C/D MCM69F536C TQ PACKAGE TQFP CASE 983A–01 ...

Page 2

... SBc SBd SE1 SE2 SE3 G MCM69F536C 2 FUNCTIONAL BLOCK DIAGRAM BURST COUNTER K2 CLR 2 15 ADDRESS REGISTER WRITE REGISTER a WRITE REGISTER b WRITE REGISTER c WRITE REGISTER d K2 ENABLE REGISTER 2 15 32K x 36 ARRAY DATA–IN REGISTER K DQa – DQd MOTOROLA FAST SRAM ...

Page 3

... DQd DQd 22 DQd 23 DQd 24 DQd DQd 28 29 DQd DQd MOTOROLA FAST SRAM PIN ASSIGNMENT DQb 79 DQb ...

Page 4

... Other vendors’ RAMs may have implemented this Sleep Mode (ZZ) feature. NC — No Connection: There is no connection to the chip. Description MOTOROLA FAST SRAM ...

Page 5

... Address (External) 2nd Address (Internal X00 X01 X10 X11 WRITE TRUTH TABLE Cycle Type Read Read Write Byte a Write Byte b Write Byte c Write Byte d Write All Bytes Write All Bytes MOTOROLA FAST SRAM SE2 SE3 ADSP ADSC ...

Page 6

... Symbol Max Unit Notes MOTOROLA FAST SRAM ...

Page 7

... Data states are all zero. 4. Device in deselected mode as defined by the Truth Table. CAPACITANCE (f = 1.0 MHz 3 Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Input/Output Capacitance MOTOROLA FAST SRAM (Voltages Referenced Symbol V DD 3.135 V IL – 0. ...

Page 8

... Max Min Max Unit Notes — 16.6 — ns — 6 — ns — 6 — — — — 0 — — 3 — — 0 — — — 2.5 — ns — 0.5 — ns MOTOROLA FAST SRAM ...

Page 9

... MOTOROLA FAST SRAM MCM69F536C 9 ...

Page 10

... ADSP Sync Non–Burst, Flow–Through SRAM NOTE: Although X is specified in the table as a don’t care, the pin must be tied either high or low Q(C) Q(D) D( ADSC ADV SE1 SE2 LBO D(F) D(G) D(H) WRITES MOTOROLA FAST SRAM ...

Page 11

... Part Number Full Part Numbers — MCM69F536CTQ8.5 MCM69F536CTQ8.5R MCM69F536CTQ9R MCM69F536CTQ10R MCM69F536CTQ12R Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

Page 12

... VIEW AB How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1-602-244-6609 Motorola Fax Back System – US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 – http://sps.motorola.com /mfax / HOME PAGE : http://motorola ...

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