SCC2692AE1B44 Philips Semiconductors, SCC2692AE1B44 Datasheet
SCC2692AE1B44
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SCC2692 Dual asynchronous receiver/transmitter (DUART) Product specification Supersedes data of 1998 Feb 19 IC19 Data Handbook Philips Semiconductors INTEGRATED CIRCUITS 1998 Sep 04 ...
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... Commercial and industrial temperature range versions TTL compatible Single +5V power supply COMMERCIAL INDUSTRIAL V = +5V +10 +5V +10 + - SCC2692AC1N40 SCC2692AE1N40 SCC2692AC1N28 SCC2692AE1N28 SCC2692AC1A44 SCC2692AE1A44 SCC2692AC1B44 SCC2692AE1B44 2 Product specification SCC2692 DWG # SOT129-1 SOT117-1 SOT187-2 SOT307–2 853–0895 19971 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART IP3 2 39 IP4 IP5 A0 1 IP1 4 37 IP6 IP2 CEN A3 4 IP0 7 34 RESET WRN 5 WRN RDN 6 RDN 9 32 X1/CLK RxDB 7 RxDB 10 31 RxDA DIP TxDB 8 TxDB ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) BLOCK DIAGRAM 8 D0–D7 BUS BUFFER OPERATION CONTROL RDN WRN ADDRESS DECODE CEN 4 A0–A3 R/W CONTROL RESET INTERRUPT CONTROL INTRN IMR ISR TIMING BAUD RATE GENERATOR CLOCK SELECTORS COUNTER/ TIMER X1/CLK XTAL OSC X2 CSRA CSRB ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) PIN DESCRIPTION APPLICABLE SYMBOL TYPE SYMBOL TYPE 40,44 28 D0- I/O Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the DUART and the CPU the least significant bit. CEN Chip Enable: Active-Low input signal. When Low, data transfers between the CPU and the DUART are enabled on D0-D7 as controlled by the WRN, RDN and A0-A3 inputs ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) DC ELECTRICAL CHARACTERISTICS SYM- PARAMETER PARAMETER BOL V Input low voltage IL V Input high voltage (except X1/CLK Input high voltage (except X1/CLK Input high voltage (X1/CLK Output low voltage OL V Output high voltage (except OD outputs) ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) AC CHARACTERISTICS (Continued) SYMBOL SYMBOL 5 Port Timing (See Figure 5) Port input setup time before RDN Low Port input hold time after RDN High output valid from WRN High PD n Interrupt Timing (See Figure 6) INTRN (or OP3-OP7 when used as interrupts) negated from: ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) BLOCK DIAGRAM The SCC2692 DUART consists of the following eight major sections: data bus buffer, operation control, interrupt control, timing, communications Channels A and B, input port and output port. Refer to the Block Diagram. Data Bus Buffer The data bus buffer provides the interface between the external and internal data buses ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) conditions of the UART. When this 8-bit port is used as a general purpose output, the pins so defined will assume the compliment of the associated bit in the Output Port Register (OPR). OPR( results in OP(n) = Low and vice versa. Bits of the OPR can be individually set and reset. A bit is set by performing a write operation at address H’ ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) mode reading the SR does not affect the FIFO. The FIFO is ‘popped’ only when the RHR is read. Therefore the status register should be read prior to reading the FIFO. If the FIFO is full when a new character is received, that character is held in the receive shift register until a FIFO position is available ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) Table 1. SCC2692 Register Addressing ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) Table 2. Register Bit Formats (Continued) BIT 7 BIT 6 RECEIVED FRAMING SRA BREAK* ERROR* SRB SRB Yes 1 = Yes NOTE: *These status bits are appended to the corresponding data character in the receive FIFO. A read of the status provides these bits (7:5) from the top of the FIFO together with bits (4:0). These bits are cleared by a “ ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) PROGRAMMING The operation of the DUART is programmed by writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU. The addressing of the registers is described in Table 1. The contents of certain control registers are initialized to zero on RESET ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) 1. Received data is re-clocked and retransmitted on the TxDA out- put. 2. The receive clock is used for the transmitter. 3. Received data is not sent to the local CPU, and the error status conditions are inactive. 4. The received parity is not checked and is not regenerated for transmission, i ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) MR1B – Channel B Mode Register 1 MR1B is accessed when the Channel B MR pointer points to MR1. The pointer is set to MR1 by RESET ‘set pointer’ command applied via CRB. After reading or writing MR1B, the pointer will point to MR2B ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) 1110 Power Down Mode On. In this mode, the DUART oscillator is stopped and all functions requiring this clock are suspended. The execution of commands other than disable power down mode (1111) requires a X1/CLK. While in the power down mode, do not issue any commands to the CR except the disable power down mode command ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) OPCR – Output Port Configuration Register OPCR[7] – OP7 Output Select This bit programs the OP7 output to provide one of the following: 0 The complement of OPR[7]. 1 The Channel B transmitter interrupt output which is the complement of TxRDYB. When in this mode OP7 acts as an open- drain output ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) Table 5. ACR 6:4 Field Definition ACR MODE CLOCK SOURCE 6:4 000 Counter External (IP2) TxCA – 1X clock of Channel A 001 Counter transmitter TxCB – 1X clock of Channel B 010 Counter transmitter Crystal or external (X1/CLK) 011 Counter divided by 16 100 Timer (square wave) ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) data clock. The formula for calculating the divisor n to load to the CTUR and CTLR for a particular 1X data clock is shown below: counter clock frequency baud rate desired Often this division will result in a non-integer number; 26.3, for example ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) A0– CEN t CS RDN D0–D7 FLOAT (READ WDN D0–D7 (WRITE) RDN IP0–IP6 (a) INPUT PINS WRN OP0–OP7 (b) OUTPUT PINS 1998 Sep RWD NOT VALID FLOAT VALID ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) WRN INTERRUPT OUTPUT RDN INTERRUPT OUTPUT NOTES: 1. INTRN or OP3-OP7 when used as interrupt outputs. 2. The test for open-drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching signal point 0.5V above V ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) TxC (INPUT) TxD TxC (1X OUTPUT) RxC (1X INPUT) RxD TxD D1 TRANSMITTER ENABLED TxRDY (SR2) WRN CTSN (IP0) 2 RTSN (OP0) OPR( NOTES: 1. Timing shown for MR2( Timing shown for MR2( 1998 Sep 04 1 BIT TIME ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) D1 RxD RECEIVER ENABLED RxRDY (SR0) FFULL (SR1) RxRDY/ FFULL 2 (OP5) RDN STATUS DATA D1 OVERRUN (SR4) 1 RTS (OP0) OPR( NOTES: 1. Timing shown for MR1( Shown for OPCR( and MR( MASTER STATION ADD#1 TxD TRANSMITTER ENABLED TxRDY ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) 2.7K INTRN 50pF D0–D7 TxDA/B OP0–OP7 150pF Figure 13. Test Conditions on Outputs Output Port Notes The output ports are controlled from four places: the OPCR register, the OPR register, the MR registers and the command register. The OPCR register controls the source of the data for the output ports OP2 through OP7 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) A condition that occurs infrequently has been observed where the receiver will ignore all data caused by a corruption of the start bit generally due to noise. When this occurs the receiver will appear to be asleep or locked up. The receiver must be reset for the UART to continue to function properly ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) DIP40: plastic dual in-line package; 40 leads (600 mil) 1998 Sep 04 26 Product specification SCC2692 SOT129-1 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) DIP28: plastic dual in-line package; 28 leads (600 mil) 1998 Sep 04 27 Product specification SCC2692 SOT117-1 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) PLCC44: plastic leaded chip carrier; 44 leads 1998 Sep 04 28 Product specification SCC2692 SOT187-2 ...
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... Philips Semiconductors Dual asynchronous receiver/transmitter (DUART) QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 1.75 mm 1998 Sep 04 29 Product specification SCC2692 SOT307-2 ...
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... Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no ...