DSP56001FE27 Motorola, DSP56001FE27 Datasheet
DSP56001FE27
Available stocks
Related parts for DSP56001FE27
DSP56001FE27 Summary of contents
Page 1
... SEMICONDUCTOR TECHNICAL DATA 24-Bit General Purpose Digital Signal Processor The DSP56001 is a member of Motorola’s family of HCMOS, low-power, general purpose Digital Signal Processors. The DSP56001 features 512 words of full speed, on-chip program RAM (PRAM) memory, two 256 word data RAMs, two preprogrammed data ...
Page 2
... XTAL In the USA: For technical assistance call: DSP Applications Helpline (512) 891-3230 For availability and literature call your local Motorola Sales Office or Authorized Motorola Distributor. For free application software and information call the Dr. BuB electronic bulletin board: 9600/4800/2400/1200/300 baud (512) 891-3771 ...
Page 3
... Port A address and control pins, one power and two ground for Port A data pins, and one pair for peripherals. Refer to the pin as- signments in the LAYOUT PRACTICES section. INTERRUPT AND MODE CONTROL POWER AND CLOCK MOTOROLA 3 ...
Page 4
... Input data is sampled on the positive edge of the Receive Clock. RXD may be programmed as a general purpose I/O pin called PC0 when the SCI is not being used. This pin is configured as a GPIO input pins during hardware reset. MOTOROLA 4 Transmit Data (TXD) This output transmits serial data from the SCI Transmit Shift Register. ...
Page 5
... Gnd or Vcc). DSP56001 Electrical Specifications Symbol Vcc Vin Tstg Maximum Electrical Ratings Symbol JA JC Symbol JA JC Symbol JA JC Value Unit -0 0.5 to Vcc + 0 -40 to +105 C -55 to +150 C Value Rating 27 C/W 6.5 C/W Value Rating 40 C/W 7.0 C/W Value Rating 38 C/W 13.0 C/W MOTOROLA 5 ...
Page 6
... Values for thermal resistance presented in this document, unless estimated, were derived using the procedure described in Motorola Reliability Report 7843, “Thermal Resistance Measurement Method for MC68XX Microcomponent Devices”, and are provided for design purposes only. Thermal measurements are complex and dependent on procedure and setup ...
Page 7
... DSP56001 Host Port may not correctly update the port status information which can result in ih min storing two or more copies of a single down loaded data word. Of course full logic transition occurs, the part will complete a normal data transfer operation. DSP56001 . Should this occur without completing il max MOTOROLA 7 ...
Page 8
... WAIT Mode (see Note 1) in STOP Mode (see Note 1) Input Capacitance Notes order to obtain these results all inputs must be terminated (i.e., not allowed to float). 2. Periodically sampled and not 100% tested. MOTOROLA 8 = -40 to +105° 20.5 MHz and 27 MHz -40 to +105° MHz) J ...
Page 9
... T = Icyc / 4 is used in the electrical characteristics. T represents an average which is independent of the duty cycle. DSP56001 maximum of 0.5 V and 20.5 MHz 27 MHz Min Max Min Max 4.0 20.5 4.0 27.0 22 150 17 150 22 150 17 150 48.75 250 37 250 97.5 500 74 500 minimum of 2.4 V for IH and OL 33 MHz Unit Min Max 4.0 33.0 MHz 13.5 150 ns 13.5 150 ns 30.33 250 ns 60 500 ns MOTOROLA 9 ...
Page 10
... Notes: (1) The suggested crystal source is ICM, # 433163 - 4.00 (4MHz fundamental load 436163 - 30.00 (30 MHz fun- damental load). Clock Figure 1. Crystal Oscillator Circuits EXTAL V ILC 1 Note: The midpoint is V Clock Figure 2. External Clock Timing MOTOROLA 10 EXTAL EXTAL • • C1 • • ...
Page 11
... Control Figure 1. Reset Timing 33 MHz Unit Max Min Max 38 — — 75000*cyc — ns — 25 cyc — 8*cyc 9*cyc+25 ns cyc-8 13 cyc-7 ns 8*cyc+5 8*cyc+19 ns — 62 — — 16 — ns — 10 — IHR 11 First Fetch MOTOROLA 11 ...
Page 12
... Delay from WR Assertion to WS=0 Interrupt Request Deassertion for WS>0 Level Sensitive Fast Interrupts 22 Delay from General-Purpose Output Valid to Interrupt Request Deassertion for Level Sensitive Fast Interrupts - If Second Interrupt Instruction is: Single Cycle Two Cycle MOTOROLA 12 (Continued) NOTE 20.5 MHz 27 MHz Min Max Min 5 cyc+tch — ...
Page 13
... MHz Unit Max Min Max 16 cyc-7 ns cyc+ 13 cyc+ 13 cyc tch+5 tch+19 — 16 — ns — 65545 cyc — — 17 cyc — — 65533 cyc — +tcl — 5 cyc+tcl — — 65545 cyc — — 17 cyc — MOTOROLA 13 ...
Page 14
... DSP56001 Electrical Characteristics EXTAL RESET A0-A15, DS, PS X/Y RESET MODA, MODB Control Figure 3. Operating Mode Select Timing IRQA, IRQB Control Figure 4. External Interrupt Timing (Negative Edge-Triggered) MOTOROLA Control Figure 2. Synchronous Reset Timing 14 V IHM V ILM 16 V IHR IRQA, IRQB ...
Page 15
... DSP56001 Electrical Characteristics A0-A15 RD WR IRQA IRQB General Purpose I/O IRQA IRQB Control Figure 5. External Level-Sensitive Fast Interrupt Timing DSP56001 First Interrupt Instruction Execution First Interrupt Instruction Execution General Purpose I/O MOTOROLA 15 ...
Page 16
... PS, X/Y Control Figure 6. Synchronous Interrupt and Synchronous Wait State Timing IRQA A0-A15, DS, PS, X/Y Control Figure 7. Recovery from Stop State Using IRQA IRQA A0-A15, DS, PS, X/Y Control Figure 8. Recovery from Stop State Using IRQA Interrupt Service MOTOROLA 16 T0 First Instruction Fetch ...
Page 17
... A potential problem exists when reading status bits HF1 and HF2 as an encoded pair, i.e., the four combinations 00, 01, 10, and 11 each have significance. A very small probability exists that the DSP will read the status bits synchronized during transition. The solution to this potential problem is to read the bits twice for consensus. DSP56001 MOTOROLA 17 ...
Page 18
... Assertion 42 HR/W High Hold Time After HEN/ HACK Deassertion 43 HA0-HA2 Setup Time Before HEN Assertion 44 HA0-HA2 Hold Time After HEN Deassertion 45 DMA HACK Assertion to HREQ Deassertion (see Note 3) MOTOROLA 18 20.5 MHz 27 MHz Min Max Min Max tcl cyc+tcl tcl cyc+tcl cyc+60 — cyc+46 50 — ...
Page 19
... Host Figure 1. Host Synchronization Delay 33 MHz Unit Max Min Max — tHSDL+cyc — ns +tch+4 — tHSDL+cyc+4 — ns — 4 — ns — tHSDL+cyc — ns +tch+4 — tHSDL+cyc+4 — MOTOROLA 19 ...
Page 20
... DSP56001 Electrical Characteristics HREQ (OUTPUT) HACK (INPUT) HR/W (INPUT) H0-H7 (OUTPUT) Host Figure 2. Host Interrupt Vector Register (IVR) Read MOTOROLA Data Valid DSP56001 ...
Page 21
... HEN (INPUT) HA2-HA0 (INPUT) HR/W (INPUT H0-H7 (OUTPUT) Host Figure 3. Host Read Cycle (Non-DMA Mode) DSP56001 32A RXH RXM Read Read Address Address Valid Valid Data Data Valid Valid 49 47 RXL Read Address Valid Data Valid MOTOROLA 21 ...
Page 22
... Address HA2-HA0 Valid (INPUT) 39 HR/W (INPUT) 33 H0-H7 (INPUT) Host Figure 4. Host Write Cycle (Non-DMA Mode) HREQ (OUTPUT) 45 HACK RXH (INPUT) Read 36 35 H0-H7 (OUTPUT) MOTOROLA 22 TXM Write 32 44 Address Valid 40 34 Data Data Valid Valid RXM Read 37 38 Data Data Valid Valid Host Figure 5 ...
Page 23
... DSP56001 Electrical Characteristics HREQ (OUTPUT HACK TXH (INPUT) Write 33 H0-H7 (INPUT) DSP56001 46 32 TXM Write 34 Data Data Valid Valid Host Figure 6. Host DMA Write Cycle 46 46 TXL Write Data Valid MOTOROLA 23 ...
Page 24
... Output Data Hold After Clock Rising Edge (External Clock) 65 Input Data Setup Time Before Clock Rising Edge (External Clock) 66 Input Data Hold Time After Clock Ris- ing Edge (External Clock) MOTOROLA 24 SCI Synchronous Mode Timing 20.5 MHz 27 MHz Min Max Min 8 cyc — ...
Page 25
... MHz Unit Max Min Max — 64 cyc — — 32 cyc-13 — — 32 cyc-13 — — 32 cyc — -61 — 32 cyc — -61 MOTOROLA 25 ...
Page 26
... DSP56001 Electrical Characteristics INTERNAL CLOCK SCLK (OUTPUT) 59 TXD RXD EXTERNAL CLOCK SCLK (INPUT) TXD RXD MOTOROLA DATA VALID 61 DATA VALID DATA VALID 65 DATA VALID SCI Figure 1. SCI Synchronous Mode Timing DSP56001 ...
Page 27
... DSP56001 Electrical Characteristics 1X SCK (OUTPUT) TXD Note: In the wire-OR mode, TXD can be pulled SCI Figure 2. SCI Asynchronous Mode Timing DSP56001 DATA VALID 70 MOTOROLA 27 ...
Page 28
... Synchronous Mode) Falling Edge 89 Data In Hold Time After RXC Falling Edge 90 FSR Input (bl) High Before RXC Falling Edge 91 FSR Input (wl) High Before RXC Falling Edge 92 FSR Input Hold Time After RXC Falling Edge MOTOROLA 28 20.5 MHz 27 MHz Min Max Min 4 cyc — 4 cyc * ...
Page 29
... MOTOROLA 29 ...
Page 30
... DSP56001 Electrical Characteristics 83 RXC (Input/Output) FSR (Bit) OUT FSR (Word) OUT DATA IN FSR (Bit) IN FSR (Word) IN FLAGS IN MOTOROLA First SSI Figure 1. SSI Receiver Timing 87 89 Bit Last Bit 92 94 DSP56001 ...
Page 31
... In the Network mode, output flag transitions can occur at the start of each time slot within the frame. In the Normal mode, the output flag state is asserted for the entire frame period. DSP56001 100 100 99 First Bit 105 103 104 106 SSI Figure 2. SSI Transmitter Timing 98 101 101a Last Bit 105 (See Note 1) MOTOROLA 31 ...
Page 32
... Data Out Hold Time from WR Deassertion (The maximum specifica- tion is periodically sampled, and not 100% tested.) 125 Data Out Setup Time to WR Deassertion (see Note 6) 126 RD Deassertion to Address Not Valid MOTOROLA 32 AC Electrical Characteristics — 20.5 MHz Min Max Min 2 cyc+tch 4*cyc+tch+ ...
Page 33
... MOTOROLA Unit ...
Page 34
... A0-A15, DS, PS, X/Y (See Note 1) RD 120 135 WR 123 D0-D23 Note: 1. During Read-Modify-Write instructions and internal instructions, the address lines do not change state. Async. Bus Figure 2. External Bus Asynchronous Timing MOTOROLA 34 115 116 117 119 118 127 131 129 122 121 133 ...
Page 35
... MHz Unit Min Max — tch+ 4.5 10.5 ns — 3.5 — — — — ns MOTOROLA 35 ...
Page 36
... DSP56001 Electrical Characteristics T0 CLK in A0-A15 DS,PS X/Y 140 RD 141 WR D0-D23 Sync. Bus Figure 1. DSP56001 Synchronous Bus Timing Note: During Read-Modify-Write Instructions, the address lines do not change states. MOTOROLA 143 142 Data Out 145 149 144 147 148 Data In 146 ...
Page 37
... MHz Max Min Max 19 2.5 19 — 2.5 — cyc-6 12 cyc-5 — 5 — 6.5 cyc-11 0 cyc-10 2*cyc-11 cyc+4 2*cyc-10 WS*cyc (WS-1) WS*cyc -11 cyc+4 - cyc+tcl cyc+tcl 2 cyc+tcl * * +17 +15 — tch-4.5 — tch-6.5 — 10 — MOTOROLA Unit ...
Page 38
... WT 143 RD D0-D23 141 WR D0-D23 Bus Arbitration Figure 1. DSP56001 Synchronous Timings Note: During Read-Modify-Write Instructions, the address lines do not change state. However, BS will deassert before asserting again for the write cycle. MOTOROLA 152 153 147 145 Data Out ...
Page 39
... Bus Arbitration Figure 2. DSP56001 Asynchronous Timings Note: During Read-Modify-Write Instructions, the address lines will not change states. However, BS will deassert before asserting again for the write cycle. DSP56001 157 123 125 Data Out 160 159 158 126 128 161 Data In 122 124 MOTOROLA 39 ...
Page 40
... DSP56001 Electrical Characteristics MOTOROLA 40 DSP56001 ...
Page 41
... ZIF Production ZIF Burn-In and Test 3 3 High Temp, Longer Leads 1 Includes Cutout in Center 1 No Cutout Comment Converts CQFP to fit AMP’s 132 position PQFP “Micro-Pitch Socket”. Comment Housing Sub-Assembly and Cover for 132 position PQFP “Micro-Pitch Socket”. MOTOROLA A-41 ...
Page 42
... MIN MAX MIN A 34.04 35.05 1.340 B 34.04 35.05 1.340 C 2.16 3.04 0.085 D 0.44 0.55 0.017 G 2.54 BSC 0.100 BSC K 4.20 5.08 0.165 Mechanical Specification Figure A-1. Pin Grid Array Mechanical Specification MOTOROLA A-42 PIN ASSIGNMENT A14 A13 A12 A10 A15 A11 GND VCC GND D5 D7 GND BOTTOM VIEW VCC D12 ...
Page 43
... NO CONNECT 40 SC1 39 STD 38 NO CONNECT 37 SC2 36 INTERNAL LOGIC VCC 35 INTERNAL LOGIC VCC 34 INTERNAL LOGIC GND 33 INTERNAL LOGIC GND 32 SCK 31 SC0 30 NO CONNECT 29 SCLK 28 TXD 27 RXD 26 NO CONNECT PERIPHERAL GND 23 PERIPHERAL GND CONNECT CONNECT MOTOROLA A-43 ...
Page 44
... Mechanical Specification Figure A-2. Ceramic Quad Flat Pack MOTOROLA A-44 DSP56001 ...
Page 45
... Mechanical Specification Figure A-2. Ceramic Quad Flat Pack (Continued) DSP56001 MOTOROLA A-45 ...
Page 46
... Mechanical Specification Figure A-3. Plastic Quad Flat Pack MOTOROLA A-46 DSP56001 ...
Page 47
... Mechanical Specification Figure A-3. Plastic Quad Flat Pack (Continued) DSP56001 MOTOROLA A-47 ...
Page 48
... RESET FUNCTION FROM OPEN COLLECTOR BUFFER Figure B-2. Port A Bootstrap with External Data RAM — Mode 1 MOTOROLA B-48 APPENDIX B APPLICATION EXAMPLES A system with external data RAM memory requires no glue logic to select the external EPROM from bootstrap mode used to enable the EPROM and DS is used to enable the high speed data memories as shown in Figure B-2 ...
Page 49
... A0-A14 * MBD301 RESET HACK * MBD301 BR MODB/IRQB D0-D23 F32 F32 ADDRESS DECODE +5 V LS09 F32 F32 8 3 Note *: These diodes must be Schottky diodes. 15 +5V A0-A14 15 2756-30 (3) +5V D0-D23 15 24 Note *: These diodes must be Schottky diodes. MOTOROLA LDS AS A4-A23 MC68000 (12.5MHz) 1K DTACK R/W D0-D7 A1- B-49 ...
Page 50
... LOGIC RESET Figure B-6. Reset Circuit Using MC34064/MC33064 MOTOROLA B-50 before initiating a 3.75 ms minimum (150,000T) oscillator stabili- resis- zation delay required for the on-chip oscillator (only 50T is re- quired for an external oscillator). This insures that the DSP is op- erational and stable before releasing the reset signal. ...
Page 51
... Figure B-7. 27 MHz DSP56001 with 20 ns SRAM DSP56001 into the ranges X:$1000-1FFF and Y:$1000-1FFF. The PLD < 10 ns, equation is: DW RAM_ENABLE = PS & !DS & !A15 & !A14 & !A13 & !A12 RAM_ENABLE 12 MCM6264D ( DATA ADDRESS MOTOROLA B-51 ...
Page 52
... D03 A06 D02 A07 D01 A08 D00 A09 A00 A31 A01 A30 A02 A29 Figure B-8. DSP56001-to-ISA Bus Interface Schematic MOTOROLA B-52 DSP56001” which is provided on request by the Motorola DSP Marketing Department (512-891-2030). +5v 1 L13 B10 3 13 HREQ A9 4 HACK 5 A10 ...
Page 53
... DC $00B400 ; 45 DC $00A400 ; 41 DC $009400 ; 37 DC $008400 ; 33 DC $007800 ; 30 DC $007000 ; 28 DC $006800 ; 26 DC $006000 ; 24 DC $005800 ; 22 DC $005000 ; 20 DC $004800 ; 18 DC $004000 ; 16 DC $003800 ; 14 DC $003000 ; 12 DC $002800 ; 10 DC $002000 ; 8 DC $001800 ; 6 DC $001000 ; 4 DC $000800 ; 2 DC $000000 ; 0 MOTOROLA C-53 ...
Page 54
... A_B8 DC $3B0000 A_B9 DC $390000 A_BA DC $3F0000 A_BB DC $3D0000 A_BC DC $330000 A_BD DC $310000 A_BE DC $370000 A_BF DC $350000 Figure C-1. Mu-Law/A-Law Expansion Table Contents (Sheet MOTOROLA C-54 ; 688 A_C0 ; 656 A_C1 ; 752 A_C2 ; 720 A_C3 ; 560 A_C4 ; 528 A_C5 ; 624 A_C6 ; 592 A_C7 ...
Page 55
... MOTOROLA D-55 ...
Page 56
... S_AF DC $8AFB2D ; -0.9142097235 S_B0 DC $89BE51 ; -0.9238795042 S_B1 DC $8893B1 ; -0.9329928160 S_B2 DC $877B7C ; -0.9415441155 S_B3 DC $8675DC ; -0.9495282173 Figure D-1. Sine Wave Table Contents (Sheet MOTOROLA D-56 S_B4 DC $8582FB ; -0.9569402933 S_B5 DC $84A2FC ; -0.9637761116 S_B6 DC $83D604 ; -0.9700313210 S_B7 DC $831C31 ; -0.9757022262 S_B8 DC $8275A1 ; -0.9807853103 S_B9 ...
Page 57
... S_F6 DC $E0E607 ; -0.2429800928 S_F7 DC $E3F47E ; -0.2191012055 S_F8 DC $E70748 ; -0.1950902939 S_F9 DC $EA1DEC ; -0.1709619015 S_FA DC $ED37F0 ; -0.1467303932 Figure D-1. Sine Wave Table Contents (Sheet DSP56001 S_FB DC $F054D9 ; -0.1224106997 S_FC DC $F3742D ; -0.0980170965 S_FD DC $F69570 ; -0.0735644996 S_FE DC $F9B827 ; -0.0490676016 S_FF DC $FCDBD5 ; -0.0245412998 MOTOROLA D-57 ...
Page 58
... DSP56001 PRAM. The program is written in DSP56000/DSP56001 assembly language. It contains two separate methods of initializing the PRAM: loading from a byte-wide memory starting at location P:$C000 or loading MOTOROLA E-58 APPENDIX E through the Host Interface. The particular method used is select the level of program memory location $C000, bit 23. If lo- cation P:$C000, bit 23 is read as a one, the external bus version of the bootstrap program will be selected ...
Page 59
... INCREMENT R0 POINTER. FINISHED 512 LOOPS? Y SET OPERATING MODE TO REGISTER MODE 2 ENABLE HOST INTERFACE LOGIC IS N HOST FLAG 0 =0? Y ENDDO STOP BOOT LOAD IS THE HOST RECEIVE FLAG = 0? DATA AVAILABLE N PUT DATA FROM HOST RECEIVE DATA REGISTER INTO ACCUMULATOR A1 CLEAR STATUS JUMP TO P:0 MOTOROLA E-59 ...
Page 60
... Motorola DSP56000 Macro Cross Assembler Version 2.00 87-08-23 09:57:46 bootcode.asm Page BOOTSTRAP SOURCE CODE FOR DSP56001 - (C) Copyright 1986 Motorola Inc Host algorithm / AND / external bus method 6 ; This is the Bootstrap source code contained in the DSP56001 32 word boot ROM This program can load the internal program memory from one of two external sources. ...
Page 61
... Motorola DSP56000 Macro Cross Assembler Version 2.00 87-08-23 09:57:46 bootcode.asm Page bootstrap operating mode, make certain that the L bit is cleared and registers and M1have been set to $FFFF. Also, make sure the BCR is set to $xxFx since 37 ; EPROMS are slow and BCR is set to $FFFF after a reset. If the L bit was set before 38 ...
Page 62
... Motorola DSP56000 Macro Cross Assembler Version 2.00 87-08-23 09:57:46 bootcode.asm Page 3 69 P:000E 07D98A 70 71 P:000F 0608A0 72 P:0010 200022 73 _LOOP2 74 P:0011 0C001B This is the second routine. It loads from the Host Interface pins P:0012 0AA020 _HOSTLD 79 P:0013 0AA983 _LBLA 000017 80 P:0015 00008C 81 P:0016 ...
Page 63
... DSP56001 MOTOROLA E-63 ...
Page 64
... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...