KM48V2100BK-6 Samsung, KM48V2100BK-6 Datasheet

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KM48V2100BK-6

Manufacturer Part Number
KM48V2100BK-6
Description
2M x 8bit CMOS dynamic RAM with fast page mode, 3.3V, 60ns
Manufacturer
Samsung
Datasheet

Specifications of KM48V2100BK-6

Case
SOJ

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Part Number:
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KM48C2000B, KM48C2100B
KM48V2000B, KM48V2100B
This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-5,-6 or -7), power con-
sumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-
before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version.
This 2Mx8 Fast Page Mode DRAM family is fabricated using Samsung's advanced CMOS process to realize high band-width, low power
consumption and high reliability.
It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
FEATURES
¡Ü
¡Ü
¡Ü
¡Ü
Speed
Active Power Dissipation
Refresh Cycles
Performance Range
Part Identification
C2000B
V2000B
C2100B
V2100B
Speed
- KM48C2000B/B-L (5V, 4K Ref.)
- KM48C2100B/B-L (5V, 2K Ref.)
- KM48V2000B/B-L (3.3V, 4K Ref.)
- KM48V2100B/B-L (3.3V, 2K Ref.)
-5
-6
-7
Part
NO.
-5
-6
-7
50ns
60ns
70ns
t
RAC
3.3V
3.3V
V
5V
5V
324
288
252
4K
CC
13ns
15ns
20ns
t
2M x 8Bit CMOS Dynamic RAM with Fast Page Mode
CAC
3.3V
Refresh
cycle
4K
2K
396
360
324
2K
110ns
130ns
90ns
t
RC
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Normal
64ms
32ms
Refresh period
35ns
40ns
45ns
495
440
385
4K
t
PC
5V
Unit : mW
5V/3.3V
5V/3.3V
5V/3.3V
Remark
128ms
L-ver
605
550
495
2K
DESCRIPTION
(A0 - A10)
(A0 - A9)
A0-A11
A0 - A8
Note)
RAS
CAS
W
*1
*1
*1
: 2K Refresh
FUNCTIONAL BLOCK DIAGRAM
¡Ü
¡Ü
¡Ü
¡Ü
¡Ü
¡Ü
¡Ü
¡Ü
¡Ü
¡Ü
¡Ü
¡Ü
Fast Page Mode operation
Byte/Word Read/Write operation
Fast parallel test mode capability
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Self-refresh capability (L-ver only)
TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
Early Write or output enable controlled write
JEDEC Standard pinout
Available in Plastic SOJ and TSOP(II) packages
Single +5V ¡¾ 10% power supply (5V product)
Single +3.3V ¡¾ 0.3V power supply (3.3V product)
Control
Clocks
Row Address Buffer
Col. Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
VBB Generator
Column Decoder
Row Decoder
Memory Array
2,097,152 x 8
Cells
CMOS DRAM
Vcc
Vss
Data out
Data in
Buffer
Buffer
OE
DQ0
DQ7
to

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KM48V2100BK-6 Summary of contents

Page 1

... Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS- before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 2Mx8 Fast Page Mode DRAM family is fabricated using Samsung's advanced CMOS process to realize high band-width, low power consumption and high reliability. ...

Page 2

KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B KM48C/V20(1)00BK ¡Ü DQ0 2 DQ1 3 DQ2 4 DQ3 RAS 7 *A11(N.C) 8 A10 *A11 is N.C for ...

Page 3

KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage Temperature Power Dissipation Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE ...

Page 4

KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B DC AND OPERATING CHARACTERISTICS Symbol Power I Don't care CC1 Normal I Don't care CC2 L I Don't care CC3 I Don't care CC4 Normal I Don't care CC5 L I Don't care CC6 I L ...

Page 5

KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B CAPACITANCE =25 ¡É Parameter Input capacitance [A0 ~ A11] Input capacitance [RAS, CAS, W, OE] Output capacitance [DQ0 - DQ7] AC CHARACTERISTICS (0 ¡É¡Â T =5.0V ¡¾ 10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V Test condition ...

Page 6

KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B AC CHARACTERISTICS (Continued) Parameter Data set-up time Data hold time Refresh period (2K, Normal) Refresh period (4K, Normal) Refresh period (L-ver) Write command set-up time CAS to W delay time RAS to W delay time Column ...

Page 7

KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B TEST MODE CYCLE Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS ...

Page 8

KM48C2000B, KM48C2100B KM48V2000B, KM48V2100B NOTES An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is 1. achieved. V (min) and V (max) are reference levels for measuring timing ...

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