MC44011FN Motorola, MC44011FN Datasheet

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MC44011FN

Manufacturer Part Number
MC44011FN
Description
Bus controlled multistandard video processor
Manufacturer
Motorola
Datasheet

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Advance Information
Bus Controlled Multistandard
Video Processor
designed to provide RGB or YUV outputs from a variety of inputs. The inputs
can be composite video (two inputs), S–VHS, RGB, and color difference
(R–Y, B–Y). The composite video can be PAL and/or NTSC as the MC44011
is capable of decoding both systems. Additionally, R–Y and B–Y outputs and
inputs are provided for use with a delay line where needed. Sync separators
are provided at all video inputs.
subsequent triple A/D converter system which digitizes the RGB/YUV
outputs. The sampling clock (6.0 to 40 MHz) is phase–locked to the
horizontal frequency.
identification, luma, burst gate, and horizontal frequency.
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
MOTOROLA ANALOG IC DEVICE DATA
Burst Gate, Composite Sync, Vertical Sync and Field Identification Outputs
The Motorola MC44011, a member of the MC44000 Chroma 4 family, is
In addition, the MC44011 provides a sampling clock output for use by a
Additional outputs include composite sync, vertical sync, field
Control of the MC44011, and reading of status flags, is via an I 2 C bus.
Accepts NTSC and PAL Composite Video, S–VHS, RGB, and R–Y, B–Y
Includes Luma and Chroma Filters, Luma Delay Lines, and Sound Traps
Digitally Controlled via I 2 C Bus
R–Y, B–Y Inputs for Alternate Signal Source
Line–Locked Sampling Clock for A/D Converters
RGB/YUV Outputs can Provide 3.0 Vpp for A/D Inputs
Overlay Capability
Single Power Supply: 5.0 V, 5%, 550 mW (Typical)
44 Pin PLCC and QFP Packages
17.7 MHz
14.3 MHz
Field ID
Comp
Video 1
Comp
Video 2
Vertical
Output
Filter
Separator
PLL
Oscillator
Sync
Decoder
Select
Vertical
Input
Burst
Gate
V CC1
Sound Trap/Luma Filter/Luma Delay/
Decoder/Hue and Saturation Control
C Sync
16Fh/
Gnd1
Select
Separator
Chroma Filter/PAL and NTSC
Sync
PLL #1 Horizontal
Switch
Filter
Representative Block Diagram
PLL/VCO
Filter
Y1
4
H
Outputs
R–Y
Quiet
Gnd
B–Y
Ref
Fh
MC44011
15 k
Ret
MC44011FN
MC44011FB
4
Motorola, Inc. 1996
Data Bus
Device
44
R–Y
Pixel Clock
Frequency
PLASTIC PACKAGE
PLL/VCO
PLL #2
Divider
1
Filter
VIDEO PROCESSOR
PLL
ORDERING INFORMATION
BUS CONTROLLED
Saturation Control DACs
FB SUFFIX
CASE 824E
MULTISTANDARD
B–Y
Contrast, Brightness,
Color Difference
MC44011
(QFP)
SEMICONDUCTOR
Temperature Range
TECHNICAL DATA
Order this document by MC44011/D
Inputs
T A = 0 to +70 C
Stage
Y2
Operating
Interface/
Registers
I 2 C Data
Clock
R
G
PLASTIC PACKAGE
B
To A/D Converters
44
FN SUFFIX
Comm
CASE 777
1
Fast
(PLCC)
PLCC–44
Package
R/V
G/Y
B/U
V CC2
Gnd2
SDL
SCL
V CC3
Gnd3
QFP
Outputs
To P
Rev 1
1

Related parts for MC44011FN

MC44011FN Summary of contents

Page 1

... MHz Filter PLL Burst 16Fh/ Gate C Sync This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA ANALOG IC DEVICE DATA Device MC44011FN MC44011FB Representative Block Diagram Outputs Y1 R–Y B–Y 4 Data Bus 4 Sync MC44011 ...

Page 2

... MC44011 DACs MOTOROLA ANALOG IC DEVICE DATA Figure 1. ...

Page 3

... Pixel Clock VCO Gain $80 32 Blue Contrast Trim $81 32 Main Contrast NOTE: Currents out of a pin are designated –, and those into a pin are designated +. MOTOROLA ANALOG IC DEVICE DATA MC44011 Table 1. Control Bit Test Settings 0 Composite Video input selected. 0 Composite Video input selected Field Rate selected ...

Page 4

... RL RGB 1 1 1.0 – – PW 15k 0 – I ref – Min 75 6.0 3.5 85 MOTOROLA ANALOG IC DEVICE DATA Typ Max Unit 5.0 5.25 Vdc 0 0.5 Vdc 1.0 1.4 Vpp – 1.2 1.0 1.4 0.7 1.0 – 1.8 – V CC3 Vdc – V CC1 – V CC2 280 560 mVpp ...

Page 5

... With 17.7 MHz Crystal: Minimum Maximum NOTE: 1. This spec indicates a correct output amplitude at Pins 41 and 42, with respect to Y1 output. For standard color bar inputs, the output amplitude is NOTE: 1. between 1.5 and 1.7 Vpp, with the settings in Tables 1 and 2. MOTOROLA ANALOG IC DEVICE DATA MC44011 Min Typ 20 40 – ...

Page 6

... MOTOROLA ANALOG IC DEVICE DATA Max Unit 1.2 V/V – MHz – dB – ns – – – – Hz – – Vdc – – Vdc 2.0 0.4 – 4.3 – 1.8 – – 1.6 – – 100 k – ...

Page 7

... Output (Pin 13) Timing (Bit $85– (See Figures 25, 27) Rising edge from Fh rising edge Duty Cycle Composite Sync Output (Pin 13) Timing (Bit $85– Input Sync center to Output Sync center (Pins 1, 3) Input Sync center to Output Sync center (Pins 26 to 29) MOTOROLA ANALOG IC DEVICE DATA MC44011 Min Typ 1.9 2.4 1 ...

Page 8

... Fig. 33, 34 – 120 – 150 MOTOROLA ANALOG IC DEVICE DATA Max Unit – s – ns – % Vdc 4.3 3.2 – – – s – – – 1.4 Vdc MHz 4.0 60 1.9 Vdc 3.5 3.8 Vdc 12 ...

Page 9

... 0. (See power distribution diagram at the end of this section.) MOTOROLA ANALOG IC DEVICE DATA MC44011 PIN FUNCTION DESCRIPTION (Pin numbers refer to PLCC package) Video Input 1 & 2 – Video 1 (Pin 1) and Video 2 (Pin 3) are composite video inputs. Either can be NTSC or PAL. Input impedance is high, termination must be external ...

Page 10

... Gnd3 – Ground for the high frequency PLL #2. Signals at Pins should be referenced to this ground. Pixel Clock Output – Sampling clock output (TTL) for external A/D converters, and for the external frequency 200 divider. Frequency range at this pin is 6 MHz. MOTOROLA ANALOG IC DEVICE DATA Description Description 1.3 s after sync center. ...

Page 11

... R–Y, B–Y Inputs 0.47 MOTOROLA ANALOG IC DEVICE DATA MC44011 (Pin numbers refer to PLCC package) (Pin numbers refer to PLCC package) V CC3 – A 5.0 V supply ( 5%), for the high frequency PLL #2. Decoupling must be provided from this pin to Pin 17. Ripple on this pin will affect pixel clock jitter. ...

Page 12

... B–Y input. This pin is clamped, and filtered at the color subcarrier frequency, 2x, and 8x that frequency. R–Y Output – Output from the PAL/NTSC decoder. Ident Filter – A 0.1 F capacitor filters the system identification circuit in the NTSC/PAL decoder. MOTOROLA ANALOG IC DEVICE DATA ...

Page 13

... V 7.0 V 18, 33, 24, 39 (Dashed lines indicate substrate connection.) MOTOROLA ANALOG IC DEVICE DATA MC44011 (Pin numbers refer to PLCC package) (Pin numbers refer to PLCC package) Crystal PLL Filter – Components at this pin filter the PLL for the crystal chroma oscillator circuit. V CC2 V CC3 Power Distribution – ...

Page 14

... Peaking 010 –20 111 –30 –40 –50 0.1 1.0 10 MOTOROLA ANALOG IC DEVICE DATA Figure 3. S–VHS Mode Sound Trap = 1,1 All Peaking Settings 3.0 5.0 7 FREQUENCY (MHz) Figure 5. S–VHS Mode Sound Trap = 1,1 All Peaking Settings 3.0 5.0 7 FREQUENCY (MHz) Figure 7. S–VHS Mode ...

Page 15

... Figure 12. (3.58 MHz) Chroma Notch –10 –15 –20 Gain at –25 Peaking = 000 001 –30 100 101 010 011 –35 110 111 –40 3.0 3.5 f, FREQUENCY (MHz) MOTOROLA ANALOG IC DEVICE DATA MC44011 10 0 –10 000 Peaking 010 –20 111 –30 –40 Sound Trap = 1,0 –50 10 0.1 1 –10 000 – ...

Page 16

... MHz Crystal –45 6.0 5.0 (5.5 + 5.75 MHz) Sound Trap –5.0 –10 –15 –20 –25 –30 –35 –40 –45 6.2 6.6 5.0 MOTOROLA ANALOG IC DEVICE DATA Figure 15. S–VHS Mode 4.5 5.0 f, FREQUENCY (MHz) Figure 17. S–VHS Mode 5.5 6.0 f, FREQUENCY (MHz) Figure 19. S–VHS Mode Sound Trap = 0,1 Peaking = 111 17.7 MHz Crystal 5.4 5.8 6.2 6.6 ...

Page 17

... Figure 22. Composite Video Mode –15 –20 –25 –30 –35 –40 –45 6.0 6.5 f, FREQUENCY (MHz) 0 – 20 – 40 – 60 – 80 –100 0 MOTOROLA ANALOG IC DEVICE DATA MC44011 (6.0 MHz) Sound Trap –5.0 –10 –15 –20 –25 –30 –35 Sound Trap = 1,0 Peaking = 111 –40 17.7 MHz Crystal –45 6.5 5.5 (6.5 MHz) Sound Trap – ...

Page 18

... Figure 26. Horizontal PLL1 Noise Gate and Filter Pin Video Input (@ Pins Noise Gate Charge Pump Current (Pin 11) Voltage Waveform (Pin 11) 18 MC44011 3.5 s 4.5 V 1/2Fh 1/16Fh (1.4 s during vertical interval) 4.0 V 3 700 mVpp with High Gain 250 mVpp with Low Gain MOTOROLA ANALOG IC DEVICE DATA 4.5 V 4.5 V 4 ...

Page 19

... Pins NOTE: In above waveforms, all timing is referenced to the center of the incoming Sync Pulse at Pin 26 to 28, or 29. Above timings based on a 4.6 s wide sync pulse. Lower two levels of Sandcastle output alternate, based on video system in effect. MOTOROLA ANALOG IC DEVICE DATA MC44011 3.5 s 4.5 V 1/2Fh 1 ...

Page 20

... Pins 41, 42 Outputs (@ Pins 20 to 22) Input @ Pin Outputs (@ Pins 20 to 22) Color Difference Inputs Enabled 20 MC44011 50% 700 ns 50% 850 ns 50% Figure 29. Fast Commutate Timing 0 50% 50% Color Difference RGB Inputs Inputs Enabled Enabled MOTOROLA ANALOG IC DEVICE DATA ...

Page 21

... Figure 30. Horizontal Outputs versus Fields (NTSC System) Line 1 Field 2 Field 1 Composite Input (@ Pins 29) Fh Ref (Pin 14) Burst Gate (Pin 8) Composite Sync (Pin 13) Field 1 Field 2 Composite Input (@ Pins 29) Fh Ref (Pin 14) Burst Gate (Pin 8) Composite Sync (Pin 13) MOTOROLA ANALOG IC DEVICE DATA MC44011 21 ...

Page 22

... Pins 29) Fh Ref (Pin 14) Burst Gate (Pin 8) Composite Sync (Pin 13) Fh Ref (Pin 14) 15 kHz Return (Pin 15) 22 MC44011 Line 1 Field 2/4 Field 1/3 Field 1/3 Field 2/4 Figure 32. Horizontal PLL2 Timing 60 ns Determined by External Circuit (Must be > 200 ns) MOTOROLA ANALOG IC DEVICE DATA ...

Page 23

... B) Bit $78– Video Input Vert Sync Out Field 2 (Pin 4) Field Ident Out (Pin 7) Video Input Vert Sync Out (Pin 4) Field 1 Field Ident Out (Pin 7) MOTOROLA ANALOG IC DEVICE DATA MC44011 Line Field 1 500 s 110 Field 2 500 Line Field 1 ...

Page 24

... Field Ident Out (Pin 7) Video Input Vert Sync Out (Pin 4) Field Ident Out (Pin 7) 24 MC44011 Line 500 s Field 2/4 Field 1/3 110 500 s Field 1/3 Field 2 Line 500 s Field 2/4 Field 1/3 100 500 s Field 1/3 Field 2/4 144 s MOTOROLA ANALOG IC DEVICE DATA ...

Page 25

... Xtal 1 38 Oscillator 36 Xtal 2 Switches shown with control bits = 0. MOTOROLA ANALOG IC DEVICE DATA MC44011 FUNCTIONAL DESCRIPTION phase–locked to the incoming sync. The VCO’s gain is adjustable for optimum performance. The MC44011 also provides vertical sync and field identification (Field 1, Field 2) outputs. ...

Page 26

... PLL) are applied to the signals at this stage. The nominal output dc level is 2.0 to 2.5 Vdc, and the load applied to these outputs should be > Sync is not present on these outputs. MOTOROLA ANALOG IC DEVICE DATA SSC SSD Color ($7C–7) ($7A– ...

Page 27

... Low and/or RGB Low and/or RGB EN Hi MOTOROLA ANALOG IC DEVICE DATA MC44011 P1 ($7D–7) ($7E– 17.7 MHz Crystal, 6.5 MHz Sound Trap, Composite Video Mode Table 6. Luma Delay 14.3 MHz Crystal Comp. Video S– ...

Page 28

... NOTES Switches controlled Interface – See Text. YUV Outputs ($82– mid–scale. Brightness $84–0/5 $82–7 5.0 DC ($85–0/5) 390 20 R/V 5 ($7E–0/5) 390 21 Outputs G/Y 5.0 DC ($83–0/5) 390 22 B/U Gain U DC ($7D–0/5) ($80–0/ Clamp Circuit MOTOROLA ANALOG IC DEVICE DATA ...

Page 29

... Frequency Divider Comparator 4.43 MHz/ 3.58 MHz VCO SC $86–6 From Sync Separator $78–6 MOTOROLA ANALOG IC DEVICE DATA MC44011 Color or Color Diff Contrast Gain Brightness in clamping levels of should be set bias the U and V outputs to 2.3 V. The Y output clamp will remain at Horizontal PLL (PLL1) ...

Page 30

... Monitor L2 Gain f H from PLL1 $83–7 Up Phase and Charge Frequency Pump Down Comparator Return 15625 Hz or 15750 Hz MOTOROLA ANALOG IC DEVICE DATA Set Bit $84– Flag 19 (VCO HI) Flag 20 (VCO LO) VCO Gain $7F–5/0 B VCO 2 $85– PLL2 Filter Pixel Clock ...

Page 31

... Counter Vertical Sync Flag 14 (< 576 Lines) Flag 15 (Vert countdown engaged) MOTOROLA ANALOG IC DEVICE DATA MC44011 The sync output (Pin active low signal which starts after the horizontal half–line sync pulses change polarity (see Figures 33 and 34). The pulse width is nominally 500 s for both PAL and NTSC signals. The position of this sync pulse’ ...

Page 32

... Clock Counter 8–Bit Shift Register 19 Registers Flag Data Table 12. Sync Source RGB Sync ($88–6) Sync Source 0 0 None 0 1 RGB (Pins 26–28 (Pin 29 Comp. Video (Pins 1, 3) Chip Read/ Address Write Latch Latch Sub–Address Latches MOTOROLA ANALOG IC DEVICE DATA ...

Page 33

... Table brief explanation of the individual control bits. A more detailed explanation of the functions is found in the block diagram description of the text (within the Functional Description section). Table 15 provides an explanation of the MOTOROLA ANALOG IC DEVICE DATA MC44011 generated by the MC44011, which tells the master to continue the communication. The second byte is then entered, followed by an acknowledge ...

Page 34

... When 0, Pin 12 is open. When 1, Pin 12 is internally switched to ground, allowing the PLL1 filter operation to be adjusted for noisy signals. $85–7 PClk/2 When 0, the PLL2 VCO provides the Pixel Clock at Pin 18 directly. When 1, the VCO output is directed through a 34 MC44011 Table 14. Control Bit Description Description 2 stage, and then to Pin 18. MOTOROLA ANALOG IC DEVICE DATA ...

Page 35

... Bit $86–6 is set to 0 after having been a 1. NOTE: The above DACs are 6–bits wide. The settings mentioned above, and in subsequent paragraphs are given in decimal values 63. These are not hex values. MOTOROLA ANALOG IC DEVICE DATA MC44011 (continued) Description 250 kHz (16 x Fh) ...

Page 36

... The MC44011 flags must be read on a regular basis to determine the status of the various circuit blocks. The MC44011 does not generate interrupts recommended the flags be read once per field or frame. See Table 16 for a description of the flags. Table 16. Flag Description Description (When Flag = 1) MOTOROLA ANALOG IC DEVICE DATA 2 2 block ...

Page 37

... Operating Mode: Fundamental series resonance Load Capacitance: Nominally 20 pF Motional Capacitance Series Resistance: < 30 (nominally 10 ) MOTOROLA ANALOG IC DEVICE DATA MC44011 APPLICATIONS INFORMATION can be non–precision. Table 18 describes the external components for each pin. Figure 42. Basic Functional Circuit 470 470 Input ...

Page 38

... A from the 5.0 V source. This pin must be well filtered to the Quiet resistors protect the pins from ESD and RFI. resistor protects the pin from ESD and RFI. The directly. If required to do so, see text for MOTOROLA ANALOG IC DEVICE DATA directly. If required to do so, see text for ...

Page 39

... Y1 Out 300 75 470 MOTOROLA ANALOG IC DEVICE DATA MC44011 The Y1 output (Pin 33) has an output impedance of 300 , and can be used as a monitoring point drive the input of the MC44145 sync separator, or other high impedance loads (minimum load for ...

Page 40

... Flag 24 (PAL Identified) – This flag when PAL signals are applied, and a 0 when NTSC signals are applied, or when no burst is present recommended that the Color Decoder section, and crystal, should be set according to the state of Flags 14, 23, and 24 according to Table 20 Gain = 0 CBI = 0 CAI = 1 MOTOROLA ANALOG IC DEVICE DATA ...

Page 41

... Xtal 2 36 14.3 MHz SandC 35 34 Sys Sel 42 R–Y Out B–Y Out 41 R– 0.1 B– MOTOROLA ANALOG IC DEVICE DATA MC44011 Table 20. Color Standard Selection Table Bit Settings SSA ($7C–6) Crystal Either 1 Either 1 17.7 MHz 0 14.3 MHz 1 (Note 1) 0 The System Select voltage is set when the color decoder is set with Bits SSA, SSB, SSC, SSD ...

Page 42

... Voltages are nominal, and do not represent guaranteed limits. 42 MC44011 Figure 45. Typical Waveforms É É É É É É É É É É É É 1200 700 É É É É É É É É 770 MOTOROLA ANALOG IC DEVICE DATA 950 400 1200 1460 440 ...

Page 43

... A 5 (MSB) MOTOROLA ANALOG IC DEVICE DATA MC44011 that it equals the horizontal frequency. The PLL within the MC44011 (or the MC44145) compares the horizontal frequency with the returned frequency, and adjusts the internal VCO accordingly, to achieve the proper relationship – negative– ...

Page 44

... MC14576A R7 Red * Green * Digital Outputs Blue * Video 1 MC44011 75 MC14576A 75 3 Video 2 Set Bits: 75 $77– $77– $88– 17.7 MHz Xtal Xtal 2 120 pF 14.3 MHz MOTOROLA ANALOG IC DEVICE DATA ...

Page 45

... Horizontal Loop (PLL1) Enabled 12 Horizontal Loop not Locked 13 Internally Set Less than 576 Lines 15 Vertical Decoder Engaged 16 Internally Set Internally Set to 1 MOTOROLA ANALOG IC DEVICE DATA MC44011 APPENDIX A Control Bit Summary FSI L2 Gate BLCP PLL2 0 = Clamp ...

Page 46

... Yes Adjust Contrast, Brightness, Trim, Set PLL1 Gain Hue, Saturation and other DACs High $83– Set Vert Decoder to Auto Countdown (Set $77– Monitor Flags on a continuing basis MOTOROLA ANALOG IC DEVICE DATA Set $80– (Pin 25 must be high) Yes YX Enable? No Yes Y2 Enable? No Set $81– ...

Page 47

... At the 9th Clock Pulse, the master must release the Data line high, and the slave must provide an acknowledge bit by pulling Data low during this clock time. If the master does not receive a proper acknowledge, it can terminate the operation. MOTOROLA ANALOG IC DEVICE DATA MC44011 APPENDIX C 2 ...

Page 48

... Charge–Pump Phase–Lock–Loops by Floyd M. Gardner, IEEE Transactions on Communications, Vol. com–28, no. 11, Nov. 1980. (2) Phaselock Techniques by Floyd M. Gardner, J. Wiley & Sons, 1979. (3) Phase–Locked–Loops by Roland E. Best, McGraw Hill, 1984. (4) AN–535, Phase–Locked–Loop Design Fundamentals , Motorola. 48 MC44011 ...

Page 49

... Frame – The information which makes up one complete picture. It consists of 525 lines in NTSC systems, and 625 lines in PAL systems. An interlaced system is typically composed of two fields. MOTOROLA ANALOG IC DEVICE DATA MC44011 GLOSSARY Front Porch – The blanking time immediately before the sync signal. ...

Page 50

... L– 0.007(0.180 L– MILLIMETERS MIN MAX 17.40 17.65 17.40 17.65 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 ––– 0.51 ––– ––– 0.64 ––– 16.51 16.66 16.51 16.66 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0. 15.50 16.00 ––– 1.02 ––– MOTOROLA ANALOG IC DEVICE DATA ...

Page 51

... PIN 1 IDENT 44 1 –L– VIEW 40X 12 –N– DATUM –H– PLANE VIEW P MOTOROLA ANALOG IC DEVICE DATA MC44011 OUTLINE DIMENSIONS FB SUFFIX PLASTIC PACKAGE CASE 824E–02 (QFP) ISSUE –M– VIEW P DATUM – ...

Page 52

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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