MC68341FT16 Motorola, MC68341FT16 Datasheet
MC68341FT16
Related parts for MC68341FT16
MC68341FT16 Summary of contents
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Parts Not Suitable for New Designs For Additional Information End-Of-Life Product Change Notice ...
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... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. " ...
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... Timer Modules 68K FAX-IT – Documentation Comments FAX 512-891-8593—Documentation Comments Only The Motorola High-End Technical Publications Department provides a fax number for you to submit any questions or comments about this document or how to order other documents. We welcome your suggestions for improving our documentation. Please do not fax technical questions ...
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UNITED STATES ALABAMA, Huntsville ARIZONA, Tempe CALIFORNIA, Agoura Hills CALIFORNIA, Los Angeles CALIFORNIA, Irvine CALIFORNIA, Rosevllle CALIFORNIA, San Diego CALIFORNIA, Sunnyvale COLORADO , Colorado Springs COLORADO , Denver CONNECTICUT, Wallingford FLORIDA , Maitland FLORIDA , Pompano Beach/Fort. Lauderdale FLORIDA , ...
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... Bus Grant Acknowledge (BGACK) .................................................. 2-10 2.4.4 Read-Modify-Write Cycle (RMC/RTCOUT) ..................................... 2-10 2.5 Exception Control Signals ................................................................... 2-10 2.5.1 Reset (RESET) ................................................................................ 2-10 2.5.2 Halt (HALT) ...................................................................................... 2-10 2.5.3 Bus Error (BERR ) ............................................................................ 2-10 2.6 Clock Signals ...................................................................................... 2-11 2.6.1 System Clock (CLKOUT)................................................................. 2-11 2.6.2 Crystal Oscillator (EXTAL, XTAL) .................................................... 2-11 MOTOROLA Title Section 1 Device Overview Section 2 Signal Descriptions MC68341 USER'S MANUAL UM Rev 1 Page Number iii ...
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... Test Mode Select (TMS) ................................................................. 2-16 2.12.3 Test Data In (TDI) ............................................................................ 2-16 2.12.4 Test Data Out (TDO) ....................................................................... 2-16 2.13 Real Time Clock Mode Signals ........................................................... 2-16 2.13.1 Battery Switch (BSW ) ...................................................................... 2-16 2.13.2 Battery Voltage (V BATT ) ................................................................. 2-16 2.13.3 Real Time Clock Output (RMC/RTCOUT) ....................................... 2-17 2.14 System Power and Ground (V CC AND GND) .................................... 2-17 iv Title MC68341 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Synchronous Operation with DSACK≈ ................................................ 3-16 3.3.6 Fast Termination Cycles ...................................................................... 3-17 3.4 Data Transfer Cycles ........................................................................... 3-18 3.4.1 M68300 Read Cycle ................................................................................ 3-18 3.4.2 68000 Read Cycle ................................................................................... 3-21 3.4.3 M68300 Write Cycle ................................................................................ 3-23 3.4.4 68000 Write Cycle ................................................................................... 3-26 3.4.5 Read-Modify-Write Cycle ........................................................................ 3-29 3.5 CPU Space Cycles.................................................................................. 3-31 3.5.1 Breakpoint Acknowledge Cycle............................................................... 3-31 MOTOROLA Title Section 3 Bus Operation MC68341 USER'S MANUAL UM Rev 1 Page Number v ...
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... Using the Periodic Timer as a Real-Time Clock........................... 4-9 4.2.2.7 Simultaneous Interrupts by Sources in the SIM41 ........................... 4-9 4.2.3 Clock Synthesizer Operation ............................................................... 4-9 4.2.3.1 Phase Comparator and Filter........................................................... 4-12 4.2.3.2 Frequency Divider. ........................................................................... 4-12 4.2.3.3 Clock Control ................................................................................... 4-15 4.2.4 Chip Select Operation ......................................................................... 4-15 4.2.4.1 Programmable Features .................................................................. 4-15 4.2.4.2 Global Chip Select Operation .......................................................... 4-16 vi Title Section 4 System Integration Module MC68341 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Real Time Clock ...................................................................................... 4-39 4.4.1 Reset ................................................................................................... 4-39 4.4.2 RTC Interrupt Control Register (RICR)................................................ 4-39 4.4.3 RTC Control/Status Register (RCR) .................................................... 4-40 4.4.3 RTC Calibration Control Register (RCCR) .......................................... 4-41 4.4.4 RTC Time of Day Registers ................................................................. 4-43 4.4.5 RTC Alarm Registers........................................................................... 4-45 4.4.6 RTC Power Up Operation .................................................................... 4-46 4.4.7 RTC Power Down Operation ............................................................... 4-46 MOTOROLA Title MC68341 USER'S MANUAL UM Rev 1 Page Number vii ...
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... Condition Tests ............................................................................ 5-27 5.3.4 Using the TBL Instructions .............................................................. 5-27 5.3.4.1 Table Example 1 Standard Usage ........................................... 5-28 5.3.4.2 Table Example 2 Compressed Table ....................................... 5-29 5.3.4.3 Table Example 3 8-Bit Independent Variable........................... 5-30 5.3.4.4 Table Example 4 Maintaining Precision ................................... 5-32 5.3.4.5 Table Example 5 Surface Interpolations .................................. 5-34 5.3.5 Nested Subroutine Calls.................................................................. 5-34 viii Title SECTION 5 CPU32 MC68341 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Type II—Correcting Faults via RTE.......................................... 5-56 5.5.3.2.4 Type III—Correcting Faults via Software .................................. 5-56 5.5.3.2.5 Type III—Correcting Faults by Conversion and Restart ........... 5-56 5.5.3.2.6 Type III—Correcting Faults via RTE......................................... 5-57 5.5.3.2.7 Type IV—Correcting Faults via Software ................................. 5-57 5.5.4 CPU32 Stack Frames ...................................................................... 5-58 5.5.4.1 Four-Word Stack Frame .............................................................. 5-58 MOTOROLA Title MC68341 USER'S MANUAL UM Rev 1 Page Number ix ...
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... Read Memory Location (READ) ............................................... 5-77 5.6.2.8.9 Write Memory Location (WRITE) ............................................. 5-78 5.6.2.8.10 Dump Memory Block (DUMP). ................................................. 5-79 5.6.2.8.11 Fill Memory Block (FILL) .......................................................... 5-80 5.6.2.8.12 Resume Execution (GO) .......................................................... 5-81 5.6.2.8.13 Call User Code (CALL) ............................................................ 5-82 5.6.2.8.14 Reset Peripherals (RST) .......................................................... 5-84 5.6.2.8.15 No Operation (NOP) ................................................................. 5-84 5.6.2.8.16 Future Commands.................................................................... 5-85 5.6.3 Deterministic Opcode Tracking ....................................................... 5-85 5.6.3.1 Instruction Fetch (IFETCH) .......................................................... 5-85 x Title MC68341 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Binary-Coded Decimal and Extended Instructions ...................... 5-103 5.7.3.8 Single Operand Instructions......................................................... 5-103 5.7.3.9 Shift/Rotate Instructions ............................................................... 5-104 5.7.3.10 Bit Manipulation Instructions ........................................................ 5-105 5.7.3.11 Conditional Branch Instructions ................................................... 5-105 5.7.3.12 Control Instructions ...................................................................... 5-106 5.7.3.13 Exception-Related Instructions and Operations........................... 5-107 5.7.3.14 Save and Restore Operations...................................................... 5-108 MOTOROLA Title MC68341 USER'S MANUAL UM Rev 1 Page Number xi ...
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... Fast Termination Option .................................................................. 6-22 6.7 Register Description................................................................................ 6-23 6.7.1 Byte Transfer Counter Register (BTC) ................................................ 6-25 6.7.2 Channel Control Register (CCR) ......................................................... 6-25 6.7.3 Channel Status Register (CSR) .......................................................... 6-29 6.7.4 Destination Address Register (DAR) ................................................... 6-30 6.7.5 Function Code Register (FCR) ............................................................ 6-31 6.7.6 Interrupt Register (INTR) ..................................................................... 6-32 xii Title Section 6 DMA Controller Module MC68341 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Channel A Clear-To-Send (CTSA ) ................................................. 7-7 7.2.11 Channel B Clear-To-Send (CTSB ) ................................................. 7-7 7.2.12 Channel A Transmitter Ready (T≈RDYA ) ........................................ 7-7 7.2.13 Channel A Receiver Ready (R≈RDYA) ............................................ 7-7 7.3 Operation ............................................................................................ 7-8 7.3.1 Baud Rate Generator ...................................................................... 7-8 7.3.2 Transmitter and Receiver Operating Modes.................................... 7-8 7.3.2.1 Transmitter ................................................................................... 7-10 7.3.2.2 Receiver ....................................................................................... 7-11 7.3.2.3 FIFO Stack ................................................................................... 7-13 MOTOROLA Title Section 7 Serial Module MC68341 USER'S MANUAL UM Rev 1 Page Number xiii ...
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... Outport Port Control Register (OPCR)......................................... 7-38 7.4.1.15 Receiver Buffer (RB) .................................................................... 7-39 7.4.1.16 Status Register (SR) .................................................................... 7-39 7.4.1.17 Transmitter Buffer (TB) ................................................................ 7-41 7.4.2 Programming ................................................................................... 7-42 7.4.2.1 Serial Module Initialization. .......................................................... 7-42 7.4.2.2 I/O Driver Example....................................................................... 7-42 7.4.2.3 Interrupt Handling ........................................................................ 7-42 7.5 Serial Module Initialization Sequence ................................................ 7-48 7.5.1 Serial Module Configuration ............................................................ 7-48 7.5.2 Serial Module Example Configuration Code ................................... 7-50 xiv Title MC68341 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Interrupt Register (IR) ....................................................................... 8-18 8.4.3 Control Register (CR) ....................................................................... 8-19 8.4.4 Status Register (SR)......................................................................... 8-22 8.4.5 Counter Register (CNTR) ................................................................. 8-24 8.4.6 Preload 1 Register (PREL1) ............................................................. 8-24 8.4.7 Preload 2 Register (PREL2) ............................................................. 8-25 8.4.8 Compare Register (COM) ................................................................. 8-25 8.5 Timer Module Initialization Sequence .................................................. 8-26 8.5.1 Timer Module Configuration ............................................................. 8-26 8.5.2 Timer Module Example Configuration Code..................................... 8-27 MOTOROLA Title Section 8 Timer Module MC68341 USER'S MANUAL UM Rev 1 Page Number xv ...
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... QSPI Control Register 3 (SPCR3) ............................................... 9-24 9.5.4.5 QSPI Status Register (SPSR) ..................................................... 9-25 9.5.4.6 QSPI RAM ................................................................................... 9-26 9.5.4.6.1 Receive Data RAM (REC.RAM) ............................................... 9-27 9.5.4.6.2 Transmit Data RAM (TRAN.RAM)............................................ 9-27 9.5.4.6.3 Command RAM (COMD.RAM) ................................................ 9-27 9.5.5 Operating Modes and Flowcharts ................................................... 9-30 9.5.5.1 Master Mode ................................................................................ 9-37 9.5.5.1.1 Master Mode Operation ........................................................... 9-37 9.5.5.1.2 Master Wraparound Mode........................................................ 9-38 xvi Title Section 9 MC68341 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Memory Interface Information ............................................................. 11-5 11.2.1 Using an 8-Bit Boot ROM ................................................................ 11-5 11.2.2 Access Time Calculations................................................................ 11-6 11.2.3 Calculating Frequency-Adjusted Output .......................................... 11-7 11.2.4 Interfacing an 8-Bit Device to 16-Bit Memory Using Single-Address DMA Mode .......................................................... 11-10 11.3 Power Consumption Considerations ................................................... 11-10 11.4 MC68341V (3.3 V)............................................................................... 11-11 MOTOROLA Title Section 10 IEEE 1149.1 Test Access Port Section 11 Applications MC68341 USER'S MANUAL UM Rev 1 Page Number xvii ...
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... AC Electrical Specification Definitions ................................................ 12-2 12.5 DC Electrical Specifications ................................................................ 12-5 12.6 AC Electrical Specifications Control Timing ........................................ 12-6 12.7 AC Timing Specifications .................................................................... 12-7 12.8 DMA Module AC Electrical Specifications .......................................... 12-22 12.9 Timer Module Electrical Specifications ............................................... 12-24 12.10 Serial Module Electrical Specifications ............................................... 12-26 12.11 QSPM Electrical Specifications ........................................................... 12-29 12.12 IEEE 1149.1 Electrical Specifications ................................................. 12-32 xviii Title Section 12 Electrical Characteristics MC68341 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Late Retry Sequence ................................................................................... 3-47 3-27 HALT Timing ................................................................................................. 3-48 3-28 Bus Arbitration Flowchart for Single Request .............................................. 3-50 3-29 Bus Arbitration Timing Diagram—Idle Bus Case ......................................... 3-51 3-30 Bus Arbitration Timing Diagram—Active Bus Case ..................................... 3-51 3-31 Bus Arbitration State Diagram ...................................................................... 3-54 3-32 Show Cycle Timing Diagram ........................................................................ 3-55 MOTOROLA Title MC68341 USER'S MANUAL UM Rev 1 Page Number xix ...
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... BKPT Timing for Single Bus Cycle .............................................................. 5-70 5-25 BKPT Timing for Forcing BDM..................................................................... 5-70 5-26 BKPT/DSCLK Logic Diagram....................................................................... 5-70 5-27 Command Sequence Diagram..................................................................... 5-73 5-28 Functional Model of Instruction Pipeline ...................................................... 5-86 5-29 Instruction Pipeline Timing Diagram ............................................................ 5-86 5-30 Block Diagram of Independent Resources .................................................. 5-88 5-31 Simultaneous Instruction Execution ............................................................. 5-90 5-32 Attributed Instruction Times ......................................................................... 5-90 xx Title MC68341 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Baud Rate Generator Block Diagram........................................................... 7-8 7-4 Transmitter and Receiver Functional Diagram............................................. 7-9 7-5 Transmitter Timing Diagram ......................................................................... 7-10 7-6 Receiver Timing Diagram............................................................................. 7-12 7-7 Looping Modes Functional Diagram............................................................. 7-15 7-8 Multidrop Mode Timing Diagram .................................................................. 7-16 7-9 Serial Module Programming Model Programming Model ............................ 7-19 7-10 Serial Module Programming Flowchart ....................................................... 7-43 MOTOROLA Title MC68341 USER'S MANUAL UM Rev 1 Page Number xxi ...
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... Statek Corporation Crystal Circuit ................................................................ 11-2 11-4 XFC and VCCSYN Capacitor Connections.................................................. 11-3 11-5 SRAM Interface ............................................................................................ 11-4 11-6 ROM Interface.............................................................................................. 11-4 11-7 Serial Interface ............................................................................................. 11-5 11-8 External Circuitry for 8-Bit Boot ROM .......................................................... 11-5 11-9 8-bit Boot ROM Timing ................................................................................ 11-6 11-10 Access Time Computation Diagram ............................................................ 11-6 11-11 Signal Relationships to CLKOUT ................................................................. 11-7 xxii Title MC68341 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Serial Module Synchronous Mode Timing Diagram ..................................... 12-28 12-24 QSPI Timing Master, CPHA 0 ...................................................................... 12-30 12-25 QSPI Timing Master, CPHA 1 ...................................................................... 12-30 12-26 QSPI Timing Slave, CPHA 0 ........................................................................ 12-31 12-27 QSPI Timing Slave, CPHA 1 ........................................................................ 12-31 12-28 Test Clock Input Timing Diagram ................................................................. 12-32 12-29 Boundary Scan Timing Diagram .................................................................. 12-33 12-30 Test Access Port Timing Diagram ................................................................ 12-33 MOTOROLA Title MC68341 USER'S MANUAL UM Rev 1 Page Number xxiii ...
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... Port B Pin Assignment Register................................................................... 4-17 4-5 Port A Pin Assignment Register................................................................... 4-17 4-6 Port B Pin Assignment Register................................................................... 4-18 4-7 SHENx Control Bits ...................................................................................... 4-24 4-8 Deriving Software Watchdog Timeout ......................................................... 4-27 4-9 BMTx Encoding ............................................................................................ 4-27 4-10 PIRQL Encoding .......................................................................................... 4-28 4-11 DDx Encoding .............................................................................................. 4-34 4-12 PSx Encoding............................................................................................... 4-34 4-13 RIRQL Encoding .......................................................................................... 4-40 xxiv LIST OF TABLES Title MC68341 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... FRZx Control Bits ......................................................................................... 6-33 7-1 RCSx Control Bits ........................................................................................ 7-21 7-2 TCSx Control Bits......................................................................................... 7-22 7-3 MISCx Control Bits ....................................................................................... 7-23 7-4 TCx Control Bits ........................................................................................... 7-24 7-5 RCx Control Bits ........................................................................................... 7-25 7-6 FRZx Control Bits ......................................................................................... 7-31 7-7 PMx and PT Control Bits .............................................................................. 7-34 7-8 B/Cx Control Bits .......................................................................................... 7-34 7-9 CMx Control Bits .......................................................................................... 7-35 7-10 SBx Control Bits ........................................................................................... 7-36 MOTOROLA Title MC68341 USER'S MANUAL UM Rev 1 Page Number xxv ...
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... External Pin Inputs/Outputs to the QSPI...................................................... 9-17 9-7 QSPI Registers ............................................................................................ 9-17 9.8 Bits per Transfer if Command Control Bit BITSE = 1 ................................... 9-19 9-9 Examples of SCK Frequencies .................................................................... 9-20 10-1 Boundary Scan Control Bits ......................................................................... 10-4 10-2 Boundary Scan Bit Definitions ..................................................................... 10-5 10-3 Instructions................................................................................................... 10-10 11-1 Memory Access Times at 16.78 MHz .......................................................... 11-7 11-2 Typical Electrical Characteristics ................................................................. 11-11 xxvi Title MC68341 USER’S MANUAL UM Rev.1.0 Page Number MOTOROLA ...
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... Figure 1-1 illustrates a block diagram of the MC68341. CPU32 (68000-BASED PROCESSOR) QUEUED SERIAL PERIPHERAL INTERFACE Figure 1-1. MC68341 Simplified Block Diagram MOTOROLA INTEGRATION MODULE TWO-CHANNEL PROTECTION TIMER DMA CONTROLLER SYNTHESIZER INTERMODULE BUS BUS INTERFACE ...
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... Fully Static HCMOS Technology — Programmable Clock Synthesizer for Full Frequency Control — Power-Down/Low Power Stop Capabilities — Idle Modules Can Be Individually Powered Down • 0– MHz Operation • 160-Pin Plastic Quad Flat Pack (QFP) 1-2 MC68341 USER’S MANUAL MOTOROLA ...
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... Chip Select and Wait State Generation—Offers eight programmable chip selects which provide signals to enable external memory and peripheral circuits and create all external handshaking and timing signals six wait states can be automatically inserted. MOTOROLA MC68341 USER’S MANUAL 1- 3 ...
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... MC68341 can replace. For applications employing reduced voltage operation, selection of the MC68341V, which requires only a 3.3-V power supply, reduces current consumption by 40–60% in all modes of operation (as well as reducing noise emissions). 1-4 MC68341 USER’S MANUAL HCMOS process MOTOROLA ...
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... The extra demands of full-motion video CD-I systems make the best use of the MC68341 high performance. The MC68341 is CD-I compliant and has been CD-I qualified. With its low voltage operation, the MC68341V is the only practical choice for portable CD-I. MOTOROLA MC68341 USER’S MANUAL 1- 5 ...
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... SECTION 2 SIGNAL DESCRIPTIONS This section contains brief descriptions of the MC68341 input and output signals in their functional groups as shown in Figure 2-1. MOTOROLA MC68341 USER’S MANUAL 2- 1 ...
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... Figure 2-1. Functional Signal Groups 2-2 TEST CPU32 CORE SYSTEM INTEGRATION IMB MODULE TWO-CHANNEL DMA CLOCK CONTROLLER MC68341 USER’S MANUAL RxDA TxDA TWO-CHANNEL CTSA SERIAL RxDB I/O TxDB CTSB TxRDYA/OP6 RxRDYA/FFULLA/OP4 OUTPUT PORT RTSB/OP1 RTSA/OP0 MISO MOSI TIMER QUEUED PCS1 SERIAL MODULE MODULE PCS0 QSCLK MOTOROLA ...
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... M68000 Address Strobe Upper Data Strobe Lower Data Strobe Upper Write Enable Lower Write Enable Size Read/Write Reset Halt Bus Error MOTOROLA Table 2-1. Bus Signal Summary Mnemonic A23–A0 A31–A24/ IACK7–1 D15–D0 FC3/DTC FC2–FC0 CS7–CS1 IRQ7–1/ B7–B1 ...
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... Table 2-5. DMA Module Mnemonic DREQ2, DREQ1 DACK2 DACK1 DONE2, DONE1 TGATE, RDY1 TIN, RDY2 TIN, RDY2 MC68341 USER’S MANUAL Input/ Output Out/In Out/Out In/— Out Input/ Output In Out In Out/Out In In Out/Out Out/Out/ Out Input/ Output I/O In I/O I/O Input/ Output In Out I MOTOROLA ...
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... BUS SIGNALS The MC68341 can interface using either a 68000 family bus or an MC68341 Family bus. Many of the signals are common to both bus types. Refer to Section 3 Bus Operation for more information on the two types of buses. MOTOROLA Table 2-6. Timer Module Mnemonic TGATE, RDY1 ...
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... For a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The MC68341 places the data on the data bus approximately one-half clock cycle after AS is asserted in a write cycle. 2 AS68K ) MC68341 USER’S MANUAL MOTOROLA ...
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... UDS/LDS for a 68000 write cycle. The equations of the byte write enables are as follows: W 2.2.8 Read/Write (R/ This active-high output signal is driven by the bus master to indicate the direction of a data transfer on the bus. A logic one indicates a read from a slave device; a logic zero indicates a write to a slave device. MOTOROLA UDS , UDS = A0 LDS = A0 SIZ0 SIZ1 ...
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... Table 2-10. SIZx Signal Encoding SIZ1 SIZ0 Transfer Size Three Byte 0 0 Long Word Address Spaces Reserved (Motorola User Data Space User Program Space Reserved (User ) Reserved (Motorola Supervisor Data Space 1 1 ...
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... The following signals are the bus arbitration control signals used to determine the bus master. Refer to Section 3 Bus Operation for more information on these signals. BR 2.4.1 Bus Request ( This active-low input signal indicates that an external device needs to become the bus master. MOTOROLA (IRQ7 — IRQ1) DSACK1, DSACK0 DSACK¯ Table 2-12. Encoding ...
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... This active-low input signal indicates that an invalid bus operation is being attempted or, when used with HALT, that the processor should retry the current cycle. Refer to Section 3 Bus Operation for a description of the effects of BERR on bus operation. 2-10 (BGACK) RMC /RTCOUT) ) MC68341 USER’S MANUAL MOTOROLA ...
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... These signals are used for test or software debugging. See Section 5 CPU32 for more information on these signals and background debug mode. 2.7.1 Instruction Fetch This pin functions as IFETCH in normal operation and as DSI in background debug mode. MOTOROLA (IFETCH / DSI) MC68341 USER’S MANUAL 2- 11 ...
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... Module for additional information on these signals. DREQ2, DREQ1 2.8.1 DMA Request ( This active-low input is asserted by a peripheral device to request an operand transfer between that peripheral and memory. The assertion of DREQ≈ starts the DMA process. 2-12 (IPIPE/ ) DSO ) /DSCLK ) MC68341 USER’S MANUAL MOTOROLA ...
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... An external clock can be connected to the X1 pin left floating in this case. 2.9.2 Serial External Clock Input (SCLK) This input can be used as the external clock input for channel A or channel B, bypassing the baud rate generator. MOTOROLA (DACK2, DACK1) ) DTC ) ...
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... When used for this function, this output is controlled by bit 6 in the output port data registers. (R¯RDYA / FFULLA/ OP4) 2.9.8 Receiver Ready This active-low output signal can be programmed as the channel A receiver ready, channel A FIFO full indicator dedicated parallel output. 2-14 (RTSA , RTSB / /OP0 OP1 (T¯RDYA / ) OP6 MC68341 USER’S MANUAL ) MOTOROLA ...
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... The following external signals are used by the timer modules. See Section 8 Timer Modules for additional information on these signals. TGATE 2 2.11.1 Timer Gate ( This active-low input can be programmed to enable and disable the counters and prescalers. TGATE can also be programmed as a simple input. MOTOROLA PCS1, PCS0 ) MC68341 USER’S MANUAL ) 2- 15 ...
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... V BATT See Section 4 System Integration Module for more information. 2.13.2 Battery Voltage (V BATT ) This pin supplies power to maintain the real-time clock when the rest of the chip is powered down. See Section 4 System Integration Module for more information. 2-16 BSW ) MC68341 USER’S MANUAL MOTOROLA ...
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... SYSTEM POWER AND GROUND (V CC AND GND) These pins provide system power and ground to the MC68341. Multiple pins are provided for adequate current capability. All power supply pins must have adequate bypass capacitance for high-frequency noise suppression. MOTOROLA RMC /RTCOUT ) MC68341 USER’S MANUAL ...
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... The three strobe signals AS68K , UDS , and LDS are dedicated for 68000 bus cycles. These signals assert only for 68000 bus cycles, while AS and DS assert only for M68300 bus cycles. The timing of shared signals CS≈, UWE, and LWE is modified depending on MOTOROLA NOTE MC68341 USER’S MANUAL ...
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... Strobe signals, one for the address bus and another for the data bus, indicate the validity of the address and provide timing information for the data. Both asynchronous and synchronous operation is possible for any port width. 3-2 MC68341 USER’S MANUAL MOTOROLA ...
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... Table 3-1 lists the encoding of the SIZx signal. These signals are valid while AS or AS68K is asserted. The R/W signal determines the MOTOROLA t su SAMPLE WINDOW Figure 3-1. Input Sample Window NOTE MC68341 USER’ ...
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... If DMA transfers are programmed with FC3 set, this signal can be used externally to distinguish DMA bus activity from CPU accesses. 3-4 Table 3-1. SIZx Signal Encoding SIZ1 SIZ0 Transfer Size 0 1 Byte 1 0 Word 1 1 Three Bytes 0 0 Long Word MC68341 USER’S MANUAL MOTOROLA ...
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... The MC68341 asserts DS approximately one clock cycle MOTOROLA Address Spaces Reserved (Motorola User Data Space User Program Space Reserved (User ) Reserved (Motorola Supervisor Data Space Supervisor Program Space CPU Space DMA Space AS ) AS68K ) MC68341 USER’S MANUAL 3- 5 ...
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... Refer to Section 4 System Integration Module for additional information. The SIM41 can alternatively be 3-6 UDS LDS and UWE and UWE = R LWE = R (A0 • SIZ0) UWE = R/W + UDS LWE = R/W + LDS DTC ) MC68341 USER’S MANUAL ) LWE ) DSACK1 AND MOTOROLA ...
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... MC68341 through the use of the DSACK≈ inputs. Refer to Table 3-3 for DSACK≈ encoding. MOTOROLA ). This signal is also a bus cycle termination indicator and AVEC ).This signal can be used to terminate interrupt MC68341 USER’ ...
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... Insert Wait States in Current Bus Cycle 0 (Asserted) Complete Cycle—Data Bus Port Size Is 8 Bits 1 (Negated) Complete Cycle—Data Bus Port Size Is 16 Bits 0 Reserved—Defaults to 16-Bit Port Size Can Be (Asserted) Used for 32-Bit DMA cycles MC68341 USER’S MANUAL MOTOROLA ...
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... The only type of transfer that can be performed to an odd address is a single-byte transfer, referred odd-byte transfer misaligned access is attempted, the CPU32 generates an address error exception, and enters exception processing. Refer to Section 5 CPU32 for more information on exception processing. MOTOROLA OPERAND OP0 31 ...
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... The slave then asserts DSACK1 to terminate the bus cycle. 3- SIZ1 SIZ0 0 (OP0 SIZ1 SIZ0 (OP0) 0 MC68341 USER’S MANUAL A0 DSACK1 DSACK0 DSACK1 DSACK0 MOTOROLA ...
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... The slave device then reads the most significant byte of the operand from bits 15–8 of the data bus and asserts DSACK0 to indicate that it received the data but is an 8-bit port. The MC68341 then decrements the transfer size counter, increments the address, and writes the least significant byte of the operand to bits 15–8 of the data bus. MOTOROLA OP0 0 7 ...
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... SIZ1 1 OP1 OP0 OP1 OP2 OP3 SIZ1 (OP1) 0 OP0 1 OP1 (OP1) 1 OP2 (OP3) 0 OP3 (OP3) MC68341 USER’S MANUAL SIZ0 A0 DSACK1 DSACK0 SIZ0 A0 DSACK1 DSACK0 MOTOROLA ...
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... R SIZ0 4 BYTES SIZ1 DSACK0 DSACK1 OP0 D15–D8 D7–D0 BYTE READ Figure 3-3. Long-Word Operand Read Timing from 8-Bit Port MOTOROLA BYTES 2 BYTES OP1 BYTE BYTE READ READ LONG-WORD OPERAND READ FROM 8-BIT BUS MC68341 USER’S MANUAL ...
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... OP1 (OP1) WRITE WRITE LONG-WORD OPERAND WRITE TO 8-BIT BUS OP0 OP1 OP2 OP3 SIZ1 OP0 OP1 0 OP2 OP3 1 MC68341 USER’S MANUAL BYTE OP2 OP3 (OP3) (OP3) WRITE 0 SIZ0 A0 DSACK1 DSACK0 MOTOROLA ...
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... DSACK1 to indicate reception and a 16-bit port. The MC68341 then decrements the transfer size counter by 2, increments the address by 2, and writes bytes 2 and 3 of the operand to bits 15–0 of the data bus. MOTOROLA ...
Page 66
... The timing parameters are described in Section 12 Electrical Characteristics system asserts DSACK≈ for the required window around the falling edge of S2 and obeys the proper bus protocol by maintaining DSACK≈ (and/or BERR /HALT) until and 3-16 DSACK¯ MC68341 USER’S MANUAL MOTOROLA ...
Page 67
... When using the fast termination option asserted only in a read cycle, not in a write cycle. S0 CLKOUT AS DS UWE, LWE R/W DSACKx D15–D0 DTC * DSACKx only internally asserted for fast termination cycles. Figure 3-6. Fast Termination Timing MOTOROLA * * TWO WAIT STATES IN READ TERMINATION MC68341 USER’ ...
Page 68
... A0, and the port size. Refer to 3.3.1 Dynamic Bus Sizing and 3.3.2 Misaligned Operands for more information. Figure 3 flowchart of a word read cycle. Figure 3 example of a functional timing diagram of a read bus cycle specified in terms of clock periods. 3-18 MC68341 USER’S MANUAL MOTOROLA ...
Page 69
... R/W, SIZ1 and SIZ0, and FC3–FC0 also remain valid throughout S5. The external device keeps its data and DSACK≈ signals asserted until it detects the negation (whichever it detects first). The device must remove its data and MOTOROLA 1. DECODE ADDRESS 2. PLACE DATA ON D15–D0 3 ...
Page 70
... A31– FC3–FC0 SIZ1 SIZ0 R/W AS CSx DS AS68K UDS, LDS UWE, LWE DSACK DTC D15–D8 D7–D0 WORD READ 3- BYTE WORD OP2 OP3 BYTE READ Figure 3-8. Read Cycle Timing MC68341 USER’S MANUAL OP3 OP3 BYTE READ MOTOROLA ...
Page 71
... State 3—If DSACK≈ is not recognized by the start of state 3 (S3), the MC68341 inserts wait states instead of proceeding to states 4 and 5. To ensure that wait states are inserted, both DSACK1 and DSACK0 must remain negated throughout the asynchronous MOTOROLA 1. DECODE ADDRESS 2. PLACE DATA ON D15–D0 3 ...
Page 72
... AS68K or UDS/LDS (whichever it detects first). The device must remove its data and negate DSACK≈ within approximately one clock period after sensing the negation of AS68K or UDS/LDS . DSACK≈ signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. 3-22 MC68341 USER’S MANUAL MOTOROLA ...
Page 73
... Figure 3-10. 68000 Read Cycle Timing 3.4.3 M68300 Write Cycle During a write cycle, the MC68341 transfers data to memory or a peripheral device. Figure 3- flowchart of a word write cycle. Figure 3- example of a functional timing diagram of a write bus cycle specified in terms of clock periods. MOTOROLA BYTE ...
Page 74
... S5. It holds the address and data valid during S5 to provide address hold time for memory systems. R/W, SIZ1/SIZ0, and FC3–FC0 also remain valid throughout S5. The 3-24 1. DECODE ADDRESS 2. LATCH DATA FROM D15–D0 3. ASSERT DSACKx SIGNALS TERMINATE CYCLE 1. NEGATE DSACKx MC68341 USER’S MANUAL SLAVE ACCEPT DATA MOTOROLA ...
Page 75
... FC3–FC0 SIZ1 SIZ0 R/W AS CSx DS AS68K UDS, LDS UWE LWE DSACK DTC D15–D8 D7–D0 WORD WRITE Figure 3-12. M68300 Write Cycle Timing MOTOROLA BYTE WORD OP2 OP3 BYTE WRITE MC68341 USER’S MANUAL OP3 OP3 BYTE WRITE 3- 25 ...
Page 76
... If DSACK≈ is not recognized by the start of S3, the MC68341 inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are 3-26 1. DECODE ADDRESS 2. LATCH DATA FROM D15–D0 3. ASSERT DSACKx SIGNALS TERMINATE CYCLE 1. NEGATE DSACKx MC68341 USER’S MANUAL SLAVE ACCEPT DATA MOTOROLA ...
Page 77
... AS68K or UDS/LDS (whichever it detects first). The device must negate DSACK≈ within approximately one clock period after sensing the negation of AS68K or UDS/LDS . DSACK≈ signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. MOTOROLA MC68341 USER’S MANUAL 3- 27 ...
Page 78
... FC3–FC0 SIZ1 SIZ0 R/W AS68K CSx DS AS UDS LDS UWE LWE DSACK DTC D15–D8 D7–D0 WORD WRITE Figure 3-14. 68000 Write Cycle Timing 3- WORD OP2 OP3 BYTE WRITE MC68341 USER’S MANUAL BYTE OP3 OP3 BYTE WRITE MOTOROLA ...
Page 79
... SIZ1/SIZ0 become valid indicate the operand size. The MC68341 drives R/W high for the read cycle. State 1—One-half clock later during S1, the MC68341 asserts A S indicating a valid address on the address bus. The MC68341 also asserts DS during S1. MOTOROLA ...
Page 80
... R/W, DS, SIZ1/SIZ0, and A0 to latch data from the appropriate section(s) of D15–D8 and D7–D0. SIZ1/SIZ0 and A0 select the data bus sections has not already done so, the device asserts DSACK≈ when it has successfully stored the data. 3-30 MC68341 USER’S MANUAL MOTOROLA ...
Page 81
... CPU space. The CPU space type, which is encoded on A19–A16 during a CPU space operation, indicates the function that the MC68341 is performing. On the MC68341, four of the encodings are implemented as shown in Figure 3-16. All unused values are reserved by Motorola for additional CPU space types. FUNCTION ...
Page 82
... I2–I0—Interrupt Mask Level The interrupt mask level is encoded on bits 2–0 of the data bus during an LPSTOP broadcast. 3-32 NOTE — — — — — MC68341 USER’S MANUAL — — — MOTOROLA 0 I0 ...
Page 83
... CONTINUE PROCESSING IF BREAKPOINT INSTRUCTION EXECUTED: 1. INITIATE ILLEGAL INSTRUCTION PROCESSING IF BKPT PIN ASSERTED: 1. INITIATE HARDWARE BREAKPOINT PROCESSING Figure 3-17. Breakpoint Operation Flowchart MOTOROLA IF BREAKPOINT INSTRUCTION EXECUTED: 1. PLACE REPLACEMENT OPCODE ON DATA BUS 2. ASSERT DSACKx 1. ASSERT BERR TO INITIATE EXCEPTION PROCESSING IF BKPT PIN ASSERTED: 1. ASSERT DSACKx 1 ...
Page 84
... D15–D8 BERR HALT BKPT BREAKPOINT OCCURS Figure 3-18. Breakpoint Acknowledge Cycle Timing (Opcode Returned) 3- BREAKPOINT ENCODING (0000) BREAKPOINT NUMBER/T-BIT READ MC68341 USER’S MANUAL CPU SPACE FETCHED INSTRUCTION EXECUTION BREAKPOINT ACKNOWLEDGE INSTRUCTION WORD FETCH MOTOROLA S0 ...
Page 85
... A15–A5, A0 FC3–FC0 SIZ0 SIZ1 AS DS R/W DSACKx D7–D0 D15–D8 BERR HALT BKPT BREAKPOINT OCCURS Figure 3-19. Breakpoint Acknowledge Cycle Timing (Exception Signaled) MOTOROLA BREAKPOINT ENCODING (0000) BREAKPOINT NUMBER/T-BIT READ MC68341 USER’S MANUAL ...
Page 86
... The following paragraphs describe the interrupt acknowledge cycle for these devices. Other interrupting conditions or devices that cannot supply a vector number will use the autovector cycle described in 3.5.4.2 Autovector Interrupt Acknowledge Cycle. 3-36 MC68341 USER’S MANUAL MOTOROLA ...
Page 87
... SIGNIFICANT BYTE OF DATA BUS 2. ASSERT DSACKx (OR AVEC IF NO VECTOR NUMBER) RELEASE 1. NEGATE DSACKx Figure 3-20. Interrupt Acknowledge Cycle Flowchart MOTOROLA 1. SYNCHRONIZE IRQ7–IRQ1 2. COMPARE IRQ1–IRQ7 TO MASK LEVEL AND WAIT FOR INSTRUCTION TO COMPLETE 3. PLACE INTERRUPT LEVEL ON A3–A1; TYPE FIELD (A19–A16 SET R/W TO READ 5. SET FC3– ...
Page 88
... AVEC, the DSACK≈ signals and data 3- 0–2 CLOCKS INTERRUPT LEVEL CPU SPACE 1 BYTE VECTOR FROM 16-BIT PORT VECTOR FROM 8-BIT PORT INTERNAL ARBITRATION IACK CYCLE MC68341 USER’S MANUAL WRITE STACK MOTOROLA ...
Page 89
... AVEC or DSACK≈ bus monitor must assert BERR , which results in the CPU32 taking the spurious interrupt vector. If HALT is also asserted, the MC68341 retries the interrupt acknowledge cycle instead of using the spurious interrupt vector. MOTOROLA MC68341 USER’S MANUAL 3- 39 ...
Page 90
... D15–D0 AVEC IRQ7–IRQ1 IACK7–IACK1 CYCLE READ * Internal Arbitration may take between 0–2 clocks. Figure 3-22 Autovector Operation Timing 3- 0–2 CLOCKS* INTERRUPT LEVEL CPU SPACE 1 BYTE INTERNAL ARBITRATION IACK CYCLE MC68341 USER’S MANUAL WRITE STACK MOTOROLA ...
Page 91
... BERR , and HALT may be negated after DSACK≈ or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely. EXAMPLE A: A system uses a bus monitor timer to terminate accesses to an unpopulated address space. The timer asserts BERR after timeout (case 3). MOTOROLA MC68341 USER’S MANUAL 3- 41 ...
Page 92
... Terminate and take bus error exception possibly deferred Terminate and take bus error exception possibly deferred Terminate and retry when HALT negated Terminate and retry when HALT negated MC68341 USER’S MANUAL Assertion Results Result MOTOROLA ...
Page 93
... BERR has priority over DSACK≈. In this case, data may be present on the bus, but it may not be valid. This sequence can be used by systems that have memory error detection and correction logic and by external cache memories. MOTOROLA MC68341 USER’S MANUAL 3- 43 ...
Page 94
... S0 S2 CLKOUT A31–A0 FC3–FC0 R DSACKx BERR DTC D15–D0 READ CYCLE WITH BUS Figure 3-23. Bus Error without 3- INTERNAL ERROR PROCESSING DSACK¯ MC68341 USER’S MANUAL STACK WRITE MOTOROLA ...
Page 95
... BERR and HALT signals are negated by external logic. After a synchronization delay, the MC68341 retries the previous cycle using the same access information (address, function code, size, etc.). BERR should be negated before S2 of the retried cycle to ensure correct operation of the retried cycle. MOTOROLA ...
Page 96
... BR ( HALT must not be included). The bus error handler software should examine the read-modify-write bit in the special status word (see Section 5 CPU32) and take the appropriate action to resolve this type of fault when it occurs. 3- DATA IGNORED HALT RETRY Figure 3-25. Retry Sequence MC68341 USER’S MANUAL READ RERUN MOTOROLA ...
Page 97
... A31–A0, FCx, SIZx, and R/W signals remain in the same state. The halt operation has no effect on bus arbitration (see 3.7 Bus Arbitration). When bus arbitration occurs while the MC68341 is halted, the address and control signals are also placed in the high- impedance state. Once bus mastership is returned to the MC68341, if HALT is still MOTOROLA S2 S4 WRITE ...
Page 98
... For example, the MC68341 attempts to stack several words containing information about the state of the machine while processing a bus error exception bus error exception 3- READ HALT (ARBITRATION PERMITTED WHILE THE PROCESSOR IS HALTED) HALT Figure 3-27. Timing MC68341 USER’S MANUAL READ MOTOROLA ...
Page 99
... The following conditions must be met for an external device to assume mastership of the bus through the normal bus arbitration procedure must have received BG through the arbitration process, and 2) BGACK must be inactive, indicating that no other bus master has claimed ownership of the bus. MOTOROLA NOTE MC68341 USER’S MANUAL 3- 49 ...
Page 100
... NEXT BUS MASTER WAITS FOR BGACK TO BE NEGATED 3. NEXT BUS MASTER ASSERTS BGACK TO BECOME NEW MASTER 4. BUS MASTER NEGATES BR OPERATE AS BUS MASTER 1. PERFORM DATA TRANSFERS (READ AND WRITE CYCLES) ACCORDING TO THE SAME RULES THE PROCESSOR USES RELEASE BUS MASTERSHIP 1. NEGATE BGACK MC68341 USER’S MANUAL MOTOROLA ...
Page 101
... A31–A0 D15– BGACK Figure 3-29. Bus Arbitration Timing Diagram—Idle Bus Case S0 S1 CLKOUT A31–A0 D15– R/W DSACK0, DSACK1 BR BG BGACK Figure 3-30. Bus Arbitration Timing Diagram—Active Bus Case MOTOROLA MC68341 USER’S MANUAL 3- 51 ...
Page 102
... Bus mastership is terminated at the negation of BGACK. Once an external device receives the bus and asserts BGACK , it should negate BR remains asserted after BGACK is asserted, the MC68341 assumes that another device is requesting the bus and prepares to issue another BG . 3-52 MC68341 USER’S MANUAL MOTOROLA ...
Page 103
... The following paragraphs are a state-by-state description of show cycles, and Figure 3-32 illustrates a show cycle timing diagram. Refer to Section 12 Electrical Characteristics for specific timing information. MOTOROLA MC68341 USER’S MANUAL 3- 53 ...
Page 104
... B - BUS CYCLE IN PROGRESS Figure 3-31. Bus Arbitration State Diagram 3- STATE STATE STATE BUS GRANT T - THREE-STATE SIGNAL TO BUS CONTROL V - BUS AVAILABLE TO BUS CONTROL MC68341 USER’S MANUAL STATE MOTOROLA R A ...
Page 105
... The reset control logic can independently drive three different lines: 1. EXTRST (external reset) drives the external RESET pin. 2. CLKRST (clock reset) resets the clock module. 3. INTRST (internal reset) goes to all other internal circuits. MOTOROLA S0 S41 S42 S43 SHOW CYCLE MC68341 USER’ ...
Page 106
... RESET negates, all control signals are driven to their inactive state, the data bus is in read mode, and the address bus is driven. After this, the first bus cycle for RESET exception processing begins. 3-56 1 CLOCK 590 CLOCK PULLED EXTERNAL DRIVEN BY MC68340 MC68341 USER’S MANUAL 512 CLOCK RESET MOTOROLA ...
Page 107
... The SIM41 registers and the module control registers in each internal peripheral module (DMA, timers, and serial modules) are not affected. All other peripheral module registers are reset the same as for a hardware reset. The external devices connected to the RESET signal are reset at the completion of the RESET instruction. MOTOROLA 512 14 CLOCKS TCLKOUT ...
Page 108
... The programmable chip select function provides eight chip select signals that can enable external memory and peripheral circuits, providing all handshaking and timing signals. Each chip select signal has an associated base address register and an address mask register that contain the programmable characteristics of that chip select six wait MOTOROLA MC68341 USER’S MANUAL 4- 1 ...
Page 109
... MBAR using the MOVES instruction to address $0003FF00 in CPU space. The source function code (SFC) and destination function code (DFC) registers contain the address space values (FC3–FC0) for the read or write operand of the MOVES 4-2 NOTE MC68341 USER’S MANUAL MOTOROLA ...
Page 110
... The SIM41 allows the user to configure the system to the particular requirements. The functions include control of FREEZE and show cycle operation, the function of the CS≈ signals, the access privilege of the supervisor/user registers, the level of interrupt arbitration, and automatic vectoring for external interrupts. MOTOROLA $FFFFFFFF $XXXXXFFF $XXXXX000 $00000000 MC68341 USER’ ...
Page 111
... The SIM41 provides a timer to generate periodic interrupts. The periodic interrupt time period can vary from 122 s to 15.94 s (with a 32.768-kHz crystal used to generate the system clock). This function can be disabled. Figure 4-2 shows a block diagram of the system configuration and protection function. 4-4 MC68341 USER’S MANUAL MOTOROLA ...
Page 112
... IARB value. The IARB must contain a value other than $0 for all modules that can generate interrupts; interrupts with IARB = 0 are discarded as extraneous. The SIM41 arbitrates for both its own interrupts and externally generated interrupts. MOTOROLA MODULE CONFIGURATION RESET ...
Page 113
... Once enabled by the SWE bit in the SYPCR, the software watchdog requires a special service sequence to be executed on a periodic basis. If this periodic servicing action does not occur, the software watchdog times out and issues a reset or a level 7 4-6 MC68341 USER’S MANUAL MOTOROLA ...
Page 114
... The value of bits 7–0 in the PITR is then loaded again into the modulus counter, and the counting process starts over new value is written to the PITR, this value is loaded into the modulus counter when the current count is completed. MOTOROLA PITCLK . ...
Page 115
... With prescaler enabled: programmable interrupt timer period 4-8 PITR count value = EXTAL (or EXTCLK) frequency/prescaler value PITR count value = = PITR count value PITR count value = = PITR count value = PITR (122 s) = PITR (62.5 ms) MC68341 USER’S MANUAL 2 2 32768 8192 32768/512 MOTOROLA ...
Page 116
... PLL and VCO, using a parallel resonant crystal connected between the EXTAL and XTAL pins. An external oscillator can also be connected to EXTCLK as a reference frequency source, as shown in Figure 4-5. A 32.768-kHz watch crystal provides an inexpensive reference, but the reference crystal or external oscillator MOTOROLA = (PIT period) (EXTAL (or EXTCLK) frequency) (Prescaler value ...
Page 117
... V CCSYN CC should be a quiet power supply with adequate external MC68341 USER’S MANUAL V CCSYN 1 0.1 F XFC V 0.01 F CCSYN MUX MUX SEL SEL used. If BSW is asserted, V pin to ensure a stable CCSYN MOTOROLA Z is BAT ...
Page 118
... VCO running at approximately one-half the operating speed (affected by the value of the X-bit in the SYNCR), using an internal voltage reference. The SLIMP bit in the SYNCR indicates that a loss of input MOTOROLA held while the chip is in operation. CCSYN ...
Page 119
... VCO frequency limits are given in Section 12 Electrical Characteristics. Table 4-2 lists some frequencies available from various combinations of SYNCR bits with a reference frequency of 32.768-KHz. 4-12 pins. The XFC capacitor should CCSYN ( 2W+X+3Z– (Y+1) CRYSTAL (4+2W) [( (Y+ SYSTEM MC68341 USER’S MANUAL (5–X–3Z MOTOROLA ...
Page 120
... MOTOROLA VCO 1 1 (kHz 131 262 524 66 262 524 1049 131 393 786 1573 197 524 ...
Page 121
... MOTOROLA ...
Page 122
... The address mask register specifies the size of the address block range. The base address register V-bit indicates that the register information for that chip select is valid. A global chip select (CS0 ) allows address decode for a boot ROM before system initialization occurs. MOTOROLA Table 4-3. Clock Control Signals Control Bits Clock Outputs ...
Page 123
... While CS0 is a global chip select, no other chip select (CS7–CS1) can be used. CS0 operates in this manner until the V-bit is set in the CS0 base address register, which will then allow the use of CS7–CS1. Provided 4-16 NOTE MC68341 USER’S MANUAL MOTOROLA ...
Page 124
... A25 A24 4.2.5.2 PORT B. Port B pins can be independently programmed to function as IRQ≈ or discrete I/O pins. Selection of a pin function is accomplished by the port B pin assignment register (PPARB). See Table 4-6 for port B selections. By changing the value of the MOTOROLA Pin Function Signal AVEC Bit = 0 AVEC Bit = 1 ...
Page 125
... CPU32 or until reset. For more information, see the description of the MCR STP bit for each module. 4-18 Pin Function Signal PPARB = 0 PPARB = 1 PORTB7 IRQ7 PORTB6 IRQ6 PORTB5 IRQ5 PORTB4 IRQ4 PORTB3 IRQ3 PORTB2 IRQ2 PORTB1 IRQ1 PORTB0 MODCK IRQ0 NOTE MC68341 USER’S MANUAL IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 MOTOROLA ...
Page 126
... The second line contains the mnemonic for the bit. The numbers below the register represent the bit values after a hardware reset. The access privilege is indicated in the lower right-hand corner. A CPU32 RESET instruction will not affect any of the SIM41 registers. MOTOROLA NOTE: MC68341 USER’S MANUAL 4- 19 ...
Page 127
... CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT CHIP SELECT MOTOROLA ...
Page 128
... MINUTES ALARM (MINA) 0CA S/U DATE ALARM (DATEA) 0CE S/U RESERVED FF S Figure 4-8. SIM41 Programming Model (Continued) MOTOROLA ADDRESS MASK 1 CS5 ADDRESS MASK 2 CS5 BASE ADDRESS 1 CS5 BASE ADDRESS 2 CS5 ADDRESS MASK 1 CS6 ADDRESS MASK 2 CS6 BASE ADDRESS 1 CS6 BASE ADDRESS 2 CS6 ADDRESS MASK 1 CS7 ...
Page 129
... The module block is not accessed. The address space bits are as follows: AS8—mask DMA Space AS7—mask CPU Space AS6—mask Supervisor Program AS5—mask Supervisor Data AS4—mask Reserved [Motorola] AS3—mask Reserved [User] AS2—mask User Program AS1—mask User Data AS0—mask Reserved [Motorola] For each address space bit Mask this address space from the internal module selection ...
Page 130
... When FREEZE is asserted, the software watchdog and periodic interrupt timer counters continue to run. See 4.2.7 Freeze for more information. MOTOROLA NOTE load D0 with the CPU space function code load SFC to indicate CPU space ...
Page 131
... SIM41 interrupts, including external interrupts discarded as extraneous. 4-24 Table 4-7. SHENx Control Bits ACTION 0 Show cycle s disabled, external arbitration enabled 1 Show cycles enabled, external arbitration disabled X Show cycles enabled, external arbitration enabled MC68341 USER’S MANUAL MOTOROLA ...
Page 132
... The last reset was caused by the double bus fault monitor. Bits 3, 0—Reserved LOC—Loss of Clock Reset 1 = The last reset was caused by a loss of frequency reference to the clock synthesizer. This reset can only occur if the RSTEN bit in the SYNCR is set and the VCO is enabled. MOTOROLA ...
Page 133
... SWIV6 SWIV5 SWIV4 SWIV3 SWIV2 Supervisor Only SWRI SWT1 SWT0 DBFE BME Supervisor Only divide count EXTAL frequency MC68341 USER’S MANUAL $020 1 0 SWIV1 SWIV0 1 1 $021 1 0 BMT1 BMT0 0 0 MOTOROLA ...
Page 134
... For more information see 4.2.2.2 Internal Bus Monitor. BMT1, BMT0—Bus Monitor Timing These bits select the timeout period for the bus monitor (see Table 4-9). Upon reset, the bus monitor is set to 512 system clocks. BMT1 MOTOROLA Software Timeout Period Crystal Period 9 2 /EXTAL Input Frequency ...
Page 135
... Interrupt Request Level Interrupt Request Level Interrupt Request Level Interrupt Request Level Interrupt Request Level Interrupt Request Level 7 NOTE: MC68341 USER’S MANUAL PIV5 PIV4 PIV3 PIV2 PIV1 Supervisor Only MOTOROLA $022 0 PIV0 1 ...
Page 136
... SWSR7 SWSR6 SWSR5 SWSR4 SWSR3 SWSR2 SWSR1 SWSR0 RESET: 0 4.3.3 Clock Synthesizer Control Register (SYNCR) The SYNCR can be read or written only in supervisor mode. The reset state of SYNCR produces an operating frequency of 8.39 MHz when the PLL is referenced to a 32.768- MOTOROLA SWP ...
Page 137
... X-bit ), determined from an internal voltage reference External input signal frequency is at VCO reference. 4-30 (2W+X+3Z– CRYSTAL MC68341 USER’S MANUAL ] (Y+1) $004 SLIMP SLOCK RSTEN STSIM Supervisor Only MOTOROLA 0 STEXT 0 ...
Page 138
... BA31–BA8—Base Address Bits 31–8 The base address field, the upper 24 bits of each base address register, selects the starting address for the chip select. The specified base address must multiple of MOTOROLA $044, $04C, $054, $05C, $064, $06C, $074, $07C 26 ...
Page 139
... A reset clears the V-bit in each base address register, but does not change any other bits in the base address and address mask registers (CS0 is a special case, see 4.2.4.2 Global Chip Select Operation Contents are valid Contents are not valid. 4-32 MC68341 USER’S MANUAL MOTOROLA ...
Page 140
... The port size field must be programmed for an internal DSACK≈ response for the DDx bits to have significance. If external DSACK≈ signals are returned earlier than indicated by the DDx and EDS bits, the cycle will terminate sooner than programmed. MOTOROLA $040, $048, $050, $058, $060, $068, $070, $078 ...
Page 141
... BSR7 BSR6 MC68341 USER’S MANUAL Cycle Duration Three Clocks Four Clocks Five Clocks Six Clocks Seven Clocks Eight Clocks Nine Clocks Two Clocks BSR5 BSR4 BSR3 BSR2 BSR1 Supervisor Only MOTOROLA $03C 0 BSR0 0 ...
Page 142
... The following paragraphs describe the registers that control the I/O pins used with the EBI. Refer to the Section 3 Bus Operation for more information about the EBI. For a list of pin numbers used with port A and port B, see the pinout diagram in Section 13 MOTOROLA ...
Page 143
... Supervisor Only IACK6 IACK5 IACK4 IACK3 IACK2 (A30) (A29) (A28) (A27) (A26 Supervisor Only MC68341 USER’S MANUAL $015 1 0 PRTA1 PRTA0 (A25) (A24 $017 1 0 IACK1 0 (A25 MOTOROLA ...
Page 144
... I/O. Any set bit configures the corresponding pin as an output; any cleared bit configures the corresponding pin as an input. This register affects only pins configured as discrete I/O. This register can be read or written at any time. DDRB 7 DD7 RESET: 0 MOTOROLA DD6 DD5 DD4 ...
Page 145
... RESET is asserted, the following occurs: 4- Supervisor/User TGATE DACK2 DACK1 FC3 RMC RTCOUT RDY1 DDACK2 DDACK1 DTC Supervisor Only MC68341 USER’S MANUAL $019, 01B $029 MOTOROLA ...
Page 146
... RIV7–RIV0—RTC Interrupt Vector Bits 7–0 These bits contain the value of the vector generated during an IACK cycle in response to an interrupt from the RTC alarm. When the SIM41 responds to an IACK cycle, the RTC interrupt vector is placed on the bus. MOTOROLA ...
Page 147
... Alarm indicator bit cannot assert. Clearing this bit clears the alarm condition and negates RTCOUT if programmed as an alarm indicator. RCK_HT—RTC Clock Halt 1 = RTC clock is stopped 0 = RTC clock runs. 4- ALARM ERRMUX ROS1 ROS0 AIE Supervisor Only MC68341 USER’S MANUAL $0C8 1 0 RCK_HT SET 0 0 32) MOTOROLA ...
Page 148
... Each calibration step has the effect of adding or subtracting 128 oscillator cycles every 117,964,800 (32768Hz 60 sec/min calibration step. The 31 steps positive and negative support a total crystal frequency adjustment range of 33.6 PPM. MOTOROLA ...
Page 149
... MIN2 User—Read Only Supervisor—Read and Write SEC6 SEC5 SEC4 SEC3 SEC2 User—Read Only Supervisor—Read and Write MC68341 USER’S MANUAL $0C2 1 0 MIN1 MIN0 U U $0C3 1 0 SEC1 SEC0 U U MOTOROLA ...
Page 150
... U YEAR 7 YR7 RESET: U DAY 7 0 RESET: U The day of the week counter is a 3-bit count-up counter with a range from The user defines the set value and day-of-week definition for the counter. MOTOROLA DATE5 DATE4 DATE3 DATE2 ...
Page 151
... HOUR5 HOUR4 HOUR3 HOUR2 User—Read Only Supervisor—Read and Write MC68341 USER’S MANUAL $0CA 1 0 MIN1 MIN0 U U $0CB 1 0 SEC1 SEC0 U U $0CC 1 0 DATE1 DATE0 U U $0CD 1 0 HOUR1 HOUR0 U U MOTOROLA ...
Page 152
... Figure 4- timing diagram of the power down operation, showing the relationships between CLKOUT, and BSW. BSW must be asserted at least three system clock cycles before V CC has reached the minimum spec operating voltage. CLKOUT V CC MOTOROLA Table 4-14 Alarm Bit Setting DATEA 1 Alarm once per second ...
Page 153
... Select the access privilege for the supervisor/user registers (SUPV bit). • Select the interrupt arbitration level for the SIM41 (IARBx bits). Autovector Register (AVR) • Select the desired external interrupt levels for internal autovectoring. 4-46 MC68341 USER’S MANUAL is ramping up, the VCO CC MOTOROLA ...
Page 154
... V-bit in the base address register before CS7 –CS1 can be used. Port A and B Registers • Program the desired function of the port A signals (PPARA1 and PPARA2 registers). • Program the desired function of the port B signals (PPARB register). MOTOROLA MC68341 USER’S MANUAL 4- 47 ...
Page 155
... Address of Module Base Address Reg. Default Module Base address value Supervisor stack pointer - initial value Reset vector pointing to init code Init SR - interrupts masked MBAR is in CPU space Load DFC to indicate CPU space Allow DMA, supervisor/user data accesses Write to MBAR MC68341 USER’S MANUAL MOTOROLA ...
Page 156
... CS4$ DC.L $0,$0 CS5$ DC.L $0,$0 CS6$ DC.L $0,$0 CS7$ DC.L $0,$0 *************************************************************************** END MOTOROLA X-bit doubles the default speed Point to CS0 addr. mask location. Set up loop counter for 2 regs * 4 CSx Point to init table location. Init. addr mask and base addr reg MC68341 USER’S MANUAL 4- 49 ...
Page 157
... As processor applications become more complex and programs become larger, high-level languages (HLLs) will become the system designer's choice in programming languages. HLLs aid in the rapid development of complex algorithms with less error and are readily portable. The CPU32 instruction set efficiently supports HLLs. MOTOROLA MC68341 USER’S MANUAL 5- 1 ...
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... When the processor attempts to access a location in the virtual memory map that is not resident in physical memory, a page fault occurs. The access to that location is temporarily suspended while the necessary data is fetched from secondary storage and placed in physical memory. The 5-2 MC68341 USER’S MANUAL MOTOROLA ...
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... Figure 5-2. Loop Mode Instruction Sequence The loop mode is entered when the DBcc instruction is executed and the loop displacement is –4. Once in loop mode, the processor performs only the data cycles associated with the instruction and suppresses all instruction fetches. The termination MOTOROLA CONTROL INSTRUCTION UNIT ...
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... To support generic handlers, the processor places the vector offset in the exception stack frame. The processor also marks the frame with a frame format. The format field allows the return-from-exception (RTE) instruction to identify what information is on the stack so that it may be properly restored. 5-4 VECTOR BASE REGISTER (VBR) MC68341 USER’S MANUAL 0 MOTOROLA ...
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... Separate User and Supervisor Stack Pointers (USP and SSP) • Separate User and Supervisor Address Spaces • Separate Program and Data Address Spaces • Many Data Types • Flexible Addressing Modes • Full Interrupt Processing • Expansion Capability MOTOROLA MC68341 USER’S MANUAL 5- 5 ...
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... Figure 5-3. User Programming Model 5 (USP CCR MC68341 USER’S MANUAL DATA REGISTERS ADDRESS REGISTERS USER STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER MOTOROLA ...
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... The CPU32 generates a function code each time it accesses an address. Specific codes are assigned to each type of access. The codes can be used to select eight dedicated 4-Gbyte address spaces. The MOVEC instruction can use registers SFC and DFC to specify the function code of a memory address. MOTOROLA (SSP) ...
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... PACK, UNPK — Pack, Unpack BCD Instructions 5 INTERRUPT PRIORITY MASK Figure 5-5. Status Register MC68341 USER’S MANUAL USER BYTE (CONDITION CODE REGISTER EXTEND NEGATIVE ZERO OVERFLOW CARRY MOTOROLA 0 C ...
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... The CPU32 traps on unimplemented instructions or illegal effective addressing modes, allowing user-supplied code to emulate unimplemented capabilities or to define special- purpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 core enhancements. Mnemonic Description ABCD Add Decimal with Extend ...
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... See 5.3.4 Using the TBL Instructions for examples. 5.3.1.2 UNIMPLEMENTED INSTRUCTIONS. The ability to trap on unimplemented instructions allows user-supplied code to emulate unimplemented capabilities or to define special-purpose functions. However, Motorola reserves the right to use all currently unimplemented instruction operation codes for future M68000 enhancements. See 5.5.2.8 Illegal or Unimplemented Instructions for more details. ...
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... Data registers, used in computation Dym, Dyn Data registers, table interpolation values Xn Index register [An] Address extension MOTOROLA OPERATION WORD SPECIAL OPERAND SPECIFIERS (IF ANY, ONE OR TWO WORDS) EXTENSION (IF ANY, ONE TO THREE WORDS) (IF ANY, ONE TO THREE WORDS) A register field of the instruction contains the number of the register ...
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... Arithmetic addition or postincrement – Arithmetic subtraction or predecrement / Arithmetic division or conjunction symbol Arithmetic multiplication = Equal to Not equal to > Greater than Greater than or equal to < Less than Less than or equal to Logical AND V Logical OR Logical exclusive OR ~ Invert; operand is logically complemented 5-12 MC68341 USER’S MANUAL MOTOROLA ...
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... Logic Shift and Rotate The complete range of instruction capabilities combined with the addressing modes described previously provide flexibility for program development. All CPU32 instructions are summarized in Table 5-2. MOTOROLA Bit Manipulation Binary-Coded Decimal Arithmetic Program Control System Control MC68341 USER’S MANUAL ...
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... ASd # data ,Dy ASd ea Bcc label BCHG Dn, ea BCHG # data ea BCLR Dn, ea BCLR # data ea BGND BKPT # data BRA label BSET Dn, ea BSET # data ea BSR label BTST Dn, ea BTST # data ea CHK ea ,Dn CHK2 ea ,Rn CLR ea CMP ea ,Dn CMPA ea ,An CMPI # data ea CMPM (Ay)+,(Ax)+ MOTOROLA ...
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... LPSTOP If supervisor state Immediate Data Interrupt Mask STOP else TRAP LSL,LSR Destination Shifted by count MOVE Source Destination MOVEA Source Destination MOVE from CCR Destination CCR MOTOROLA Operation Dn; PC) Destination Destination Destination Destination Destination CCR SR SR Destination (SSP); (SSP); (SSP (SP) ...
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... MULS MULS MULS.L ea ,Dh: MULU MULU MULU.L ea ,Dh: NBCD ea NEG ea NEGX ea NOP NOT ,Dn OR Dn, ea ORI # data , ea ORI # data ,CCR ORI # data ,SR PEA ea RESET ROd 1 Rx,Dy ROd 1 # data ,Dy ROd 1 ea MOTOROLA ...
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... SSP; Format/Offset SSP – 4 SSP (SSP); Vector Address TRAPcc If cc then TRAP TRAPV If V then TRAP TST Destination Tested UNLK An SP; (SP) NOTE direction MOTOROLA Operation Destination ROXd 1 Rx,Dy SP SP; (SP) PC; SP Destination SR; STOP Destination Destination Destination Destination Destination Register [15:0] Condition Codes ...
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... Dµ Rm Dµ Dµ R∂ D∂ Rm D∂ D∂ R∂ R∂ D∂ Rm D∂ D∂ Rµ Rµ – ... V Dm – Dµ (Dm – – r) MOTOROLA ...
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... EXG Rn, Rn LEA LINK An MOVE MOVEA MOVEM list list MOVEP Dn An An), Dn MOVEQ # data Dn PEA ea UNLK An MOTOROLA – Operand Size 16 – 16, 32 Source 16, 32 ...
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... A set of extended instructions provides multiprecision and mixed-size arithmetic. These instructions are add extended (ADDX), subtract extended (SUBX), sign extend (EXT), and negate binary with extend (NEGX). Refer to Table 5-5 for a summary of the integer arithmetic operations. 5-20 MC68341 USER’S MANUAL MOTOROLA ...
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... SUBA SUBI # data SUBQ # data SUBX Dn, Dn – (An), – (An) TBLS/TBLU Dym:Dyn, Dn TBLSN/TBLUN Dym:Dyn, Dn MOTOROLA Operand Size 8, 16, 32 Source + Destination 8, 16, 32 16, 32 Source + Destination ea 8, 16, 32 Immediate Data + Destination ea 8, 16, 32 Immediate Data + Destination 8, 16, 32 Source + Destination + X 8, 16, 32 ...
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... Immediate Data 8, 16, 32 Source Destination ea 8, 16, 32 Immediate Data 8, 16, 32 Destination 8, 16, 32 Source V Destination 8, 16 16, 32 Immediate Data V Destination 8, 16, 32 Source – set condition codes MC68341 USER’S MANUAL Operation Destination Destination Destination Destination Destination Destination Destination Destination Destination MOTOROLA ...
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... Table 5 summary of bit manipulation instructions. Table 5-8. Bit Manipulation Operations Operand Instruction Syntax BCHG Dn data BCLR Dn data BSET Dn data BTST Dn data MOTOROLA Operand Size 16, 32 ...
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... 16 – 4 SP; PC none Destination PC none SP – 4 SP; PC none Returns 16 (SP) PC none (SP) CCR none (SP) PC MC68341 USER’S MANUAL Operation Destination Destination Destination Operation PC PC; PC (SP (SP); destination PC SP SP; (SP) PC MOTOROLA ...
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... All of these instructions cause the processor to flush the instruction pipeline. Table 5-11 summarizes the instructions. The preceding list of condition tests also applies to the TRAPcc instruction. Refer to 5.3.3.10 Condition Tests for detailed information on condition codes. MOTOROLA LS — Low or same LT — Less than MI — Minus NE — ...
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... Immediate Data 16 Source CCR 16 CCR Destination 8 Immediate Data V CCR MC68341 USER’S MANUAL Operation SP; (SP) PC SR; STOP SR; interrupt mask EBI; – (SSP); – (SSP); (vector) PC (SSP); (SSP); (SSP); PC (SSP); (SSP); SR (SSP); PC CCR CCR CCR CCR CCR MOTOROLA ...
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... Example 1 (see Figure 5-7) demonstrates TBL for a 257-entry table, allowing up to 256 interpolation levels between entries. Example 2 (see Figure 5-8) reduces table length for the same data to four entries. Example 3 (see Figure 5-9) demonstrates use of an 8-bit independent variable with an instruction. MOTOROLA Table 5-12. Condition Tests Condition Encoding ...
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... All entries between these points fall on the line. Y 5-28 X-Value 128* 32768 162 41472 163 41728 164 41984 165 42240 192* 49152 16384 32768 49152 X INDEPENDENT VARIABLE Figure 5-7. Table Example 1 MC68341 USER’S MANUAL X 49152. Y-Value 1311 1659 1669 1679 1690 1966 65536 MOTOROLA ...
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... The table has been compressed to only five entries, but up to 256 levels of interpolation are allowed between entries. Y Extreme table compression with many levels of interpolation is possible only with highly linear functions. The table entries within the range of interest are listed in Table 5-14. MOTOROLA ...
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... The subroutine uses the data listed in Table 5-15, based on the function shown in Figure 5-9. 5-30 X-Value 2 512 3 786 LSR.W #6, [8:15 [0:7] = $8E = 142 (142 (1966 – 1311)) / 256 = 1674 MC68341 USER’S MANUAL Y-Value 1311 1966 MOTOROLA ...
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... Y The first column is the value passed to the subroutine, the second column is the value expected by the table instruction, and the third column is the result returned by the subroutine. MOTOROLA 2048 3072 1024 X INDEPENDENT VARIABLE Figure 5-9. Table Example 3 Table 5-15. 8-Bit Independent Variable Entries X X (Subroutine) ...
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... Dx [8:15 [0:7] = $D0 = 208 (208 (64 – 80)) / 256 = 67 0010 0000 . 0111 0000 TBL # 1 0011 1111 . 0111 0000 TBL# 2 0000 0001 . 0111 0000 TBL # 3 MC68341 USER’S MANUAL MOTOROLA ...
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... TBLSN ADD.L Dx, Dm ADD.L Dm, Dl ASR.L #8, Dl BCC.B L1 ADDQ.B # MOTOROLA TBL # 1 0010 0000 . TBL # 2 0011 1111 . TBL # 3 0000 0001 . 0010 0000 . 0011 1111 . 0000 0001 . 0110 0000 . 0010 0000 . 0111 0000 0011 1111 . 0111 0000 0000 0001 . 0111 0000 0110 0001 ...
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... This section describes the processing states of the CPU32. It includes a functional description of the bits in the supervisor portion of the SR and an overview of actions taken by the processor in response to exception conditions. 5-34 Copy entry number and fraction number Surface interpolation, with round Read just the result No round necessary Half round up MC68341 USER’S MANUAL MOTOROLA ...
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... SUPERVISOR PRIVILEGE LEVEL. If the S-bit in the SR is set, supervisor privilege level applies, and all instructions are executable. The bus cycles generated for instructions executed in supervisor level are normally classified as supervisor references, and the values of the function codes on FC2–FC0 refer to supervisor address spaces. MOTOROLA MC68341 USER’S MANUAL 5- 35 ...
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... An exception is a special condition that pre-empts normal processing. Exception processing is the transition from normal mode program execution to execution of a routine that deals with an exception. The following paragraphs discuss system resources related to exception handling, exception processing sequence, and specific features of individual exception processing routines. 5-36 MC68341 USER’S MANUAL MOTOROLA ...
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... MOTOROLA Vector Offset Hex Space 0 000 SP Reset: Initial Stack Pointer 4 004 SP Reset: Initial Program Counter 8 008 SD Bus Error 12 00C SD Address Error 16 010 SD Illegal Instruction ...
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... Next, current processor status is saved. An exception stack frame is created and placed on the supervisor stack. All stack frames contain copies of the SR and the PC for use by RTE. The type of exception and the context in which the exception occurs determine what other information is stored in the stack frame. 5-38 CAUTION MC68341 USER’S MANUAL MOTOROLA ...
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... Each exception has an assigned vector that points to an associated handler routine. Exception processing includes steps described in 5.5.1.2 Exception Processing Sequence, but does not include execution of handler routines, which is done in normal mode. MOTOROLA STATUS REGISTER PROGRAM COUNTER HIGH PROGRAM COUNTER LOW ...
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... Suspends processing (instruction or exception); saves internal context. Exception processing is a part of instruction execution. Exception processing begins before instruction execution. Exception processing begins when current instruction or previous exception processing is complete. MC68341 USER’S MANUAL Characteristics MOTOROLA ...
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... All other internal peripheral module registers are reset the same as for a hardware reset. The external devices connected to the RESET signal are reset at the completion of the RESET instruction. MOTOROLA MC68341 USER’S MANUAL 5- 41 ...
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... FETCH VECTOR # 1 PC PREFETCH 3 WORDS OTHERWISE BEGIN Figure 5-11. Reset Operation Flowchart 5-42 ENTRY T0,T1 $7 I2:I0 $0 VBR . BUS ERROR OTHERWISE (VECTOR # 0) BUS ERROR OTHERWISE (VECTOR # 1) BUS ERROR/ ADDRESS ERROR INSTRUCTION EXECUTION ASSERT HALT EXIT EXIT MC68341 USER’S MANUAL (DOUBLE BUS FAULT) MOTOROLA ...
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... Address error exception processing begins when the processor attempts to use information from the aborted bus cycle. If the aborted cycle is a data space access, exception processing begins when the processor attempts to use the data, except in the MOTOROLA MC68341 USER’S MANUAL 5- 43 ...
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... BERR , the processor performs illegal instruction exception processing. If the bus cycle is terminated by DSACK≈, the processor uses the data returned to replace the breakpoint in the instruction pipeline and begins execution of that instruction. See Section 3 Bus Operation for a description of CPU space operations. 5-44 MC68341 USER’S MANUAL MOTOROLA ...