XPC860PZP66D3 Motorola, XPC860PZP66D3 Datasheet

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... It particularly excels in both communications and networking systems. The PowerQUICC unit is referred to as the MPC860 in this manual. The MPC860 is a derivative of Motorola’s MC68360 Quad Integrated Communications Controller (QUICC implements the PowerPC architecture. The CPU on the MPC860 is a 32-bit ...

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... MPC860 Family Hardware Specifications Ethernet ATM SCC 10T 10/100 — — yes yes — — — yes yes yes yes 1 1 Ref. 1 1,2,3 1,2,3 1 1,2 1,2,3 1,2,3 4 MOTOROLA ...

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... Gate mode can enable/disable counting — Interrupt can be masked on reference match and event capture • System integration unit (SIU) — Bus monitor — Software watchdog — Periodic interrupt timer (PIT) — Low-power stop mode — Clock synthesizer MOTOROLA MPC860 Family Hardware Specifications Features 3 ...

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... Communication-specific commands (for example, , and ENTER HUNT MODE RESTART TRANSMIT — Supports continuous mode transmission and reception on all serial channels — 8Kbytes of dual-port RAM — 16 serial DMA (SDMA) channels 4 MPC860 Family Hardware Specifications , GRACEFUL STOP TRANSMIT ) MOTOROLA ...

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... Multiple-master environment support • Time-slot assigner (TSA) — Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation — Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user defined — 8-bit resolution MOTOROLA MPC860 Family Hardware Specifications Features 5 ...

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... Reliability of operation is enhanced, if unused inputs are tied to an appropriate logic voltage level (for example, either GND MPC860 Family Hardware Specifications ). MOTOROLA ...

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... Air Flow (200 ft/min) 1 Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. MOTOROLA MPC860 Family Hardware Specifications Thermal Characteristics Symbol Value V – ...

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... MPC860 Family Hardware Specifications ) Typical Maximum Unit 450 550 mW 700 850 mW 870 1050 mW 375 TBD mW 575 TBD mW 750 TBD mW 656 735 mW TBD TBD mW 722 762 mW 851 909 mW NOTE -based power dissipation DDL . I/O power DDH MOTOROLA ...

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... V (Except XTAL, XFC, and Open DDH Drain Pins) Output Low Voltage IOL = 2.0 mA, CLKOUT 2 IOL = 3 IOL = 5.3 mA IOL = 7.0 mA, TXD1/PA14, TXD2/PA12 IOL = 8.9 mA, TS, TA, TEA, BI, BB, HRESET, SRESET 1 Input capacitance is periodically sampled. MOTOROLA MPC860 Family Hardware Specifications DC Characteristics Symbol Min VDDSYN 3.0 DDH DDL KAPWR 2.0 (power-down mode) ...

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... Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance θ JA θ JC θ MPC860 Family Hardware Specifications × PI/O, where PI/O is the power °C can be obtained from the equation: J – MOTOROLA ...

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... Board Temperature Rise Above Ambient Divided by Package Power Board Temperture Rise Above Ambient Divided by Package Figure 7-1. Effect of Board Temperature Rise on Thermal Behavior MOTOROLA MPC860 Family Hardware Specifications Estimation with Junction-to-Board Thermal Resistance . For instance, the user θ ...

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... A small amount of epoxy is placed over the thermocouple junction and over about wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 12 MPC860 Family Hardware Specifications ) can be used to determine the JT MOTOROLA ...

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... Table 9-6 provides the bus operation timing for the MPC860 at 33, 40, 50, and 66 MHz. The maximum bus speed supported by the MPC860 is 66 MHz. Higher-speed parts must be operated in half-speed bus mode (for example, an MPC860 used at 80 MHz must be configured for a 40 MHz bus). MOTOROLA MPC860 Family Hardware Specifications (415) 964-5111 800-854-7179 or 303-397-7956 http://www ...

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... MHz Unit Min Max 30.30 ns 0.90 ns 2.30 ns 0.60 ns 2.00 ns — 0.50 % — 2.00 % — 3.00 % — 0.50 % 6.06 — ns 6.06 — ns — 4.00 ns — 4.00 ns 3.80 — ns 3.80 — ns 3.80 — ns 3.80 10.04 ns 3.80 10.04 ns 3.80 10.04 ns 3.80 10.04 ns MOTOROLA ...

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... CLKOUT rising edge to CS asserted 7.58 GPCM ACS = 00 B22a CLKOUT falling edge to CS asserted GPCM ACS = 10, TRLX = 0 B22b CLKOUT falling edge to CS asserted 7.58 GPCM ACS = 11, TRLX = 0, EBDF = 0 MOTOROLA MPC860 Family Hardware Specifications Bus Signal Timing 33 MHz 40 MHz 50 MHz Min Max Min ...

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... MHz Unit Min Max 5.18 12.31 ns 2.00 8.00 ns 1.79 — ns 5.58 — ns — 9.00 ns 2.00 9.00 ns — ns — ns — 9.00 ns 3.80 10.54 ns — 10.54 ns 5.18 12.31 ns — 12.31 ns 1.79 — ns 5.58 — ns MOTOROLA ...

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... ACS = 10, or ACS = 11, EBDF = 0 B30b WE(0:3) negated to A(0:31), 43.45 invalid GPCM BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A(0:31), Invalid GPCM, write access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11, EBDF = 0 MOTOROLA MPC860 Family Hardware Specifications Bus Signal Timing 33 MHz 40 MHz 50 MHz Min Max Min ...

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... BST1 in the corresponding word in UPM, EBDF = 1 18 MPC860 Family Hardware Specifications 33 MHz 40 MHz 50 MHz Min Max Min Max Min Max — 6.38 — 4.50 — — 31.38 — 24.50 — 17.83 6.00 1.50 6.00 1.50 6.00 14.33 6.25 13.00 5.00 11.75 8.00 1.50 8.00 1.50 8.00 14.33 6.25 13.00 5.00 11.75 17.99 11.28 16.00 9.40 14.13 6.00 1.50 6.00 1.50 6.00 14.33 6.25 13.00 5.00 11.75 8.00 1.50 8.00 1.50 8.00 14.33 6.25 13.00 5.00 11.75 17.99 11.28 16.00 9.40 14.13 66 MHz Unit Min Max 2.68 — ns — ns 1.50 6.00 ns 3.80 10.54 ns 1.50 8.00 ns 3.80 10.04 ns 7.58 12.31 ns 1.50 6.00 ns 3.80 10.54 ns 1.50 8.00 ns 3.80 10.54 ns 7.58 12.31 ns MOTOROLA ...

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... UPWAIT valid to CLKOUT falling 6.00 9 edge B38 CLKOUT falling edge to UPWAIT 1.00 9 valid 10 B39 AS valid to CLKOUT rising edge 7.00 B40 A(0:31), TSIZ(0:1), RD/WR, BURST, 7.00 valid to CLKOUT rising edge MOTOROLA MPC860 Family Hardware Specifications Bus Signal Timing 33 MHz 40 MHz 50 MHz Min Max Min Max Min Max 6.00 1.50 6.00 1.50 6.00 14 ...

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... Figure 9-20. Figure 9-2 is the control timing diagram. 20 MPC860 Family Hardware Specifications 33 MHz 40 MHz 50 MHz Min Max Min Max Min Max — 7.00 — 7.00 — — 2.00 — 2.00 — — TBD — TBD — TBD 66 MHz Unit Min Max 7.00 — ns 2.00 — ns — TBD ns MOTOROLA ...

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... Minimum output hold time. C Minimum input setup time specification. D Minimum input hold time specification. Figure 9-2. Control Timing Figure 9-3 provides the timing for the external clock. CLKOUT Figure 9-3. External Clock Timing MOTOROLA MPC860 Family Hardware Specifications Bus Signal Timing 2.0 V 0.8 V 2 2.0 V 2.0 V 0.8 V 0.8 V ...

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... Figure 9-5 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT B11 TS, BB B11a TA, BI B14 TEA Figure 9-5. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals 22 MPC860 Family Hardware Specifications B9 B9 B13 B12 B13a B12a B15 Timing MOTOROLA ...

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... Figure 9-8 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) MOTOROLA MPC860 Family Hardware Specifications Bus Signal Timing ...

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... Figure 9-9 through Figure 9-12 provide the timing for the external bus read controlled by various GPCM factors. CLKOUT B11 TS B8 A[0:31] B22 CSx OE B28 WE[0:3] D[0:31], DP[0:3] Figure 9-9. External Bus Read Timing (GPCM Controlled—ACS = 00) 24 MPC860 Family Hardware Specifications B21 and DLT3 = 1 B12 B23 B25 B26 B19 B18 MOTOROLA ...

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... Figure 9-10. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT B11 TS B8 A[0:31] CSx B24a OE D[0:31], DP[0:3] Figure 9-11. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MOTOROLA MPC860 Family Hardware Specifications Bus Signal Timing B12 B23 B22a B25 B26 B18 B19 B12 B22b ...

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... CSx OE B27a B22b B22c D[0:31], DP[0:3] Figure 9-12. External Bus Read Timing (GPCM Controlled—TRLX = 1, ACS = 10, Figure 9-13 through Figure 9-15 provide the timing for the external bus write controlled by various GPCM factors. 26 MPC860 Family Hardware Specifications B23 B22a B27 B18 ACS = 11) B26 B19 MOTOROLA ...

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... CLKOUT B11 TS B8 A[0:31] B22 CSx WE[0:3] B26 OE D[0:31], DP[0:3] Figure 9-13. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 0) MOTOROLA MPC860 Family Hardware Specifications Bus Signal Timing B12 B30 B23 B25 B28 B29b B29 ...

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... Bus Signal Timing CLKOUT B11 TS B8 A[0:31] B22 CSx WE[0:3] B26 OE D[0:31], DP[0:3] Figure 9-14. External Bus Write Timing (GPCM Controlled—TRLX = 0, CSNT = 1) 28 MPC860 Family Hardware Specifications B12 B30a B30c B28b B28d B23 B25 B29c B29g B29a B28a B28c B8 B9 B29f MOTOROLA ...

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... B25 WE[0:3] B26 OE B8 D[0:31], DP[0:3] Figure 9-15. External Bus Write Timing (GPCM Controlled—TRLX = 1, CSNT = 1) Figure 9-16 provides the timing for the external bus controlled by the UPM. MOTOROLA MPC860 Family Hardware Specifications Bus Signal Timing B30b B30d B28b B28d B23 B29e B29i B29d B29h ...

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... B36 B35a B35b GPL_A[0:5], GPL_B[0:5] Figure 9-16. External Bus Timing (UPM Controlled Signals) Figure 9-17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM. 30 MPC860 Family Hardware Specifications B31a B31d B31c B31b B32a B32d B32c B32b B33a B33 MOTOROLA ...

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... CLKOUT B37 UPWAIT B38 CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 9-18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Figure 9-19 provides the timing for the synchronous external master access controlled by the GPCM. MOTOROLA MPC860 Family Hardware Specifications Bus Signal Timing Timing Timing 31 ...

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... GPCM. CLKOUT AS A[0:31], TSIZ[0:1], R/W CSx Figure 9-20. Asynchronous External Master Memory Access Timing (GPCM Controlled—ACS = 00) Figure 9-21 provides the timing for the asynchronous external master control signals negation. 32 MPC860 Family Hardware Specifications B41 B42 B40 B22 00) B39 B40 B22 MOTOROLA ...

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... Figure 9-22 provides the interrupt detection timing for the external level-sensitive lines. CLKOUT IRQx Figure 9-22. Interrupt Detection Timing for External Level Sensitive Lines Figure 9-23 provides the interrupt detection timing for the external edge-sensitive lines. MOTOROLA MPC860 Family Hardware Specifications Bus Signal Timing B43 All Frequencies ...

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... Max Min Max Min — 16.75 — 13.00 — 9.36 — 23.00 — 18.00 — 13.15 15.58 6.25 14.25 5.00 13.00 3.79 — 7.25 — 6.00 — 4.84 15.58 6.25 14.25 5.00 13.00 3.79 15.58 6.25 14.25 5.00 13.00 3.79 — 11.00 11.00 — 11.00 11.00 2.00 11.00 2.00 11.00 2.00 15.58 6.25 14.25 5.00 13.00 3.79 — 15.58 14.25 — 13.00 — 4.25 — 3.00 — 1.79 — 8.00 — 8.00 — 8.00 — 2.00 — 2.00 — 2.00 66 MHz Unit Max — ns — ns 11.84 ns — ns 11.84 ns 11.84 ns — 11.00 ns 11.00 ns 10.04 ns — 11.84 ns — ns — ns — ns MOTOROLA ...

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... P48 CE1/CE2 PCOE, IORD P52 ALE D[0:31] Figure 9-24. PCMCIA Access Cycles Timing External Bus Read Figure 9-25 provides the PCMCIA access cycle timing for the external bus write. MOTOROLA MPC860 Family Hardware Specifications Bus Signal Timing P44 P45 P47 P49 P50 P51 ...

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... Figure 9-26 provides the PCMCIA WAIT signals detection timing. CLKOUT WAITx Figure 9-26. PCMCIA WAIT Signals Detection Timing Table 9-9 shows the PCMCIA port timing for the MPC860. 36 MPC860 Family Hardware Specifications P44 P45 P47 P49 P50 P51 P53 P52 B8 B9 P55 P56 P54 MOTOROLA ...

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... Figure 9-27. PCMCIA Output Port Timing Figure 9-28 provides the PCMCIA output port timing for the MPC860. CLKOUT Input Signals Figure 9-28. PCMCIA Input Port Timing Table 9-10 shows the debug port timing for the MPC860. MOTOROLA MPC860 Family Hardware Specifications Bus Signal Timing 33 MHz 40 MHz 50 MHz Max ...

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... Figure 9-30 provides the timing for the debug port. DSCK DSDI D66 DSDO Figure 9-30. Debug Port Timings 38 MPC860 Family Hardware Specifications All Frequencies Min Max 3 × T — CLOCKOUT 1.25 × T — CLOCKOUT 0.00 3.00 8.00 — 5.00 — 0.00 15.00 0.00 2.00 D62 D62 D63 D64 D65 D67 MOTOROLA Unit — — ...

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... R81 DSDI, DSCK hold time 0.00 R82 SRESET negated to CLKOUT rising 242.42 edge for DSDI and DSCK sample Figure 9-31 shows the reset timing for the data bus configuration. MOTOROLA MPC860 Family Hardware Specifications Bus Signal Timing 33 MHz 40 MHz 50 MHz Max ...

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... Figure 9-32 provides the reset timing for the data bus weak drive during configuration. CLKOUT HRESET RSTCONF R77 D[0:31] (OUT) (Weak) Figure 9-32. Reset Timing—Data Bus Weak Drive During Configuration Figure 9-33 provides the reset timing for the debug port configuration. 40 MPC860 Family Hardware Specifications R76 R75 R69 R79 R78 MOTOROLA ...

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... TCK falling edge to output valid out of high impedance J94 TCK falling edge to output high impedance J95 Boundary scan input valid to TCK rising edge J96 TCK rising edge to boundary scan input invalid MOTOROLA MPC860 Family Hardware Specifications IEEE 1149.1 Electrical Specifications R70 R82 R80 R81 ...

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... J84 Figure 10-34. JTAG Test Clock Input Timing TCK TMS, TDI J87 TDO Figure 10-35. JTAG Test Access Port Timing Diagram TCK TRST Figure 10-36. JTAG TRST Timing Diagram 42 MPC860 Family Hardware Specifications J83 J83 J84 J85 J86 J88 J89 J91 J90 MOTOROLA ...

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... STBI low to STBO high (Tx interlock) 29 Data-in setup time to clock high 30 Data-in hold time from clock high 31 Clock low to data-out valid (CPU writes data, control, or direction Specification 23. MOTOROLA MPC860 Family Hardware Specifications CPM Electrical Characteristics J92 J94 J93 J95 J96 All Frequencies ...

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... STBI 27 STBO Figure 11-38. PIP Rx (Interlock Mode) Timing Diagram DATA-OUT 25 STBO (Output) STBI (Input) Figure 11-39. PIP Tx (Interlock Mode) Timing Diagram DATA-IN 21 STBI (Input) STBO (Output) Figure 11-40. PIP Rx (Pulse Mode) Timing Diagram 44 MPC860 Family Hardware Specifications MOTOROLA ...

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... Table 11-14 provides the IDMA controller timings as shown in Figure 11-43 through Figure 11-46. Table 11-14. IDMA Controller Timing Num Characteristic 40 DREQ setup time to clock high 41 DREQ hold time from clock high 42 SDACK assertion delay from clock high MOTOROLA MPC860 Family Hardware Specifications IDMA Controller AC Electrical Specifications All Frequencies Unit ...

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... Figure 11-43. IDMA External Requests Timing Diagram CLKO (Output) TS (Output) R/W (Output) 42 DATA TA (Input) SDACK Figure 11-44. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA 46 MPC860 Family Hardware Specifications All Frequencies Min Max — 12 — 20 — — MOTOROLA Unit ...

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... CLKO (Output) TS (Output) R/W (Output) 42 DATA TA (Output) SDACK Figure 11-45. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA CLKO (Output) TS (Output) R/W (Output) 42 DATA TA (Output) SDACK Figure 11-46. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA MOTOROLA MPC860 Family Hardware Specifications IDMA Controller AC Electrical Specifications ...

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... TIN/TGATE high time 64 TIN/TGATE cycle time 65 CLKO low to TOUT valid 48 MPC860 Family Hardware Specifications All Frequencies Min — All Frequencies Min Unit Max — ns Unit Max — ns — CLK — CLK — CLK 25 ns MOTOROLA ...

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... L1SYNC valid to L1ST(1–4) valid 79 L1CLK edge to L1ST(1–4) invalid 80 L1CLK edge to L1TXD valid 4 80A L1TSYNC valid to L1TXD valid 81 L1CLK edge to L1TXD high impedance 82 L1RCLK, L1TCLK frequency (DSC =1) MOTOROLA MPC860 Family Hardware Specifications Serial Interface AC Electrical Specifications All Frequencies Min 1, 2 — ...

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... L1RXD (Input) 76 L1ST(4-1) (Output) Figure 11-49. SI Receive Timing Diagram with Normal Clocking (DSC = 0) 50 MPC860 Family Hardware Specifications All Frequencies Min — 4 1.00 42.00 42.00 — 70 71a RFSD=1 77 BIT0 78 79 Unit Max — ns — ns 30.00 ns — L1TCL K — ns — ns 0.00 ns MOTOROLA ...

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... L1RCLK (FE=1, CE=1) (Input L1RCLK (FE=0, CE=0) (Input) RFSD=1 75 L1RSYNC (Input L1RXD BIT0 (Input L1ST(4-1) (Output) 84 L1CLKO (Output) Figure 11-50. SI Receive Timing with Double-Speed Clocking (DSC = 1) MOTOROLA MPC860 Family Hardware Specifications Serial Interface AC Electrical Specifications 83a ...

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... Serial Interface AC Electrical Specifications L1TCLK (FE=0, CE=0) (Input L1TCLK (FE=1, CE=1) (Input) 73 TFSD=0 75 L1TSYNC (Input) 74 80a L1TXD BIT0 (Output L1ST(4-1) (Output) Figure 11-51. SI Transmit Timing Diagram (DSC = 0) 52 MPC860 Family Hardware Specifications 81 79 MOTOROLA ...

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... L1RCLK (FE=0, CE=0) (Input L1RCLK (FE=1, CE=1) (Input) TFSD=0 75 L1RSYNC (Input L1TXD BIT0 (Output) 80 78a L1ST(4-1) (Output L1CLKO (Output) Figure 11-52. SI Transmit Timing with Double Speed Clocking (DSC = 1) MOTOROLA MPC860 Family Hardware Specifications Serial Interface AC Electrical Specifications 83a ...

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... Serial Interface AC Electrical Specifications Figure 11-53. IDL Timing 54 MPC860 Family Hardware Specifications MOTOROLA ...

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... The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater or equal to 3/1. 2 Also applies to CD and CTS hold time when they are used as an external sync signals. Figure 11-54 through Figure 11-56 show the NMSI timings. MOTOROLA MPC860 Family Hardware Specifications SCC in NMSI Mode Electrical Specifications All Frequencies ...

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... Figure 11-54. SCC NMSI Receive Timing Diagram TCLK1 102 102 TxD1 (Output) 103 RTS1 (Output) 104 CTS1 (Input) CTS1 (SYNC Input) Figure 11-55. SCC NMSI Transmit Timing Diagram 56 MPC860 Family Hardware Specifications 101 100 101 100 105 104 107 108 107 MOTOROLA ...

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... TCLK1 clock period 131 TXD1 active delay (from TCLK1 rising edge) 132 TXD1 inactive delay (from TCLK1 rising edge) 133 TENA active delay (from TCLK1 rising edge) MOTOROLA MPC860 Family Hardware Specifications Ethernet Electrical Specifications 101 100 107 104 All Frequencies ...

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... RxD1 (Input) RENA(CD1) (Input) Figure 11-58. Ethernet Receive Timing Diagram 58 MPC860 Family Hardware Specifications All Frequencies Min — — 120 121 121 124 123 Last Bit 125 126 127 Unit Max — CLK MOTOROLA ...

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... Figure 11-59. Ethernet Transmit Timing Diagram RCLK1 RxD1 0 1 (Input) Start Frame RSTRT (Output) Figure 11-60. CAM Interface Receive Start Timing Diagram REJECT Figure 11-61. CAM Interface REJECT Timing Diagram MOTOROLA MPC860 Family Hardware Specifications Ethernet Electrical Specifications 128 129 121 132 1 BIT1 BIT2 136 125 ...

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... SPI Master AC Electrical Specifications Table 11-22 provides the SPI master timings as shown in Figure 11-63 and Figure 11-64. 60 MPC860 Family Hardware Specifications All Frequencies Min 100 50 50 — 151 151 150 153 Unit Max — ns — ns — — ns — ns MOTOROLA ...

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... SPICLK (CI=1) (Output) 163 162 166 SPIMISO msb Data (Input) 165 167 SPIMOSI msb Data (Output) Figure 11-63. SPI Master ( Timing Diagram MOTOROLA MPC860 Family Hardware Specifications SPI Master AC Electrical Specifications All Frequencies Min Max 4 1024 2 512 50 — 0 — — — ...

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... Slave access time 62 MPC860 Family Hardware Specifications 166 160 167 Data lsb 165 164 166 Data lsb All Frequencies Min — msb msb Unit Max — t cyc — ns — ns — t cyc — t cyc — ns — MOTOROLA ...

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... SPICLK (CI=1) (Input) 177 SPIMISO Undef msb (Output) 175 176 SPIMOSI msb (Input) Figure 11-66. SPI Slave ( Timing Diagram MOTOROLA MPC860 Family Hardware Specifications SPI Slave AC Electrical Specifications 172 174 181 170 182 178 lsb Undef 181 182 lsb 172 ...

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... Unit Max 100 kHz 100 kHz µs — µs — µs — µs — µs — µs — — ns µs 1 300 ns µs — Unit Hz Hz — s — s — s — s — — — s MOTOROLA ...

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... UTPB, SOC, Rxclav and Txclav setup time U4 UTPB, SOC, Rxclav and Txclav hold time U5 UTPB, SOC active delay (and PHREQ and PHSEL active delay in MPHY mode) Figure 12-68 shows signal timings during UTOPIA receive operations. MOTOROLA MPC860 Family Hardware Specifications UTOPIA AC Electrical Specifications 204 207 208 209 ...

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... Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5 3 MPC860 Family Hardware Specifications HighZ at MPHY U4 4 HighZ at MPHY MOTOROLA ...

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... The transmitter functions correctly MII_TX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In addition, the processor clock frequency must exceed the MII_TX_CLK frequency – 1%. Table 13-28 provides information on the MII transmit signal timing. MOTOROLA MPC860 Family Hardware Specifications Min Max 5 — ...

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... Figure 13-72 shows the MII asynchronous inputs signal timing diagram. MII_CRS, MII_COL Figure 13-72. MII Async Inputs Timing Diagram 68 MPC860 Family Hardware Specifications Min Max 5 — — 65% 35% 65 Min Max 1.5 — M9 Unit ns MII_TX_CLK period MII_TX_CLK period Unit MII_TX_CLK period MOTOROLA ...

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... MII_MDC pulse width high M15 MII_MDC pulse width low Figure 13-73 shows the MII serial management channel timing diagram. MII_MDC (Output) MII_MDIO (Output) MII_MDIO (Input) M12 Figure 13-73. MII Serial Management Channel Timing Diagram MOTOROLA MPC860 Family Hardware Specifications Min Max 0 — — — ...

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... Table 14-32. MPC860 Family Package/Frequency Availability Frequency Package Type (MHz) 70 MPC860 Family Hardware Specifications 2 Ethernet Support Multi-Channel ATM (Mbps) HDLC Support Support 10/100 yes yes 10 N/A N/A 10/100 Yes Yes 10/100 Yes Yes 10 N/A N/A 10 Yes Yes 10/100 Yes Yes 10/100 Yes Yes Temperature Order Number (Tj) MOTOROLA ...

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... Ball grid array 50 (ZP suffi Ball grid array 50 (CZP suffi Where nn specifies version D.3 (as D3) or D.4 (as D4). MOTOROLA MPC860 Family Hardware Specifications Mechanical Data and Ordering Information 1 0° to 95°C XPC860DEZP50nn XPC860DTZP50nn XPC860ENZP50nn XPC860SRZP50nn XPC860TZP50nn XPC855TZP50D4 0° ...

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... WE1 WE3 CS4 CE2A VSSSYN1 N/C U N/C VSSSYN T XFC VDDSYN R PORESET KAPWR P XTAL N EXTCLK EXTAL M BADDR29 VDDL L OP1 MODCK1 K IRQ4 J IPB2 ALEB H IPB0 IPB7 G IPB4 IPB3 F IRQ3 BURST TEA C TA GPLA4 B WR GPLB4 A CS1 2 1 MOTOROLA ...

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... Mechanical Dimensions of the PBGA Package For more information on the printed circuit board layout of the PBGA package, including thermal via design and suggested pad layout, please refer to Motorola Application Note, Plastic Ball Grid Array (order number: AN1231/D), available from your local Motorola sales offi ...

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... B23 max value @ 66 Mhz from 2ns to 8ns, added this revision history table 6 10/2002 Added the MPC855T. Corrected Figure 9-25 on page 36. 6.1 11/2002 Corrected UTOPIA RXenb* and TXenb* timing values. Changed incorrect usage of Vcc to Vdd. Corrected dual port RAM to 8Kbytes. 74 MPC860 Family Hardware Specifications Change MOTOROLA ...

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... THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA MPC860 Family Hardware Specifications Document Revision History 75 ...

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... Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc Equal Opportunity/Affirmative Action Employer. ...