K7N323601M-QC20 Samsung, K7N323601M-QC20 Datasheet
K7N323601M-QC20
Related parts for K7N323601M-QC20
K7N323601M-QC20 Summary of contents
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... K7N323601M K7N321801M Document Title 1Mx36 & 2Mx18-Bit Pipelined NtRAM Revision History Rev. No. History 0.0 1. Initial document. 0.1 1. Add 165FBGA package 0.2 1. Update JTAG scan order 2. Speed bin merge. From K7N3236(18)09M to K7N3236(18)01M 3. AC parameter change. tOH(min)/tLZC(min) from 0.8 to 1.5 at -25 tOH(min)/tLZC(min) from 1.0 to 1.5 at -22 tOH(min)/tLZC(min) from 1 ...
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... K7N323601M K7N321801M 32Mb NtRAM(Flow Through / Pipelined) Ordering Informa Org. Part Number K7M321825M-QC75 2Mx18 K7N321801M-Q(F)C25/20/16/13 K7N321845M-Q(F)C25/20/16/13 K7M323625M-QC75 1Mx36 K7N323601M-Q(F)C25/20/16/13 K7N323645M-Q(F)C25/20/16/13 1Mx36 & 2Mx18 Pipelined NtRAM tion Speed Mode VDD FT ; Access Time(ns) Pipelined ; Cycle Time(MHz) FlowThrough 3.3 7.5ns Pipelined 3.3 250/200/167/133MHz Pipelined 2 ...
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... For read cycles, pipelined SRAM output data is temporarily stored by an edge triggered output register and then released to the output buffers at the next rising edge of clock. -20 -16 -13 Unit The K7N323601M and K7N321801M are implemented with 5.0 6.0 7.5 ns SAMSUNG s high performance CMOS technology and is avail- 3.2 3 ...
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... Burst Mode Control Note : 1. A and A are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired 1Mx36 & 2Mx18 Pipelined NtRAM 100 Pin TQFP (20mm x 14mm) K7N323601M(1Mx36) TQFP PIN NO. SYMBOL 32,33,34,35,36,37,43, V Power Supply(+3.3V) DD 44,45,46,47,48,49,50, V Ground ...
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... K7N323601M K7N321801M PIN CONFIGURATION (TOP VIEW) N.C. 1 N. DDQ V 5 SSQ N.C. 6 N.C. 7 DQb 8 8 DQb SSQ V 11 DDQ DQb 12 6 DQb DQb 18 4 DQb DDQ 21 V SSQ DQb 22 2 DQb ...
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... K7N323601M K7N321801M 165-PIN FBGA PACKAGE CONFIGURATIONS K7N323601M(1Mx36 CS2 C DQPc NC V DDQ D DQc DQc V DDQ E DQc DQc V DDQ F DQc DQc V DDQ G DQc DQc V DDQ DQd DQd V DDQ K DQd DQd V DDQ L DQd DQd V DDQ M DQd ...
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... K7N323601M K7N321801M 165-PIN FBGA PACKAGE CONFIGURATIONS K7N321801M(2Mx18 CS2 DDQ D NC DQb V DDQ E NC DQb V DDQ F NC DQb V DDQ G NC DQb V DDQ DQb NC V DDQ K DQb NC V DDQ L DQb NC V DDQ M DQb ...
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... K7N323601M K7N321801M FUNCTION DESCRIPTION The K7N323601M and K7N321801M are NtRAM there is transition from Read to Write, or vice versa. All inputs (with the exception LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by the burst advance pin (ADV) ...
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... K7N323601M K7N321801M BEGIN READ READ BURST COMMAND DS READ WRITE BURST Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) 1Mx36 & ...
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... K7N323601M K7N321801M TRUTH TABLES SYNCHRONOUS TRUTH TABLE ADV WE BWx ...
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... K7N323601M K7N321801M ASYNCHRONOUS TRUTH TABLE OPERATION ZZ Sleep Mode H L Read L Write L Deselected L ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on Any Other Pin Relative to V Power Dissipation Storage Temperature Operating Temperature Storage Temperature Range Under Bias *Note : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... K7N323601M K7N321801M DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL Input Leakage Current(except ZZ) Output Leakage Current Operating Current Standby Current Output Low Voltage(3.3V I/O) Output High Voltage(3.3V I/O) Output Low Voltage(2.5V I/O) Output High Voltage(2.5V I/O) Input Low Voltage(3.3V I/O) Input High Voltage(3.3V I/O) Input Low Voltage(2.5V I/O) Input High Voltage(2.5V I/O) Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. ...
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... K7N323601M K7N321801M Output Load(A) Dout Zo=50 AC TIMING CHARACTERISTICS PARAMETER Cycle Time Clock Access Time Output Enable to Data Valid Clock High to Output Low-Z Output Hold from Clock High Output Enable Low to Output Low-Z Output Enable High to Output High-Z Clock High to Output High-Z Clock High Pulse Width ...
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... K7N323601M K7N321801M SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I SLEEP MODE is dictated by the length of time the High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE ...
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... K7N323601M K7N321801M IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control ...
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... K7N323601M K7N321801M SCAN INFORMATION (165 FBGA ) SCAN REGISTER DEFINITION Part Instruction Register 1Mx36 3 bits 2Mx18 3 bits ID REGISTER DEFINITION Revision Number Part (31:28) 1Mx36 0000 2Mx18 0000 BOUNDARY SCAN EXIT ORDER BIT PIN ID(x18 10P 7 10R 8 11R 9 11P ...
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... K7N323601M K7N321801M JTAG DC OPERATING CONDITIONS Parameter Power Supply Voltage Input High Level ( 3.3V I/O / 2.5V I/O ) Input Low Level ( 3.3V I/O / 2.5V I/O ) Output High Voltage( 3.3V I/O / 2.5V I/O ) Output Low Voltage( 3.3V I/O / 2.5V I/O ) NOTE : The input level of SRAM pin is to follow the SRAM DC specification JTAG AC TEST CONDITIONS Parameter Input High/Low Level( 3.3V I/O , 2.5V I/O ) Input Rise/Fall Time( 3.3V I/O , 2.5V I/O ) ...
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... K7N323601M K7N321801M 1Mx36 & 2Mx18 Pipelined NtRAM - Nov. 2003 Rev 2.0 ...
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... K7N323601M K7N321801M 1Mx36 & 2Mx18 Pipelined NtRAM - Nov. 2003 Rev 2.0 ...
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... K7N323601M K7N321801M 1Mx36 & 2Mx18 Pipelined NtRAM - Nov. 2003 Rev 2.0 ...
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... K7N323601M K7N321801M 1Mx36 & 2Mx18 Pipelined NtRAM - Nov. 2003 Rev 2.0 ...
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... K7N323601M K7N321801M 1Mx36 & 2Mx18 Pipelined NtRAM - Nov. 2003 Rev 2.0 ...
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... K7N323601M K7N321801M PACKAGE DIMENSIONS 100-TQFP-1420A #1 0.65 1Mx36 & 2Mx18 Pipelined NtRAM 22.00 0.30 20.00 0.20 0.30 (0.58) 0.10 0.10 MAX 1.40 0.05 MIN 0.50 0. Units ; millimeters/Inches 0~8 + 0.10 0.127 - 0.05 16.00 0.30 0.10 MAX 14.00 0.20 (0.83) 0.50 0.10 1.60 MAX 0.10 TM Nov. 2003 Rev 2.0 ...
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... K7N323601M K7N321801M 165 FBGA PACKAGE DIMENSIONS 15mm x 17mm Body, 1.0mm Bump Pitch, 11x15 Ball Array C E Symbol Value Units 0.1 C 1.3 0.1 D 0.35 0.05 1Mx36 & 2Mx18 Pipelined NtRAM Note Symbol Top View Side View D Bottom View ...