DSP56002PV66 Motorola, DSP56002PV66 Datasheet

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... Unit Core Internal Data Bus Switch OnCE™ Port Interrupt Control Clock PLL Gen. Program Control Unit IRQ Figure 1 DSP56002 Block Diagram ©1996 MOTOROLA, INC Program Serial Host Memory Comm. Interface 512 24 RAM (SCI) (HI ROM or I/O or I/O (boot) PAB ...

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... Values for and (800) 521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com Logic State Signal State True Asserted False Deasserted True Asserted False Deasserted are defined by individual product specifications. OH DSP56002/D, Rev Voltage MOTOROLA ...

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... Two 256 24-bit on-chip data ROMs containing sine, A-law, and -law tables • External memory expansion with 16-bit address and 24-bit data buses • Bootstrap loading from external data bus, Host Interface, or Serial Communications Interface MOTOROLA DSP56002/D, Rev. 3 DSP56002 Features ...

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... Byte-wide host interface (HI) with Direct Memory Access (DMA) support (or fifteen Port B GPIO lines) • SSI support: – Supports serial devices with one or more industry-standard codecs, other DSPs, microprocessors, and Motorola-SPI-compliant peripherals – Asynchronous or synchronous transmit and receive sections with separate or shared internal/external clocks and frame syncs – ...

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... DSP56002 and are necessary to design properly with the part. Documentation is available from one of the following locations (see back cover for detailed information): • A local Motorola distributor • A Motorola semiconductor sales office • A Motorola Literature Distribution Center • The World Wide Web (WWW) Name DSP56000 ...

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... Product Documentation vi DSP56002/D, Rev. 3 MOTOROLA ...

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... Port A signals define the External Memory Interface port. 2. Port B signals are the HI signals multiplexed on the external pins with the GPIO signals. 3. Port C signals are the SCI and SSI signals multiplexed on the external pins with the GPIO signals. Figure 1 diagram of DSP56002 signals by functional group. MOTOROLA SECTION 1 1 Port A 2 ...

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... Interface (SSI) STD 2 Port Timer/ TIO Event Counter DSCK OnCE DSI Port DSO DR DSP56002/D, Rev. 3 Interrupt IRQA IRQB NMI Port B PB0–PB7 PB8–PB10 PB11 PB12 PB13 PB14 Port C PC0 PC1 PC2 PC3–PC5 PC6 PC7 PC8 Status OS1 OS0 AA1081G MOTOROLA ...

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... Host Interface Power —These lines supply power to the Host Interface logic. CCH V Serial Interface Power —This line supplies power to the serial interface logic CCS (SCI and SSI). MOTOROLA Table 1-2 Power Description power rail. Use a 0.1 F capacitor and a CC line and the GND line ...

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... Interface logic. GND (2) Serial Interface Ground —These lines supply ground connections for the serial S interface logic (SCI and SSI). 1-4 Table 1-3 Ground Description line and the GND line. CCP P line and the GND line. CCQ Q DSP56002/D, Rev. 3 line and the GND CCCK CK MOTOROLA ...

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... Input PCAP Input/ Indeter- Output minate MOTOROLA Table 1-4 PLL and Clock Signals Signal Description External Clock/Crystal Input—This input connects the internal oscillator input to an external crystal external oscillator. Crystal Output—This output connects the internal crystal oscillator output to an external crystal external oscillator is used, XTAL should be left unconnected. PLL Output Clock— ...

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... Note: PLOCK is a reliable indicator of the PLL lock state only after the chip has exited the Reset state. During hardware reset, the PLOCK state is determined by PINIT and the current PLL lock condition. DSP56002/D, Rev. 3 MOTOROLA ...

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... Reset D0–D23 Input/ Tri-stated Data Bus—These signals provide the bidirectional data bus for Output MOTOROLA Table 1-5 Address Bus Signals Signal Description program and data memory accesses. If there is no external bus activity, A0–A15 remain at their previous values to reduce power consumption. A0–A15 are tri-stated when the bus grant signal is asserted ...

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... Note: To prevent erroneous operation, pull up the BR signal when it is not in use. Bus Grant—When this output is asserted, it grants an external device’s request for access to the external bus. This output is deasserted during hardware reset. DSP56002/D, Rev. 3 MOTOROLA ...

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... Output Tri-stated Write Enable—WR is asserted low during external memory write RD Output Tri-stated Read Enable—RD is asserted low during external memory read MOTOROLA Signal Description Bus Not Required—The BN signal is asserted whenever the chip requires mastership of the external bus. During instruction cycles where the external bus is not required deasserted ...

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... IRQB. After reset, the chip operating mode can be changed by software. The IRQB input is an external interrupt request that indicates that an external device is requesting service. It may be programmed to be level-sensitive or negative-edge- triggered. If level-sensitive triggering is selected, an external pull up resistor is required for wired-OR operation. DSP56002/D, Rev. 3 MOTOROLA ...

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... Type Reset MODC/NMI Input Input RESET Input Input MOTOROLA Signal Description Mode Select C/Non-maskable Interrupt Request—This input has two functions select the initial chip operating mode, and 2. after internal synchronization, to allow an external device to request a non-maskable DSP interrupt. MODC is read and internally latched in the DSP when the processor exits the Reset state ...

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... DSP. HR/W must be stable when HEN is asserted. Port B GPIO 11 (PB11)—This signal is a General Purpose I/O signal called PB11 when the Host Interface is not being used. After reset, the default state for this signal is GPIO input. DSP56002/D, Rev. 3 MOTOROLA ...

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... Tri-stated Host Acknowledge—This input has two functions. It provides a PB14 Input or Output MOTOROLA Table 1-9 HI Signals (Continued) Signal Description bus. When HEN is asserted and HR/W is high, H0–H7 become outputs and the host processor may read DSP56002/L002 data. When HEN is asserted and HR/W is low, H0–H7 become inputs ...

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... Synchronous mode. The direction and function of the signal is defined by the RCM bit in the SCI+ Clock Control Register (SCCR). Port C GPIO 2 (PC2)—This signal is a GPIO signal called PC2 when the SCI SCLK function is not being used. After reset, the default state is GPIO input. DSP56002/D, Rev. 3 MOTOROLA ...

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... Output PC4 SC2 Input Tri- or stated Output PC5 MOTOROLA Synchronous Serial Interface Port Signal Description Serial Clock 0 (SC0)—This signal’s function is determined by whether the SCLK is in Synchronous or Asynchronous mode. • In Synchronous mode, this signal is used as a serial I/O flag. • In Asynchronous mode, this signal receives clock I/O. ...

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... SSI Transmit Data (STD)—This output signal transmits serial data from the SSI Transmitter Shift Register. Port C GPIO 8 (PC8)—This signal is a GPIO signal called PC8 when the SSI STD function is not being used. After reset, the default state is GPIO input. DSP56002/D, Rev. 3 MOTOROLA ...

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... TIO Input Tri- or stated Output MOTOROLA Table 1-12 Timer Signals Signal Description Timer Input/Output—The TIO signal provides an interface to the timer/event counter module. When the module functions as an external event counter or is used to measure external pulse width/ signal period, the TIO is an input. When the module functions as a timer, the TIO is an output, and the signal on the TIO signal is the timer pulse ...

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... When output, this signal works with the OS0 signal to provide information about the chip status. The DSCK/OS1 signal is an output when the chip is not in Debug mode. Note: Connect an external pull-down resistor to this signal. DSP56002/D, Rev. 3 MOTOROLA ...

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... Output Pulled high DR Input Input MOTOROLA Signal Description Debug Serial Output—Data contained in one of the OnCE controller registers is provided through the DSO output signal, as specified by the last command received from the external command controller. Data is always shifted out the OnCE serial port Most Significant Bit (MSB) first ...

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... Signal/Pin Descriptions On-Chip Emulation Port 1-20 DSP56002/D, Rev. 3 MOTOROLA ...

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... Therefore, a “maximum” value for a specification will never occur in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. MOTOROLA SECTION SPECIFICATIONS CAUTION DSP56002/D, Rev ...

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... stg Table 2-2 Thermal Characteristics PQFP TQFP 3 Value Value 12.4 10 4.0 0.16 JT DSP56002/D, Rev. 3 Value –0.3 to +7.0 (GND – –40 to +105 –55 to +150 TQFP PGA Unit Value Value ˚ 40.6 22 C/W ˚ — 6.5 C/W ˚ — N/A C/W MOTOROLA Unit ...

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... Input Capacitance Section 4 Design Considerations Notes order to obtain these results all inputs must be terminated (i.e., not allowed to float). 3. Values are given for PLL enabled. 4. Values are given for CKOUT enabled. 5. Periodically sampled and not 100% tested MOTOROLA Symbol ...

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... Fall Time Note: The midpoint Figure 2-1 Signal Measurement Reference 2-4 minimum of 2.4 V for all pins, except EXTAL, IH and V reference levels set at 0.8 V and 2 Pulse Width Low – DSP56002/D, Rev RESET High 90% 50% 10% Rise Time AA0179 MOTOROLA , ...

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... With PLL enabled and MF > 4 Internal Clock Low Period • With PLL disabled • With PLL enabled and MF 4 • With PLL enabled and MF > 4 Internal Clock Cycle Time Instruction Cycle Time MOTOROLA , substitute with the numbers in Table 2- ...

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... MHz load limits crystal current. 4. Reference Benjamin Parzen, The Design of Crystal and Other Harmonic Oscillators, John Wiley & Sons, 1983. DSP56002/D, Rev. 3 XTAL XTAL1 3rd Overtone Crystal Oscillator 10% 10% 20% 20% 10% 10% overtone crystal. rd overtone, AA0211 MOTOROLA ...

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... With PLL disabled • With PLL enabled 4 Instruction Cycle Time = CYC C • With PLL disabled • With PLL enabled Note: External Clock Input High and External Clock Input Low are measured at 50% of the input transition. MOTOROLA 0.5 (V – ILC ...

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... Min Max Unit 10 f MHz MF 340 MF 480 pF MF 380 MF 970 pF ) for CCP Min Max Unit — 75000T — 25T — 2500T — 8 — — — ns MOTOROLA ...

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... Duration of Level Sensitive IRQA Assertion to ensure interrupt service (when exiting ‘Stop’) • Internal Crystal Oscillator Clock, OMR bit • Stable External Clock, OMR Bit • Stable External Clock, PCTL Bit MOTOROLA RESET, Stop, Mode Select, and Interrupt Timing 5T 9T 11T ...

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... Since this stabilization period typically allowed to assure that the oscillator is stable before executing C 10 Figure 2-4 Reset Timing 13 DSP56002/D, Rev. 3 Min Max Unit 65548T — 20T — 13T — IHR 11 First Fetch AA0356 AA0357 MOTOROLA ...

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... IRQA IRQB NMI General Purpose I/O 18 IRQA IRQB NMI Figure 2-7 External Level-Sensitive Fast Interrupt Timing MOTOROLA RESET, Stop, Mode Select, and Interrupt Timing 14 V IHM V ILM First Interrupt Instruction Execution/Fetch First Interrupt Instruction Execution 22 b) General Purpose I/O DSP56002/D, Rev. 3 ...

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... A0–A15, DS, PS X/Y Figure 2-10 Recovery from Stop State Using IRQA IRQA A0–A15, DS, PS X/Y Figure 2-11 Recovery from Stop State Using IRQA Interrupt Service 2-12 16 16A T0 First Instruction Fetch 27 28 DSP56002/D, Rev. 3 AA0361 AA0362 AA0363 First IRQA Interrupt Instruction Fetch AA0364 MOTOROLA ...

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... HA0–HA2 Setup Time Before HEN Assertion 44 HA0–HA2 Hold Time After HEN Deassertion 45 DMA HACK Assertion to HREQ Deassertion 46 DMA HACK Deassertion to HREQ Assertion • For DMA RXL Read • For DMA TXL Write • All other cases MOTOROLA Min 4,5 T ...

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... May decrease for future versions. HREQ (Output) HACK (Input) 41 HR/W (Input) 35 H0–H7 (Output) Figure 2-12 Host Interrupt Vector Register (IVR) Read 2-14 4,5 4,5 4,5 Section Data Valid DSP56002/D, Rev. 3 Min Max Unit — — AA1084 MOTOROLA ...

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... Figure 2-13 Host Read Cycle (Non-DMA Mode) HREQ (Output) TXH HEN Write (Input HA2–HA0 Address Valid (Input) 39 HR/W (Input) 33 H0–H7 (Output) Figure 2-14 Host Write Cycle (Non-DMA Mode) MOTOROLA RXM Read 32 44 Address Valid Data Valid TXM Write 32 44 Address Valid 40 34 Data ...

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... H0–H7 Data (Output) Valid 2- RXM Read 37 38 Data Valid Figure 2-15 Host DMA Read Cycle 46 32 TXM Write 34 Data Valid Figure 2-16 Host DMA Write Cycle DSP56002/D, Rev RXL Read Data Valid AA1115 46 46 TXL Write Data Valid AA1116 MOTOROLA ...

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... Clock Low Period 69 Clock High Period 70 < intentionally blank > 71 Output Data Setup to Clock Rising Edge (Internal Clock) 72 Output Data Hold After Clock Rising Edge (Internal Clock) MOTOROLA Serial Communication Interface (SCI) Timing is determined by the SCI Clock SCC value SCC C Min 8T SCC ...

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... In the wire-OR mode, TXD can be pulled Figure 2-18 SCI Asynchronous Mode Timing 2- Data Valid 61 62 Data Valid a) Internal Clock Data Valid 65 66 Data Valid b) External Clock Data Valid DSP56002/D, Rev AA0388 69 72 AA0389 MOTOROLA ...

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... FSR Out (bl) Low 86 RXC Rising Edge to FSR Out (wl) High 87 RXC Rising Edge to FSR Out (wl) Low 88 Data In Setup Time Before RXC (SCK in Synchronous Mode) Falling Edge MOTOROLA Synchronous Serial Interface (SSI) Timing Table 2-11 SSI Timing 40 MHZ or 66 MHz Min Max 4T — — – ...

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... MOTOROLA ...

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... Falling Edge 106 Flag Output Valid After TXC Rising Edge Notes: 1. For internal clock, External Clock Cycle is defined Periodically sampled and not 100% tested MOTOROLA Synchronous Serial Interface (SSI) Timing Table 2-11 SSI Timing (Continued) 40 MHZ or 66 MHz Min Max — ...

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... In the Network mode, output flag transitions can occur at the start of each time slot within the frame. In the Normal mode, the output flag state is asserted for the entire frame period. 2- 100 100 99 First Bit 105 103 104 106 Figure 2-19 SSI Transmitter Timing DSP56002/D, Rev 101A 101 Last Bit 105 See Note AA0390 MOTOROLA ...

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... RXC (Input/Output) FSR (Bit) Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In Flags In MOTOROLA Synchronous Serial Interface (SSI) Timing First Bit Figure 2-20 SSI Receiver Timing DSP56002/D, Rev. 3 Specifications 87 89 Last Bit 92 94 AA0391 2-23 ...

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... DSP56002/D, Rev MHz Max Min Max + WS WS WS) +14 (2T WS MOTOROLA Unit ...

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... Data Out Hold Time T H from WR Deassertion (the maximum specification is periodically sampled, and not 100% tested) 125 Data Out Setup Time to WR Deassertion • – 0.8 L • WS > – 0.8 MOTOROLA 40 MHz 66 MHz Max Min 5.5 — T 5.5 C – + — – 5.5 H — – ...

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... – – — T – 4.5 — – 5.5 — T – 5 – — ((WS+ 5.5 5.5 — T – 5 — C — T – 2.5 — C — T – 3 — C — — – MOTOROLA Unit – ...

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... Characteristics Min 136 RD Deassertion to WR Assertion • • WS > A0–A15, PS DS, X/Y, RD, WR D0–D23 Figure 2-21 Bus Request / Bus Grant Timing MOTOROLA 40 MHz 66 MHz Max Min – 4 — T – 2 — – – 2.5 H 115 117 118 DSP56002/D, Rev ...

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... Note) RD 120 135 WR 123 D0–D23 Note: During Read-Modify-Write instructions, the address lines do not change state. Figure 2-22 External Bus Asynchronous Timing 2-28 127 131 129 122 121 133 132 130 125 124 Data Out DSP56002/D, Rev. 3 126 134 136 128 Data In AA0393 MOTOROLA ...

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... T149) indicate the time after which data/address are no longer guaranteed to be valid. 4. Timings are given from CKOUT midpoint First CKOUT transition is a falling edge of CKOUT for CKP = 0. MOTOROLA External Bus Synchronous Timing 40 MHz 66 MHz Min Max Min — ...

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... RD 141 WR D0–D23 BN 171 EXTAL 170 Note: During Read-Modify-Write Instructions, the address lines do not change states. Figure 2-23 Synchronous Bus Timing 2- 143 142 Data Out 145 146 172 DSP56002/D, Rev 144 149 147 148 Data In AA0395 MOTOROLA ...

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... WT Deassertion Deassertion 159 Minimum BS Deassertion Width for Consecutive External Accesses 160 BS Deassertion to 2 Address Invalid 161 Data-In Valid to RD Deassertion (Set Up) 162 BR Assertion to second CKOUT transition for Minimum Timing MOTOROLA 40 MHz 66 MHz Min Max Min — — 5.6 5.3 — 5 – 7.9 ...

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... Stop state. 2-32 40 MHz 66 MHz Min Max Min — 8.8 — — 5.3 — 3 9.7 3 0.3 3.7 0.3 — 5.7 — — 5 — DSP56002/D, Rev MHz Unit Max Min Max 8.8 — 8.8 ns 5.3 — 5.3 ns 9.7 3 9.7 ns 3.7 0.3 3.7 ns 5.7 — 5 — MOTOROLA ...

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... CKOUT 162 BR BG Figure 2-24 Synchronous Bus Request / Bus Grant Timing MOTOROLA External Bus Synchronous Timing 164 163 DSP56002/D, Rev. 3 Specifications 165 AA0396 2-33 ...

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... During Read-Modify-Write instructions, the address lines do not change state. However, BS will deassert before asserting again for the write cycle. Figure 2-25 Synchronous Timings 2- 152 153 145 DSP56002/D, Rev 149 154 144 147 148 Data In 142 146 Data Out AA0397 MOTOROLA ...

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... D0–D23 120 WR D0–D23 Note: During Read-Modify-Write instructions, the address lines do not change state. However, BS will deassert before asserting again for the write cycle. Figure 2-26 Asynchronous Timings MOTOROLA External Bus Synchronous Timing 158 123 125 Data Out DSP56002/D, Rev. 3 Specifications ...

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... — – — – 21 — — — — 17T — 12T – — C 17T — 65548T + 20T + 13T + MOTOROLA ...

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... The maximum specified is periodically sampled and not 100% tested. DSCK (Input) Figure 2-27 OnCE Serial Clock Timing DR (Input) DSO (Output) Figure 2-28 OnCE Acknowledge Timing MOTOROLA Table 2-15 OnCE Port Timing 65549T 21T 14T 1 65553T 25T 18T , T , and T will not be constant ...

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... Figure 2-31 OnCE Data I/O To Status Timing 2-38 (Last) 237 (Last) 235 Figure 2-30 OnCE Read Timing 239 (See Note) 240 (See Note) 236 DSP56002/D, Rev. 3 (OS1) (ACK) 238 (OS0) (See Note) AA0501 (See Note) 245 AA0502 (DSCK Input) (DSO Output) (DSI Input) 237 AA0503 MOTOROLA ...

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... Figure 2-33 OnCE Read Register to Next Command Timing CKOUT DR (Input) DSO (Output) Figure 2-34 Synchronous Recovery from Wait State DR (Input) DSO (Output) Figure 2-35 Asynchronous Recovery from Wait State MOTOROLA 242 244 T0, T2 T1, T3 248 246 247 248 249 DSP56002/D, Rev. 3 Specifications OnCE Port Timing ...

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... Specifications OnCE Port Timing DR (Input) DSO (Output) Figure 2-36 Asynchronous Recovery from Stop State 2-40 250 251 DSP56002/D, Rev. 3 AA0508 MOTOROLA ...

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... CKOUT Rising Edge to TIO (output) Deassertion 266 CKOUT Rising Edge to TIO (General Purpose Output) TIO CKOUT TIO (Input) ADDRESS Figure 2-38 Timer Interrupt Generation MOTOROLA Table 2-16 Timer Timing 260 261 Figure 2-37 TIO Timer Event Input 262 First Interrupt Instruction Execution DSP56002/D, Rev. 3 ...

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... Timer Timing CKOUT TIO (Output) Figure 2-39 External Pulse Generation fetch the instruction MOVE X0,X:(R0); X0 contains the new value of TIO CKOUT A0–A15 PS, DS EXTP, X/Y TIO (Output) 2-42 264 ; and R0 contains the address of TCSR Figure 2-40 GPIO Output Timing DSP56002/D, Rev. 3 265 AA0511 266 AA0512 MOTOROLA ...

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... Section 1 are allocated for each package. The DSP56002 is available in three package types: • 132-pin Plastic Quad Flat Pack (PQFP) • 144-pin Thin Quad Flat Pack (TQFP) • 132-pin Ceramic Pin Grid Array (PGA) MOTOROLA SECTION 3 PACKAGING DSP56002/D, Rev. 3 3-1 ...

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... Orientation Mark (Chamfered Edge) (Top View) DSP56002/D, Rev. 3 GND D D21 D20 V CCD D19 D18 GND D D17 D16 D15 D14 GND D D13 D12 V CCD D11 D10 GND D GND Q V CCQ GND CCD D3 D2 GND AA0611 MOTOROLA ...

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... An OVERBAR indicates the signal is asserted when the voltage = ground (active low simplify locating the pins, each fifth pin is shaded in the illustration. Figure 3-2 Bottom View of the 132-pin Plastic Quad Flat Pack (PQFP) Package MOTOROLA Pin-out and Package Information (Bottom View) DSP56002/D, Rev ...

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... HACK RXD C TXD SCLK SC0 SC1 SC2 SCK SRD STD TIO No port assigned DSP56002/D, Rev. 3 GPIO ID PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 MOTOROLA ...

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... HREQ/PB13 14 H7/PB7 15 H6/PB6 16 GND H 17 H5/PB5 18 H4/PB4 19 H3/PB3 20 V CCH 21 H2/PB2 22 GND H 23 H1/PB1 24 H0/PB0 25 RXD/PC0 MOTOROLA Pin-out and Package Information Pin No. Signal Name Pin No. 26 TXD/PC1 51 27 GND SCLK/PC2 53 29 SC0/PC3 CCS 31 SCK/PC6 56 32 SC2/PC5 57 33 STD/PC8 ...

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... D16 127 109 D17 128 110 GND 129 D 111 D18 130 112 D19 131 113 V 132 CCD DSP56002/D, Rev. 3 Signal Name D20 D21 GND D D22 D23 MODC/NMI MODB/IRQB MODA/IRQA GND CK CKOUT V CCCK RESET CKP V CCP PCAP GND P PLOCK PINIT XTAL MOTOROLA ...

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... A12 78 A13 80 A14 82 A15 CKOUT 123 CKP 126 MOTOROLA Pin-out and Package Information Signal Name Pin No. D3 114 D4 116 D5 117 D6 119 D10 100 D11 101 D12 103 D13 104 D14 106 ...

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... RESET 125 RXD 25 SC0 29 SC1 35 SC2 32 SCK 31 SCLK 28 SRD 38 STD 33 TIO 39 TXD CCA V 69 CCA V 79 CCA V 45 CCC V 124 CCCK V 89 CCD V 102 CCD V 113 CCD V 9 CCH V 20 CCH V 127 CCP XTAL 132 MOTOROLA ...

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... MOTOROLA Pin-out and Package Information Power Supply V CCA GND A V CCC GND C V CCCK GND CK V CCD GND D V CCH GND H DSP56002/D, Rev. 3 Packaging Circuit Supplied ...

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... Pin-out and Package Information Table 3-4 DSP56002 Power Supply Pins in PQFP Package (Continued) Pin Number 127 129 3-10 Power Supply V CCQ GND Q V CCP GND P V CCS GND S DSP56002/D, Rev. 3 Circuit Supplied Internal Logic PLL Serial Port MOTOROLA ...

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... TIPS 0.012 H L 0.002 132X 0.008 U D 132X M 0.008 T L-M N SECTION AA-AA Figure 3-3 132-Pin Plastic Quad Flat Pack (PQFP) Mechanical Information MOTOROLA J1 N 117 116 PIN IDENT 0.002 L-M 4X 0.004 T 132X SEATING PLANE ...

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... Figure 3-4 Top View of the 144-pin Thin Quad Flat Pack (TQFP) Package 3-12 (Top View) DSP56002/D, Rev DSCK/OS1 NC GND CCC TIO SRD/PC7 V CCQ GND Q SC1/PC4 NC GND S STD/PC8 SC2/PC5 SCK/PC6 V CCS SC0/PC3 SCLK/PC2 GND S TXD/PC1 RXD/PC0 H0/PB0 H1/PB1 GND H H2/PB2 V CCH H3/PB3 H4/PB4 NC 37 AA0613 MOTOROLA ...

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... An OVERBAR indicates the signal is asserted when the voltage = ground (active low simplify locating the pins, each fifth pin is shaded in the illustration. Figure 3-5 Bottom View of the144-pin Thin Quad Flat Pack (TQFP) Package MOTOROLA Pin-out and Package Information (Bottom View) Orientation Mark DSP56002/D, Rev ...

Page 82

... HACK RXD C TXD SCLK SC0 SC1 SC2 SCK SRD STD TIO No port assigned DSP56002/D, Rev. 3 GPIO ID PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 MOTOROLA ...

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... PCAP 14 GND P 15 PLOCK 16 PINIT 17 XTAL EXTAL 20 V CCQ 21 GND Q 22 HA2/PB10 23 GND H 24 HA1/PB9 25 HA0/PB8 MOTOROLA Pin-out and Package Information Pin No. Signal Name Pin No. 26 HACK/PB14 CCH 28 HEN/PB12 53 29 GND HR/W/PB11 55 31 HREQ/PB13 56 32 H7/PB7 57 33 ...

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... CCD 116 D4 139 117 D5 140 118 GND 141 D 119 D6 142 120 D7 143 121 D8 144 DSP56002/D, Rev. 3 Signal Name D9 V CCQ GND Q GND D D10 NC D11 V CCD D12 D13 GND D D14 D15 D16 D17 GND D D18 D19 V CCD D20 D21 GND D NC MOTOROLA ...

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... A13 104 A14 106 A15 107 CKOUT 8 CKP 11 D0 110 D1 111 D2 113 MOTOROLA Pin-out and Package Information Signal Name Pin No. D3 114 D4 116 D5 117 D6 119 D7 120 D8 121 D9 122 D10 126 D11 128 D12 130 D13 131 ...

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... DSP56002/D, Rev. 3 Signal Name Pin No. PLOCK RESET 10 RXD 45 SC0 49 SC1 56 SC2 52 SCK 51 SCLK 48 SRD 59 STD 53 TIO 60 TXD CCA V 93 CCA V 103 CCA V 66 CCC V 9 CCCK V 115 CCD V 129 CCD V 140 CCD V 27 CCH V 40 CCH V 12 CCP MOTOROLA ...

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... Table 3-7 DSP56002 TQFP Pin Identification by Signal Name (Continued) Signal Name Pin No CCQ V 58 CCQ V 89 CCQ V 123 CCQ V 50 CCS X/Y 78 MOTOROLA Pin-out and Package Information Signal Name Pin No. XTAL DSP56002/D, Rev. 3 Packaging Signal Name Pin No. ...

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... Power Supply V CCA GND A V CCC GND C V CCCK GND CK V CCD GND D V CCH GND H DSP56002/D, Rev. 3 Circuit Supplied Address Bus Buffers Bus Control Buffers Clock Data Bus Buffers Host Interface Buffers MOTOROLA ...

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... Table 3-8 DSP56002 Power Supply Pins in TQFP Package (Continued) Pin Number 123 124 MOTOROLA Pin-out and Package Information Power Supply V CCQ GND Q V CCP GND P V CCS GND S DSP56002/D, Rev. 3 Packaging Circuit Supplied Internal Logic PLL Serial Port ...

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... D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLED DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.35. MILLIMETERS MIN MAX DIM A 20.00 BSC A1 10.00 BSC B 20.00 BSC B1 10.00 BSC C 1.40 1.60 C1 0.05 0.15 C2 1.35 1.45 D 0.17 0.27 E 0.45 0.75 F 0.17 0.23 G 0.50 BSC J 0.09 0.20 K 0.50 REF P 0.25 BSC R1 0.13 0.20 R2 0.13 0.20 S 22.00 BSC 0.25 S1 11.00 BSC V 22.00 BSC V1 11.00 BSC Y 0.25 REF Z 1.00 REF AA 0.09 0. MOTOROLA ...

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... No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias OVERBAR indicates the signal is asserted when the voltage = ground (active low). Figure 3-7 Top View of the 132-pin Ceramic (RC Pin Grid Array Package MOTOROLA ...

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... IRQB MODC/ D23 D21 D20 GND NMI D22 D18 GND D19 D17 D16 D15 D13 D14 D12 D10 D11 D9 A15 CCD A11 A14 D6 GND D5 A10 A13 D4 GND D3 A9 A12 CCD GND V GND D0 GND A CCA A MOTOROLA AA0616 ...

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... C11 E10 D10 B12 A11 B11 B10 C10 A10 C12 D12 E12 F11 G12 F13 F12 G13 G11 H11 MOTOROLA Pin-out and Package Information Primary Function Port HA0 HA1 HA2 HR/W HEN HREQ HACK RXD C TXD ...

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... HR/W/PB11 H1 D10 H4/PB4 H2 D11 H1/PB1 H3 D12 TXD/PC1 H11 D13 V H12 CCH E1 GND H13 D DSP56002/D, Rev. 3 Signal Name D18 D19 D22 H3/PB3 H0/PB0 SCLK/PC2 GND H D15 D16 D17 SC0/PC3 SCK/PC6 SC2/PC5 D14 D13 D12 STD/PC8 SC1/PC4 SRD/PC7 D11 D10 D9 TIO MOTOROLA ...

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... NC” are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias OVERBAR indicates the signal is asserted when the voltage = ground (active low). MOTOROLA Pin-out and Package Information Pin No. Signal Name Pin No. ...

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... GND N5 A GND N3 A GND N13 C GND C4 CK GND N1 D GND L1 D GND K1 D GND E1 D GND D1 D GND B1 D GND A12 H GND A13 H GND C13 H GND E13 H GND C6 P GND A1 Q GND A2 Q GND A5 Q GND A7 Q GND J13 S MOTOROLA ...

Page 97

... MODA C3 MODB C2 MODC D5 NMI D5 OS0 M11 OS1 N12 PB0 E11 PB1 D11 PB2 C11 PB3 E10 PB4 D10 MOTOROLA Pin-out and Package Information Signal Name Pin No. PB5 B12 PB6 A11 PB7 B11 PB8 C9 PB9 B9 PB10 A9 PB11 D9 PB12 B10 PB13 C10 PB14 ...

Page 98

... D1 B1 B13 D13 A12 A13 C13 E13 3-30 Power Supply V CCA GND A V CCC GND C V CCCK GND CK V CCD GND D V CCH GND H DSP56002/D, Rev. 3 Circuit Supplied Address Bus Buffers Bus Control Buffers Clock Data Bus Buffers Host Interface Buffers MOTOROLA ...

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... Table 3-12 DSP56002 Power Supply Pins in PGA Package (Continued) Pin Number K13 J13 L13 -T- -A- -B- C Figure 3-9 132-pin Ceramic Pin Grid Array (PGA) Package Mechanical Information MOTOROLA Power Supply V CCQ GND Q V CCP GND P V CCS GND ...

Page 100

... Ordering Drawings ORDERING DRAWINGS Complete mechanical information regarding DSP56002 packaging is available by facsimile through Motorola's Mfax™ system. Call the following number to obtain information by facsimile: The Mfax automated system requests the following information: • The receiving facsimile telephone number including area code or country code • ...

Page 101

... Printed Circuit Board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the Printed Circuit Board to which the package is mounted. Again, if the MOTOROLA SECTION + P R ...

Page 102

... Note: Table 2-2 Thermal Characteristics on page 2-2 contains the package thermal values for this chip. 4-2 do not satisfactorily answer whether the thermal determined by a thermocouple – DSP56002/D, Rev This value gives a better D MOTOROLA ...

Page 103

... V GND circuits. • All inputs must be terminated (i.e., not allowed to float) using CMOS levels. • Take special care to minimize noise levels on the PLL supply pins (both V and GND). MOTOROLA CAUTION ). CC CC and GND pins are less than 0.5 inch per capacitor lead. ...

Page 104

... Minimize external memory accesses; use internal memory accesses instead. 2. Minimize the number of pins that are switching. 3. Minimize the capacitive load on the pins. 4. Connect the unused inputs to pull-up or pull-down resistors. 4-4 – 5 2.75mA -max), reflects the maximum I CCI DSP56002/D, Rev. 3 expected CC -typ) reflects CCI MOTOROLA ...

Page 105

... TP1 nop jmp MOTOROLA p:RESET MAIN p:MAIN #$180000,x:$FFFD #0,r0 #0,r4 #$00FF, m0 #$00FF, m4 #256 r0,x:(r0)+ #256 r4,y:(r4)+ a l:(r0)+,a #30 x0,y0,a x:(r0)+,x0 y:(r4)+,y0 a,p:(r5) TP1 MAIN DSP56002/D, Rev. 3 Design Considerations Power Consumption ...

Page 106

... Host/DMA Interface Programming Model for descriptions of these status bits. OVERWRITING THE HOST VECTOR The Host programmer should change the Host Vector register only when the Host Command bit (HC) is clear. This change guarantees that the DSP interrupt control logic will receive a stable vector. 4-6 DSP56002/D, Rev. 3 MOTOROLA ...

Page 107

... A very small probability exists that the DSP will read the status bits synchronized during transition. The solution to this potential problem is to read the HF0 and HF1 bits twice and check for consensus. MOTOROLA DSP56002/D, Rev. 3 Design Considerations Host Port Considerations ...

Page 108

... D0 pin is near the corner of both the PQFP package (pin 84) and the TQFP package (pin 109), and is adjacent both packages. Note: Some “no connect” pins in the TQFP pin sequence are excluded from the PQFP pin sequence. 4-8 DSP56002/D, Rev. 3 MOTOROLA ...

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... Voltage Plastic Quad Flat Pack DSP56002 5 V Plastic Thin Quad Flat Ceramic Pin Grid Array MOTOROLA SECTION Package Type Pin Count 132 (PQFP) 144 Pack (TQFP) 132 DSP56002/D, Rev Frequency Order Number (MHz) 40 DSP56002FC40 66 DSP56002FC66 80 DSP56002FC80 40 DSP56002PV40 66 DSP56002PV66 80 DSP56002PV80 40 DSP56002RC40 5-1 ...

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... Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “ ...