EP1K30FC256 Altera Corporation, EP1K30FC256 Datasheet
EP1K30FC256
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EP1K30FC256 Summary of contents
Page 1
... Feature Typical gates Maximum system gates Logic elements (LEs) EABs Total RAM bits Maximum user I/O pins Altera Corporation A-DS-ACEX-01.01 ® Programmable logic devices (PLDs), providing low cost system-on-a-programmable-chip integration in a single device – Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions – ...
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... Individual tri-state output enable control for each pin – Open-drain option on each I/O pin – Programmable output slew-rate control to reduce switching noise – Clamp to V user-selectable on a pin-by-pin basis CCIO – Supports hot-socketing Preliminary Information TM options for reduced clock delay, Altera Corporation ...
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... Area (mm ) 256 Length ´ width 16 ´ 16 (mm ´ mm) Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Software design support and automatic place-and-route provided by ® Altera’s MAX+PLUS II development system for Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC ...
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... Resources Used LEs EABs (2) 544 Preliminary Information Performance Speed Grade -1 -2 200 188 128 200 188 128 3.2 4 212 181 131 142 128 Altera Corporation Units -3 MHz MHz 5 MHz MHz 94 MHz ...
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... Fast Fourier transform (FFT) function a16450 universal asynchronous receiver/transmitter (UART) Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Table 5 shows ACEX 1K device performance for more complex designs. These designs are available as Altera MegaCore LEs ...
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... When implementing logic, each EAB can contribute 100 to 600 gates towards complex logic functions such as multipliers, microcontrollers, state machines, and DSP functions. EABs can be used independently, or multiple EABs can be combined to implement larger functions. Preliminary Information MAX+PLUS II Programmable Logic Sheet. Altera Corporation ...
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... Preliminary Information Altera Corporation ACEX 1K Programmable Logic Family Data Sheet The logic array consists of logic array blocks (LABs). Each LAB contains eight LEs and a local interconnect consists of a 4-input LUT, a programmable flipflop, and dedicated signal paths for carry and cascade functions. The eight LEs can be used to create medium-sized blocks of logic— ...
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... Preliminary Information IOE IOE IOE IOE IOE Logic Array Logic Array Block (LAB) IOE IOE Local Interconnect IOE IOE IOE Altera Corporation Logic Element (LE) ...
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... Preliminary Information Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Embedded Array Block The EAB is a flexible block of RAM, with registers on the input and output ports, that is used to implement common gate array megafunctions. Because it is large and flexible, the EAB is suitable for functions such as multipliers, vector scalars, and error correction circuits ...
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... Data In 1,024 ´ 4 2,048 ´ 2 Data Out D Q ENA Read Address Q Write Address Read Enable Q Write Enable Multiplexers allow read address and read enable registers to be clocked by inclock or outclock signals. Column Interconnect 16, 32 Figure 3. The Figure 4). Altera Corporation ...
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... Global Signals Dedicated Clocks 2 EAB Local Interconnect (1) Note: (1) EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB local interconnect channels. Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Port A Port B address_a[] address_b[] data_a[] data_b[] we_a clkena_a ...
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... RAM blocks can be combined to form a 256 ´ 32 block, and two 512 ´ 8 RAM blocks can be combined to form a 512 ´ 16 block. Figure 6 shows examples of multiple EAB combination. 256 32 Preliminary Information Figure 5 shows the ACEX 1K 2,048 2 1,024 4 512 16 512 8 512 8 Altera Corporation ...
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... Preliminary Information Altera Corporation ACEX 1K Programmable Logic Family Data Sheet If necessary, all EABs in a device can be cascaded to form a single RAM block. EABs can be cascaded to form RAM blocks 2,048 words without impacting timing. The MAX+PLUS II software automatically combines EABs to meet a designer’s RAM specifications. ...
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... EP1K10, EP1K30, and EP1K50 devices have 30 LAB local interconnect channels; EP1K100 devices have 34. 14 Dedicated Inputs & Global Signals Row Interconnect 6 4 Carry-In & Cascade- LE1 4 LE2 4 LE3 4 LE4 4 LE5 4 LE6 4 LE7 4 LE8 Preliminary Information Carry-Out & Cascade-Out Altera Corporation See Figure 13 for details. Column-to-Row Interconnect Column Interconnect ...
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... Preliminary Information Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Each LAB provides four control signals with programmable inversion that can be used in all eight LEs. Two of these signals can be used as clocks, the other two can be used for clear/preset control. The LAB clocks can be driven by the dedicated clock input pins, global signals, I/O signals, or internal signals via the LAB local interconnect ...
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... LAB and all LABs in the same row. Intensive use of carry and cascade chains can reduce routing flexibility. Therefore, the use of these chains should be limited to speed-critical portions of a design. Preliminary Information Register Bypass Programmable Register PRN D Q ENA CLRN Altera Corporation To FastTrack Interconnect To LAB Local Interconnect ...
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... Preliminary Information Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Carry Chain The carry chain provides a very fast (as low as 0.2 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit drives forward into the higher-order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain ...
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... ACEX 1K Programmable Logic Family Data Sheet 18 Figure 9. ACEX 1K Carry Chain Operation (n-Bit Full Adder) Carry-In a1 LUT b1 Carry Chain a2 LUT b2 Carry Chain a n LUT b n Carry Chain LUT Carry Chain Preliminary Information s1 Register LE1 Register s2 LE2 s n Register LE n Register Carry-Out Altera Corporation ...
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... Figure 10. ACEX 1K Cascade Chain Operation AND Cascade Chain d[3..0] d[7..4] d[(4 n – 1)..(4 n – 4)] Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Cascade Chain With the cascade chain, the ACEX 1K architecture can implement functions that have a very wide fan-in. Adjacent LUTs can be used to compute portions of the function in parallel; the cascade chain serially connects the intermediate values. The cascade chain can use a logical AND or logical OR (via De Morgan’ ...
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... LE operating mode for optimal performance. The architecture provides a synchronous clock enable to the register in all four modes. The MAX+PLUS II software can set DATA1 to enable the register synchronously, providing easy implementation of fully synchronous designs. Figure 11 shows the ACEX 1K LE operating modes. Preliminary Information Altera Corporation ...
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... Up/Down Counter Mode Carry-In data1 (ena) data2 (u/d) data3 (data) data4 (nload) Clearable Counter Mode Carry-In data1 (ena) data2 (nclr) data3 (data) data4 (nload) Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Cascade-In LUT Cascade-Out Cascade-In LUT LUT Cascade-Out Carry-Out Cascade-In 3-Input ...
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... Two 3-input LUTs are used; one generates the counter data, and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading. Data can also be loaded asynchronously with the clear and preset register control signals without using the LUT resources. Preliminary Information Altera Corporation ...
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... Preliminary Information Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Clearable Counter Mode The clearable counter mode is similar to the up/down counter mode, but it supports a synchronous clear instead of the up/down control. The clear function is substituted for the cascade-in signal in the up/down counter mode. Two 3-input LUTs are used ...
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... Preliminary Information Figure 12 Asynchronous Preset & Clear labctrl1 PRN D Q labctrl2 Chip-Wide Reset CLRN Asynchronous Load without Clear or Preset NOT labctrl1 (Asynchronous Load) data3 (Data) NOT Chip-Wide Reset PRN D Q CLRN shows examples PRN D Q CLRN PRN D Q CLRN Altera Corporation ...
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... Preliminary Information Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Asynchronous Clear The flipflop can be cleared by either LABCTRL1 or LABCTRL2. In this mode, the preset signal is tied to VCC to deactivate it. Asynchronous Preset An asynchronous preset is implemented as an asynchronous load, or with an asynchronous clear. If DATA3 is tied to VCC, asserting LABCTRL1 asynchronously loads a one into the register ...
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... LABs. For example one LAB can drive the row and column channels normally driven by a particular LE in the adjacent LAB in the same row, and vice versa. This flexibility enables routing resources to be used more efficiently. Preliminary Information Figure 13 shows the ACEX 1K LAB. Altera Corporation ...
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... Figure 13. ACEX 1K LAB Connections to Row & Column Interconnect Row Channels Each LE can drive two row channels Altera Corporation ACEX 1K Programmable Logic Family Data Sheet At each intersection, six row channels can drive column channels. Each LE can switch interconnect access with the adjacent LAB ...
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... Each LAB is labeled according to its location: a letter represents the row and a number represents the column. For example, LAB row B, column 3. Preliminary Information Channels per Columns Row 144 24 216 36 216 36 312 52 Altera Corporation Channels per Column ...
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... Preliminary Information Figure 14. ACEX 1K Interconnect Resources I/O Element (IOE) IOE IOE Row LAB Interconnect A1 Column Interconnect IOE IOE LAB B1 Altera Corporation ACEX 1K Programmable Logic Family Data Sheet IOE IOE IOE IOE LAB LAB A2 LAB LAB B2 IOE IOE IOE IOE I/O Element An IOE contains a bidirectional I/O buffer and a register that can be used ...
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... VCC OE[7..0] Programmable Delay VCC CLK[1..0] CLK[3..2] VCC ENA[5..0] VCC CLRN[1..0] Chip-Wide VCC Chip-Wide Preliminary Information OE Register D Q ENA CLRN Reset Chip-Wide Output Enable Output Register D Q ENA Open-Drain CLRN Output Slew-Rate Control Reset Input Register D Q ENA CLRN Reset Altera Corporation ...
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... Preliminary Information Altera Corporation ACEX 1K Programmable Logic Family Data Sheet On all ACEX 1K devices, the input path from the I/O pad to the FastTrack Interconnect has a programmable delay element that can be used to guarantee a zero hold time. Depending on the placement of the IOE relative to what it is driving, the designer may choose to turn on the programmable delay to ensure a zero hold time or turn it off to minimize setup time ...
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... EP1K30 EP1K50 Row A Row A Row B Row B Row C Row D Row D Row F Row E Row H Row F Row J Row A Row A Row B Row C Row C Row E Row D Row G Row E Row I Row F Row J EP1K100 Row A Row C Row E Row L Row I Row K Row F Row D Row B Row H Row J Row G Altera Corporation ...
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... Up to eight IOEs connect to each side of each row channel (see Figure 16. ACEX 1K Row-to-IOE Connections Row FastTrack Interconnect n Note: (1) The values for m and n are shown in Table 8 Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Figure Note ( Each IOE is driven by an m-to-1 multiplexer. ...
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... ACEX 1K column-to-IOE interconnect resources. Table 9. ACEX 1K Column-to-IOE Interconnect Resources Channels per Column (n) Column Channels per Pin (m) Device EP1K10 EP1K30 EP1K50 EP1K100 Preliminary Information Each IOE is driven by a m-to-1 multiplexer IOE1 m IOE1 m Table Altera Corporation ...
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... Preliminary Information SameFrame Pin-Outs Altera Corporation ACEX 1K Programmable Logic Family Data Sheet ACEX 1K devices support the SameFrame pin-out feature for FineLine BGA packages. The SameFrame pin-out feature is the arrangement of balls on FineLine BGA packages such that the lower-ball- count packages form a subset of the higher-ball-count packages. ...
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... The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and ClockBoost circuitry. When the dedicated clock pin is driving the ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device. Preliminary Information 256-Pin FineLine BGA 484-Pin FineLine BGA (1) ( Altera Corporation ...
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... The t parameter refers to the nominal input clock period; the t I period. Altera Corporation ACEX 1K Programmable Logic Family Data Sheet For designs that require both a multiplied and non-multiplied clock, the clock trace on the board can be connected to the GCLK1 pin. In the MAX+PLUS II software, the GCLK1 pin can feed both the ClockLock and ClockBoost circuitry in the ACEX 1K device ...
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... OUTDUTY generated clock 38 and 12 summarize the ClockLock and ClockBoost parameters Condition (1) t <100 INCLKSTB t < 50 INCLKSTB Preliminary Information Min Typ Max Unit 180 MHz 16 90 MHz 25,000 PPM (2) 100 10 (4) 250 200 ( Altera Corporation µ ...
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... The t specification is measured under long-term observation. The maximum value for t JITTER t is lower than 50 ps. INCLKSTB I/O Configuration Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Condition (1) t INCLKSTB t INCLKSTB value is less than the time required for configuration. LOCK ...
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... ACEX 1K devices in all packages to interface with systems of differing supply voltages. These devices have one set of V pins for internal operation and input buffers (VCCINT), and another set for I/O output drivers (VCCIO). Preliminary Information is CCIO is 2 pin CCIO CC Altera Corporation ...
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... Preliminary Information Power Sequencing & Hot-Socketing Altera Corporation ACEX 1K Programmable Logic Family Data Sheet The VCCINT pins must always be connected to a 2.5-V power supply. With a 2.5-V V level, input voltages are compatible with 2.5-V, 3.3-V, and CCINT 5.0-V inputs. The VCCIO pins can be connected to either a 2.5-V or 3.3-V power supply, depending on the output requirements ...
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... IDCODE information for ACEX 1K devices. Table 15. ACEX 1K Boundary-Scan Register Length Device EP1K10 EP1K30 EP1K50 EP1K100 Preliminary Information TM Standard Test and 14. Description Boundary-Scan Register Length (1) 690 798 1,050 Tables 15 and 16 Altera Corporation ...
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... Contact Altera Applications. (2) The most significant bit (MSB the left. (3) The least significant bit (LSB) for all JTAG IDCODEs Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Note (2) IDCODE (32 Bits) Part Number (16 Bits) (1) 0001 0000 0011 0000 0001 0000 0101 0000 0000 0001 0000 0000 ACEX 1K devices include weak pull-up resistors on the JTAG pins ...
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... Update register clock to output JSCO t Update register high impedance to valid output JSZX t Update register valid output to high impedance JSXZ Preliminary Information t JPH t JPXZ t JSXZ Parameter Min Max Unit 100 Altera Corporation ...
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... Ambient temperature AMB T Junction temperature J Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Each ACEX 1K device is functionally tested. Complete testing of each configurable static random access memory (SRAM) bit and all logic functionality ensures 100% yield. AC test measurements for ACEX 1K devices are made under conditions equivalent to those shown in Figure 21 ...
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... V CCIO 0 70 – –40 100 40 40 Notes (6), (7) Typ Max 5.75 (8) CCIO 0.8, 0.3 ´ V (8) CCIO 2.4 – 0.2 CCIO 2.1 2.0 1.7 Altera Corporation Unit ° C ° C ° C ° Unit ...
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... Input pin leakage current I I Tri-stated I/O pin leakage OZ current I V supply current (standby) CC0 CC R Value of I/O pin pull-up CONF resistor before and during configuration Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Conditions Min DC, OL (10 3.00 V CCIO I = 0.1 mA DC, OL (10 ...
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... 1.0 MHz 1.0 MHz 1.0 MHz OUT Sheet. must rise monotonically 2.5 V, and 3.3 V. CCINT CCIO Preliminary Information Min Max and V CCINT CCIO and V meet the relationship CCIO CCINT by an external source. CCIO Altera Corporation Unit are ...
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... Preliminary Information Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Figure 22 shows the required relationship between V satisfy 3.3-V PCI compliance. Figure 22. Relationship between V 2.7 V (V) CCINT II 2.5 2.3 3.0 Figure 23 shows the typical output drive characteristics of ACEX 1K devices with 3.3-V and 2.5-V V 3.3-V PCI Local Bus Specification, Revision 2.2 (when VCCIO pins are connected to 3 ...
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... The Timing Analyzer provides point- to-point timing delay information, setup and hold time analysis, and device-wide performance analysis. Preliminary Information Output Voltage ( LUT ) 2.5 V CCINT V = 3.3 V CCIO Room Temperature Altera Corporation ...
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... Figure 24. ACEX 1K Device Timing Model Dedicated Clock/Input Figure 25. ACEX 1K Device LE Timing Model Carry-In Data-In Control-In Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Figure 24 shows the overall timing model, which maps the possible paths to and from the various elements of the ACEX 1K device. Interconnect Logic ...
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... WASU t WAH RASU t RAH Preliminary Information Output Delays Delays t IOCO t OD1 t IOCOMB t OD2 t IOSU t OD3 t IOH IOCLR t ZX1 t ZX2 t ZX3 t INREG Output Register EAB Output Delays Delay t t EABCO EABOUT t EABBYPASS t EABSU t EABH t EABCH t EABCL Data-Out Altera Corporation ...
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... LE register preset delay PRE t LE register clear delay CLR t Minimum clock high time from clock pin CH t Minimum clock low time from clock pin CL Altera Corporation ACEX 1K Programmable Logic Family Data Sheet OE Register PRN D Q CLRN Output Register PRN D Q CLRN ...
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... Address access delay (including the read enable to output delay Note (1) Parameter = V CCIO = low voltage CCIO = V CCIO = low voltage CCIO Note (1) Parameter Preliminary Information Conditions ( CCINT ( ( (2) CCINT ( (4) Conditions Altera Corporation ...
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... EAB address setup time before rising edge of write pulse when not using EABWASU input registers t EAB address hold time after falling edge of write pulse when not using input EABWAH registers t EAB write enable to data output valid delay EABWO Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Note (1) Parameter Notes (1), (6) Parameter Conditions (5) ...
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... These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing analysis are required to determine actual worst-case performance. 56 Note (1) Parameter = 3.3 V ± 10% for commercial or industrial use in ACEX 1K devices = 2.5 V ± 0.125 V for commercial or industrial use in ACEX 1K devices. = 2 5.0 V. Preliminary Information Conditions (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) (7) Altera Corporation ...
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... Contact Altera Applications for test circuit specifications and test conditions. (3) These timing parameters are sample-tested only. (4) This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local Bus Specification, Revision 2.2. Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Tables 27 through 29 describe the ACEX 1K external timing parameters and their symbols ...
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... Tables 30 through 36 show EP1K10 device internal and external timing parameters. All timing specifications for EP1K10 are preliminary. Speed Grade -1 -2 Max Min 0.6 0.5 0.7 0.5 0.6 0.2 0.5 0.2 0.8 0.5 0.5 0.5 0.6 1.1 0.5 0.5 2.5 2.5 Preliminary Information Note (1) -3 Max Min Max 0.8 1.1 0.6 0.8 0.8 1.1 0.6 0.8 0.7 0.9 0.2 0.3 0.5 0.8 0.2 0.3 0.9 1.2 0.6 0.8 0.6 0.7 0.6 0.7 0.8 1.5 0.6 0.8 0.6 0.8 3.0 3.0 Unit Altera Corporation ...
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... Table 31. EP1K10 Device IOE Timing Microparameters Symbol Min t IOD t IOC t IOCO t IOCOMB t 2.2 IOSU t 0.5 IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Speed Grade -1 -2 Max Min Max 2.4 0.3 0.2 0.5 2.6 0.6 0.2 1.1 0.6 3.0 1.1 1.1 0.6 3.0 5.0 3.0 3.0 Note (1) -3 Min Max 2.8 3.8 0.3 0.5 0.2 0.3 0.6 0.8 3.5 0.8 ...
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... 0.9 WDSU t 0.1 WDH t 1.7 WASU t 1.8 WAH t 3.1 RASU t 0.2 RAH EABOUT t 1.5 EABCH t 1.5 EABCL 60 Speed Grade -1 -2 Max Min Max 1.7 0.6 1.1 0.4 0.8 0.4 0.0 0.3 0.5 1.0 0.4 0.3 3.2 2.9 1.1 1.0 0.1 2.0 2.1 3.7 0.2 2.5 2.5 0.5 2.0 2.0 Preliminary Information Note (1) -3 Min Max 2.0 2.7 0.7 0.9 1.3 1.8 0.4 0.6 0.9 1.2 0.4 0.6 0.0 0.0 0.3 0.5 0.6 0.8 1.4 0.6 0.3 0.5 3.8 5.1 3.9 1.5 1.4 0.2 2.7 2.9 5.0 0.3 2.9 3.9 2.9 3.9 0.6 0.8 2.5 2.5 Unit Altera Corporation ...
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... Table 33. EP1K10 Device EAB Internal Timing Macroparameters Symbol Min t EABAA t 6.4 EABRCCOMB t 4.4 EABRCREG t 2.5 EABWP t 6.0 EABWCCOMB t 6.8 EABWCREG t EABDD t EABDATACO t 1.5 EABDATASU t 0.0 EABDATAH t 1.3 EABWESU t 0.0 EABWEH t 1.5 EABWDSU t 0.0 EABWDH t 3.0 EABWASU t 0.5 EABWAH t EABWO Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Speed Grade -1 -2 Max Min Max 6.4 7.6 5.1 2.9 7.0 7.8 5.7 0.8 1.7 0.0 1.4 0.0 1.7 0.0 3.6 0.5 5.1 Note (1) -3 Min Max 7.6 10.2 10.2 7.0 3.9 9.5 10.6 6.7 9.0 0.9 1.3 2.3 0.0 2.0 0.0 2.3 0.0 4.8 0.8 6.0 8.1 ...
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... PCICO 62 Speed Grade -1 -2 Max Min Max 4.1 0.9 1.8 3.9 0.9 0.1 1.3 0.7 2.0 3.3 3.8 0.1 0.3 Note (1) Speed Grade -1 -2 Max Min Max 7.5 3.6 0.0 3.5 2.0 2.6 0.0 2.5 0.5 4.2 0.0 6.0 2.0 Preliminary Information Note (1) -3 Min Max 4.6 5.9 1.0 1.3 1.9 2.3 4.6 6.2 1.0 1.3 0.1 0.2 1.3 1.8 0.8 1.5 2.1 3.3 3.4 5.1 4.1 5.3 0.1 0.2 0.3 0.5 -3 Min Max 9.5 12.5 4.8 0.0 4.5 2.0 7.1 – – 3.5 – – 6.4 0.0 7.5 2.0 10.2 Unit Unit Altera Corporation ...
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... Symbol Min t LUT t CLUT t RLUT t PACKED CICO t CGEN t CGENR t CASC COMB t 0.5 SU Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Speed Grade -1 -2 Max Min 2.2 0.0 3.5 2.0 5.8 2.0 4.7 2.0 2.5 0.5 5.3 0.5 4.2 0.5 Tables 22 through 29 Tables 37 through 43 show internal and external timing parameters for EP1K30 devices. ...
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... ZX2 t ZX3 t INREG t IOFD t INCOMB 64 Speed Grade -1 -2 Max Min Max 1.1 0.5 0.5 2.5 2.5 Speed Grade -1 -2 Max Min Max 2.4 0.3 0.2 0.5 2.6 0.6 0.2 1.1 0.6 3.0 1.1 1.1 0.6 3.0 5.0 3.0 3.0 Preliminary Information Note (1) -3 Min Max 1.5 0.6 0.8 0.6 0.8 3.0 3.0 Note (1) -3 Min Max 2.8 3.8 0.3 0.5 0.2 0.3 0.6 0.8 3.5 0.8 0.2 0.3 1.3 1.8 0.9 1.6 3.5 4.8 1.3 1.8 1.3 1.6 0.9 1.6 3.5 4.8 5.9 8.0 3.6 4.8 3.6 4.8 Unit Unit Altera Corporation ...
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... EABWE2 t EABRE1 t EABRE2 t EABCLK t EABCO t EABBYPASS t 0.9 EABSU t 0.4 EABH t EABCLR 2 0 0.9 WDSU t 0.1 WDH t 1.7 WASU t 1.8 WAH t 3.1 RASU t 0.2 RAH EABOUT t 1.5 EABCH t 1.5 EABCL Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Speed Grade -1 -2 Max Min Max 1.7 0.6 1.1 0.4 0.8 0.4 0.0 0.3 0.5 1.0 0.4 0.3 3.2 2.9 1.1 1.0 0.1 2.0 2.1 3.7 0.2 2.5 2.5 0.5 2.0 2.0 Note (1) -3 Min Max 2.0 2.7 0.7 0.9 1.3 1.8 0.4 0.6 0.9 1.2 0.4 0.6 0.0 0.0 0.3 0.5 0.6 0.8 1.4 ...
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... Min t EABAA t 6.4 EABRCCOMB t 4.4 EABRCREG t 2.5 EABWP t 6.0 EABWCCOMB t 6.8 EABWCREG t EABDD t EABDATACO t 1.5 EABDATASU t 0.0 EABDATAH t 1.3 EABWESU t 0.0 EABWEH t 1.5 EABWDSU t 0.0 EABWDH t 3.0 EABWASU t 0.5 EABWAH t EABWO 66 Speed Grade -1 -2 Max Min Max 6.4 7.6 5.1 2.9 7.0 7.8 5.7 0.8 1.7 0.0 1.4 0.0 1.7 0.0 3.6 0.5 5.1 Preliminary Information Note (1) -3 Min Max 7.6 10.2 10.2 7.0 3.9 9.5 10.6 6.7 9.0 0.9 1.3 2.3 0.0 2.0 0.0 2.3 0.0 4.8 0.8 6.0 8.1 Unit Altera Corporation ...
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... INSU , t (2), (3) 0.0 INH t (2), (3) 2.0 OUTCO (2), (4) t 2.0 INSU (2), (4) t 0.0 INH (2), (4) t 0.5 OUTCO t (2) 3.0 PCISU t (2) 0.0 PCIH t (2) 2.0 PCICO Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Speed Grade -1 -2 Max Min Max 4.1 0.9 1.8 3.9 0.9 0.1 1.3 0.7 2.0 3.3 3.8 0.1 0.3 Note (1) Speed Grade -1 -2 Max Min Max 8.0 3.6 0.0 3.5 2.0 2.6 0.0 2.5 0.5 4.2 0.0 6.0 2.0 Note (1) -3 Min Max 4 ...
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... Speed Grade -1 -2 Max Min 0.6 0.5 0.7 0.5 0.6 0.2 0.5 0.2 0.8 0.5 0.5 0.5 0.6 Preliminary Information Notes (1), (2) -3 Max Min Max 3.6 0.0 4.5 2.0 7.1 6.3 2.0 8.0 5.3 2.0 7.2 3.5 – – 5.8 – – 4.8 – – in this data sheet. Note (1) -3 Max Min Max 0.8 1.1 0.6 0.8 0.8 1.1 0.6 0.8 0.7 0.9 0.2 0.3 0.5 0.8 0.2 0.3 0.9 1.2 0.6 0.8 0.6 0.7 0.6 0.7 0.8 Unit Unit Altera Corporation ...
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... Symbol Min t IOD t IOC t IOCO t IOCOMB t 2.2 IOSU t 0.5 IOH t IOCLR t OD1 t OD2 t OD3 ZX1 t ZX2 t ZX3 t INREG t IOFD t INCOMB Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Speed Grade -1 -2 Max Min Max 1.1 0.5 0.5 2.5 2.5 Speed Grade -1 -2 Max Min Max 2.4 0.3 0.2 0.5 2.6 0.6 0.2 1.1 0.6 3.0 1.1 1.1 0.6 3.0 5.0 3.0 3.0 Note (1) -3 Min Max 1 ...
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... 0.9 WDSU t 0.1 WDH t 1.7 WASU t 1.8 WAH t 3.1 RASU t 0.2 RAH EABOUT t 1.5 EABCH t 1.5 EABCL 70 Speed Grade -1 -2 Max Min Max 1.7 0.6 1.1 0.4 0.8 0.4 0.0 0.3 0.5 1.0 0.4 0.3 3.2 2.9 1.1 1.0 0.1 2.0 2.1 3.7 0.2 2.5 2.5 0.5 2.0 2.0 Preliminary Information Note (1) -3 Min Max 2.0 2.7 0.7 0.9 1.3 1.8 0.4 0.6 0.9 1.2 0.4 0.6 0.0 0.0 0.3 0.5 0.6 0.8 1.4 0.6 0.3 0.5 3.8 5.1 3.9 1.5 1.4 0.2 2.7 2.9 5.0 0.3 2.9 3.9 2.9 3.9 0.6 0.8 2.5 2.5 Unit Altera Corporation ...
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... Table 47. EP1K50 Device EAB Internal Timing Macroparameters Symbol Min t EABAA t 6.4 EABRCCOMB t 4.4 EABRCREG t 2.5 EABWP t 6.0 EABWCCOMB t 6.8 EABWCREG t EABDD t EABDATACO t 1.5 EABDATASU t 0.0 EABDATAH t 1.3 EABWESU t 0.0 EABWEH t 1.5 EABWDSU t 0.0 EABWDH t 3.0 EABWASU t 0.5 EABWAH t EABWO Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Speed Grade -1 -2 Max Min Max 6.4 7.6 5.1 2.9 7.0 7.8 5.7 0.8 1.7 0.0 1.4 0.0 1.7 0.0 3.6 0.5 5.1 Note (1) -3 Min Max 7.6 10.2 10.2 7.0 3.9 9.5 10.6 6.7 9.0 0.9 1.3 2.3 0.0 2.0 0.0 2.3 0.0 4.8 0.8 6.0 8.1 ...
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... PCICO 72 Speed Grade -1 -2 Max Min Max 4.6 0.9 1.5 3.9 0.9 0.1 1.3 1.6 2.9 4.2 4.3 0.1 0.3 Note (1) Speed Grade -1 -2 Max Min Max 8.0 3.6 0.0 3.5 2.0 2.6 0.0 2.5 0.5 4.2 0.0 6.0 2.0 Preliminary Information Note (1) -3 Min Max 5.1 6.4 1.0 1.3 1.9 2.3 4.6 6.2 1.0 1.3 0.1 0.2 1.3 1.8 1.7 2.4 3.0 4.2 4.3 6.0 4.6 5.8 0.1 0.2 0.3 0.5 -3 Min Max 9.5 12.5 4.8 0.0 4.5 2.0 7.1 – – 3.5 – – 6.4 0.0 7.7 2.0 10.5 Unit Unit Altera Corporation ...
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... LUT t CLUT t RLUT t PACKED CICO t CGEN t CGENR t CASC COMB t 0 0.9 H Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Speed Grade -1 -2 Max Min 2.2 0.0 3.5 2.0 5.8 2.0 4.7 2.0 2.5 0.5 4.8 0.5 3.7 0.5 Tables 22 through 29 Tables 51 through 57 show the EP1K100 device internal and external timing parameters. Speed Grade ...
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... ZX2 t ZX3 t INREG t IOFD t INCOMB 74 Speed Grade -1 -2 Max Min Max 0.5 0.5 2.5 2.5 Speed Grade -1 -2 Max Min Max 2.4 0.3 0.2 0.5 2.6 0.6 0.2 1.1 0.6 3.0 1.1 1.1 0.6 3.0 5.0 3.0 3.0 Preliminary Information Note (1) -3 Min Max 0.6 0.8 0.6 0.8 3.0 3.0 Note (1) -3 Min Max 2.8 3.8 0.3 0.5 0.2 0.3 0.6 0.8 3.5 0.8 0.2 0.3 1.3 1.8 0.9 1.6 3.5 4.8 1.3 1.8 1.3 1.6 0.9 1.6 3.5 4.8 5.9 8.0 3.6 4.8 3.6 4.8 Unit Unit Altera Corporation ...
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... EABWE2 t EABRE1 t EABRE2 t EABCLK t EABCO t EABBYPASS t 0.9 EABSU t 0.4 EABH t EABCLR 2 0 0.9 WDSU t 0.1 WDH t 1.7 WASU t 1.8 WAH t 3.1 RASU t 0.2 RAH EABOUT t 1.5 EABCH t 1.5 EABCL Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Speed Grade -1 -2 Max Min Max 1.7 0.6 1.1 0.4 0.8 0.4 0.0 0.3 0.5 1.0 0.4 0.3 3.2 2.9 1.1 1.0 0.1 2.0 2.1 3.7 0.2 2.5 2.5 0.5 2.0 2.0 Note (1) -3 Min Max 2.0 2.7 0.7 0.9 1.3 1.8 0.4 0.6 0.9 1.2 0.4 0.6 0.0 0.0 0.3 0.5 0.6 0.8 1.4 ...
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... Min t EABAA t 6.4 EABRCCOMB t 4.4 EABRCREG t 2.5 EABWP t 6.0 EABWCCOMB t 6.8 EABWCREG t EABDD t EABDATACO t 1.5 EABDATASU t 0.0 EABDATAH t 1.3 EABWESU t 0.0 EABWEH t 1.5 EABWDSU t 0.0 EABWDH t 3.0 EABWASU t 0.5 EABWAH t EABWO 76 Speed Grade -1 -2 Max Min Max 6.4 7.6 5.1 2.9 7.0 7.8 5.7 0.8 1.7 0.0 1.4 0.0 1.7 0.0 3.6 0.5 5.1 6.0 Preliminary Information Note (1) -3 Min Max 7.6 10.2 10.2 7.0 3.9 9.5 10.6 6.7 9.0 0.9 1.3 2.3 0.0 2.0 0.0 2.3 0.0 4.8 0.8 8.1 Unit Altera Corporation ...
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... DRR t (2), (3) 3.1 INSU t (2), (3) 0.0 INH (2), (3) t 2.0 OUTCO (2), (4) t 2.1 INSU (2), (4) t 0.0 INH t (2), (4) 2.0 OUTCO t (2) 3.0 PCISU t (2) 0.0 PCIH t (2) 2.0 PCICO Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Speed Grade -1 -2 Max Min Max 3.5 0.6 2.0 1.7 0.6 0.1 1.7 1.2 2.9 4.6 4.3 0.1 0.3 Note (1) Speed Grade -1 -2 Max Min Max 9.0 12.0 3.7 0.0 3.7 2.0 2.7 0.0 2.7 0.5 6.2 0.0 6.0 2.0 Note (1) ...
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... Preliminary Information Notes (1), (2) -3 Max Min Max 4.4 0.0 4.4 2.0 6.3 6.1 2.0 8.3 5.6 2.0 8.1 3.4 – – 5.1 – – 4.6 – – in this data sheet. ´ CCACTIVE ) CC IO value, which depends on the IO Application Note 74 (Evaluating Unit Altera Corporation ...
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... Preliminary Information Altera Corporation ACEX 1K Programmable Logic Family Data Sheet The I value can be calculated with the following equation: CCACTIVE = K ´ f ´ N ´ tog I CCACTIVE MAX Where Maximum operating frequency in MHz MAX N = Total number of LEs used in the device tog = Average percent of LEs toggling at each clock LC (typically 12 ...
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... The ACEX 1K POR time does not exceed 50 µs; however, when configuring with a configuration device, the configuration device imposes a 200-ms delay that allows system power to stabilize before configuration. Preliminary Information 200 150 Supply 100 Frequency (MHz) 100 50 rises, the device initiates a CC 100 Altera Corporation ...
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... Passive serial (PS) Passive parallel asynchronous (PPA) Passive parallel synchronous (PPS) JTAG Altera Corporation ACEX 1K Programmable Logic Family Data Sheet During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. Together, the configuration and initialization processes are called command mode ...
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... Preliminary Information 208-Pin PQFP EP1K30 EP1K50 EP1K100 108 107 52 105 155 2 19 154 3 206 204 208 207 16 10 166 164 162 161 159 158 157 156 153 78, 80, 182, 184 79, 183 79 Altera Corporation ...
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... CS (4) RDYnBSY (4) CLKUSR Altera Corporation ACEX 1K Programmable Logic Family Data Sheet Note (1) 144-Pin TQFP EP1K30 EP1K50 42 122 128 16, 50, 75, 85, 103, 127 5, 24, 45, 61, 71, 94, 115, 134 53 6, 15, 25, 40, 52, 58, 66, 84, 93, 104, 123, 129, 139 57 ...
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... A9 P12 D8 C9 E11, F5, F7, F9, F12, H6, H7, H10, J7, J10, J11, K9, L5, L7, L12, M11, R2 D12, E6, F8, F10, G6, G8, G11, H11, J6, K6, K8, K11, L10, M6, N12 L9 A3, A14, C7, E5, E12, F6, F11, G7, G9, G10, H8, H9, J8, J9, K5, K7, K10, L1, L6, L11, M5, M12 T8 – 186 Altera Corporation ...
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... DATA0 (2) TDI (2) TDO (2) TCK (2) TMS (2) TRST Dedicated Inputs Dedicated Clock Pins (7) GCLK1 (8) LOCK (3) DEV_CLRn (3) DEV_OE Altera Corporation ACEX 1K Programmable Logic Family Data Sheet 484-Pin FineLine BGA EP1K50 U4 V4 W19 T7 E5 F18 K19 E4 E19 E17 F17 D19 D18 K17 G18 ...
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... N10, N13, P4, P9, P14, R8, R15, R22, T1, V3, W20, Y1, Y2, Y3, Y21, Y22, AA1, AA6, AA22, AB11, AB16 W11 A2, A3, A4, A5, B3, B4, B10, C17, F2, J2, K2, L2, N1, P20, P22, R3, T20, T21, U1, W22, Y16, AA15, AB3, AB4, AB5, AB7, AB15, AB17, AB18, AB19, AB20 333 Altera Corporation ...
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... GNDINT, respectively. (10) The user I/O pin count includes dedicated input pins, dedicated clock pins, and all I/O pins. Revision History Altera Corporation ACEX 1K Programmable Logic Family Data Sheet The information contained in the ACEX 1K Programmable Logic Family Data Sheet version 1.01 supersedes information published in previous versions ...
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... San Jose, CA 95134 Jam, MasterBlaster, MAX, MAX+PLUS, MAX+PLUS II, MegaCore, MultiVolt, and SameFrame are trademarks and/or service marks of Altera Corporation in the United States and other countries. Altera acknowledges the (408) 544-7000 trademarks of other organizations for their respective products or services mentioned in this document. Altera http://www ...