MAX9726BETP+ Maxim Integrated Products, MAX9726BETP+ Datasheet - Page 13

• Manufacturer Part Number: MAX9726BETP+
• Description: IC AMP AUDIO .124W STER 20TQFN
• Manufacturer: Maxim Integrated Products
• Series: DirectDrive™r
• Type: Class ABr

Specifications of MAX9726BETP+

• Output Type: Headphones, 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 124mW x 2 @ 16 Ohm
• Voltage - Supply: 2.7 V ~ 5.5 V
• Features: Bass Boost, Depop, I²C, Mute, Short-Circuit and Thermal Protection, Shutdown, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 20-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse since changes in SDA while SCL is
high are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I
SDA and SCL idle high when the bus is not in use. A
master device initiates communication by issuing a
START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is a
low-to-high transition on SDA while SCL is high (Figure
5). A START condition from the master signals the
beginning of a transmission to the MAX9726. The mas-
ter terminates transmission, and frees the bus, by issu-
ing a STOP condition. The bus remains active if a
REPEATED START condition is generated instead of a
STOP condition.
The MAX9726 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition.
Figure 4. START, STOP, and REPEATED START Conditions
Table 1. MAX9726 Slave Address with Read/Write Bit
2
C bus is not busy.
SDA
SCL
MAX9726A
MAX9726B
PART
S
______________________________________________________________________________________
A6 (MSB)
BassMax, I
DirectDrive, Headphone Amplifier with
1
1
START and STOP Conditions
Sr
Early STOP Conditions
A5
0
0
Bit Transfer
P
2
A4
0
0
C, Volume and Gain Control
A3
The slave address is defined as the seven most signifi-
cant bits (MSBs) of the serial data transmission. The
first byte of information sent to the MAX9726 after the
START condition must contain the slave address and
R/W bit (see Table 1). The MAX9726 is a slave device
only capable of being written to. The sent R/W bit must
always be set to zero when configuring the MAX9726.
The MAX9726 acknowledges the receipt of its address
even if R/W is set to 1. However, the MAX9726 does not
drive SDA. Addressing the MAX9726 with R/W set to 1
causes the master to receive all ones regardless of the
contents of the command register.
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9726 uses to handshake receipt each byte of data
(see Figure 6). The MAX9726 pulls down SDA during
the master generated 9th clock pulse. The SDA line
must remain stable and low during the high period of
the acknowledge clock pulse. Monitoring ACK allows
for detection of unsuccessful data transfers. An unsuc-
cessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master may
reattempt communication.
Figure 5. Acknowledge Bit
1
1
SDA
SCL
CONDITION
START
A2
1
1
1
2
A1
0
0
NOT ACKNOWLEDGE
ACKNOWLEDGE
A0
8
ACKNOWLEDGMENT
CLOCK PULSE FOR
0
1
Slave Address
Acknowledge
9
R/W
0
0
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