ML6652EM Micro Linear, ML6652EM Datasheet

no-image

ML6652EM

Manufacturer Part Number
ML6652EM
Description
Manufacturer
Micro Linear
Datasheet
The ML6652 is a low cost multi-function / multi-standard
single chip Media Converter that provides 10Mbps and
100Mbps signal conversion between twisted pair and fiber
optic Ethernet technologies. The device supports
conversion between:
The device supports 10Mbps and 100Mbps operating data
rates with Auto-Negotiation using 850nm or 1300nm
optics. One or both of the fiber optic and twisted pair
interfaces can be interfaced to industry standard miniature
fiber optic components or Physical Media Dependent
(PMD) modules using Positive Emitter Coupled Logic/Low
Voltage Positive Emitter Coupled Logic (PECL/LVPECL)
compatible modes. Support of other wavelengths is
possible using the PECL/LVPECL interface.
• Single/Multi Port 10/100 Auto-Negotiating Media
• Single/Multi Port 100BASE-FX/SX to100BASE-TX
• Single/Multi Port 10BASE-FL to 10BASE-T Media
• Single/Multi Mode Fiber Converters
• Fiber Optic Front-End for Network Interface Cards
• Fiber-To-The-Desk/Building/Factory Floor as well as
• Redundant Link Converters and Wavelength Converters
GENERAL DESCRIPTION
APPLICATIONS
Converters
Media Converters
Converters
(NICs), Repeaters, Bridges, Hubs and Switches
Home Connectivity Gateway/Demarcation Products
10BASE-T and 10BASE-FL
100BASE-TX and 100BASE-FX/SX
100BASE-FX and 100BASE-SX
FLP Bursts and FLNP Bursts
10/100Mbps Ethernet Fiber and Copper
Media Converter with Auto-Negotiation
January 2004
Final Datasheet
• Complete implementation of fiber optic and twisted pair
• Supports ISO/IEC 8802.3, IEEE 802.3 and TIA/EIA-785
• 850nm, 1300nm miniature fiber optic components and
• Supports 1:1 receiver/transmitter transformer ratio for
• Low latency
• Integrated voltage and current references
• Integrated twisted pair output wave shaping eliminates
• Integrated twisted pair 10BASE-T input filter and
• Serial Management Interface
• Full and Half Duplex with Auto-Negotiation
• Integrated LED Driver
• Integrated Data Quantizer
• Small 44-Pin TQFP and LPCC/QFN
• Low 3.3V power supply
• Integrated Link Integrity Warning (LIW)
FEATURES
media interface
Industry Standards, including full Auto-Negotiation for
twisted pair and fiber optic media
PMD modules
twisted pair
external filtering
100BASE-TX equalizer with baseline wander correction
circuit
ML6652
DS6652-F-02

Related parts for ML6652EM

ML6652EM Summary of contents

Page 1

Ethernet Fiber and Copper Media Converter with Auto-Negotiation GENERAL DESCRIPTION The ML6652 is a low cost multi-function / multi-standard single chip Media Converter that provides 10Mbps and 100Mbps signal conversion between twisted pair and fiber optic Ethernet technologies. The ...

Page 2

... Order Information .......................................................................................................................................................... 28 WARRANTY Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this document ...

Page 3

BLOCK DIAGRAM 3 January 2004 Final Datasheet ML6652 GNDB GNDQ VCCQ GNDFC VCCFC VCCL GNDL VCCD GNDD GNDE VCCE GNDT MDIO MDC DUPLEX SPEED AD10 AD32 AD4LIW PECLQU PECLTP TPOUTOFF# FOOUTOFF# PWRDWN# BCKLINK TPINSPD TPANDT FOINSPD FOANDT DS6652-F-02 ...

Page 4

PIN CONFIGURATION PIN DESCRIPTIONS Signal names followed by "#" indicate active low input. Pin No. Signal Name CONFIGURATION 4 AD4LIW I 5 AD32 I 4 Description Sets the value of the Physical Layer (PHY) address bit 4 ...

Page 5

PIN DESCRIPTIONS (continued) Pin No. Signal Name AD10 I Pin Name AD4LIW Input Level LIW Function PHYAD4 Bit 0 Disabled 1/3 of VCC Enabled 2/3 of VCC Enabled VCC Disabled 7 PECLTP I PECLTP Interfaces at ...

Page 6

PIN DESCRIPTIONS (continued) Pin No. Signal Name PECLQU I PECLQU Interfaces at Voltage FOINP/FOINN and IOUT/IOUT# 0 Quantizer and LED Driver 1/3 of VCC PECL/LVPECL 2/3 of VCC Quantizer and LED Driver VCC Quantizer and LED ...

Page 7

PIN DESCRIPTIONS (continued) Pin No. Signal Name SPEED I SPEED Voltage 0 VCC/2 VCC Mode Forced 10 10Mbps data rate only available. The Duplex mode is selected by the link partner. Forced 100 100Mbps data rate ...

Page 8

PIN DESCRIPTIONS (continued) Pin No. Signal Name CONTROL 13 TPOUTOFF# I (CMOS) 14 FOOUTOFF# I (CMOS) 24 PWRDWN# I (CMOS) DATA SIGNAL INPUT/OUTPUT 1 TPOUTP O 3 TPOUTN O 38 RTTP I 10 TPINP I 11 TPINN ...

Page 9

PIN DESCRIPTIONS (continued) Pin No. Signal Name Input from transformer circuit Pulse H1019 or equiv. 37 REQSD I 39 SDTH I 21 IOUT O 22 IOUT Description 10 100Ω 11 Figure 1. Twisted Pair Interface ...

Page 10

PIN DESCRIPTIONS (continued) Pin No. Signal Name RTOP O 33 FOINP I 32 FOINN I 30 CQOS 29 SDFO I 10 Description implemented, a 1kΩ off-chip resistor should be connected to ground and a 1nF capacitor ...

Page 11

PIN DESCRIPTIONS (continued) Pin No. Signal Name BACKUP LINK FUNCTION 40 BCKPLINK I/O LED STATUS 41 TPINSPD O 42 FOINSPD O 43 TPANDT O 11 Description PECL/LVPECL Compatible Interface Mode: This input pin is connected to the ...

Page 12

PIN DESCRIPTIONS (continued) Pin No. Signal Name LED STATUS (CONTINUED) 44 FOANDT O MANAGEMENT INTERFACE 16 MDIO 17 MDC REFERENCE CLOCK 18 REFCLK POWER AND GROUND 2 GNDT 12 GNDE 15 GNDD 20 GNDL 28 GNDFC 34 ...

Page 13

GENERAL DESCRIPTION The ML6652 Fast Ethernet Media Converter provides signal conversion between the following standards: • 10BASE-T to 10BASE-FL; (10Mbps twisted pair copper media and 10Mbps 850nm fiber media) • Proprietary 10BASE-T to 10BASE-1300nm Fiber; (10Mbps twisted pair copper media ...

Page 14

FUNCTIONAL DESCRIPTION DEVICE CONFIGURATION Configuring the ML6652 Media Converter is accomplished through input configuration pins or bits in management control register 30. Configuration pins AD4LIW, AD32 and AD10 determine the PHY address used with the serial management interface consisting of ...

Page 15

FUNCTIONAL DESCRIPTION SPEED SELECTION The Operating modes, FORCED, TRANSPARENT and NON-TRANSPARENT are chosen at power up by setting of the DUPLEX and SPEED pins. Thereafter the operating modes may be set by toggling bits in management register 30. DUPLEX and ...

Page 16

OPERATING MODES Operating Modes are: 1) Forced 10 0 (zero) Volt input on SPEED (or the equivalent Reg. 30 settings) enables only FORCED 10Mbps operation. 100Mbps and Auto-Negotiation are disabled. Link Integrity Warning (LIW) can also be enabled. 2) Forced ...

Page 17

OPERATING MODES TRANSPARENT or NON-TRANSPARENT Mode of operation. Transparent Mode is the default mode of operation for the ML6652 when DUPLEX input is VCC this mode, the control circuit implements the state diagrams of the Auto-Negotiation sub-layer defined ...

Page 18

OPERATING MODES (without thoroughly understanding your PCB layout power up dynamics the safest course is to make short connections and do not to add decoupling capacitors to these pins). When Pin 7 (PECLTP) and Pin 8 (PECLQU) are connected to ...

Page 19

OPERATING MODES resistor is connected to ground and a 1nf capacitor is connected to IOUT to determine the peaking current waveform. If peaking is not implemented, IOUT# should be connected directly to VCC. The preferred mode of operation is PECL/LVPECL ...

Page 20

OPERATING MODES ...

Page 21

CONTROL REGISTERS Control Registers Register 31 ADDR 11111 (bin) 1F (hex) All bits are R/W All bits default to 0 Bit Name Description 15 Power Down Setting bit to 1 powers down all circuits and resets all control logic. Register ...

Page 22

CONTROL REGISTERS Control Registers Register 30 Continued Bit Name Description 9 SINGLESPEED Setting this bit to 1 enables only a single data rate 8 SEL 10Mbps Setting bit to 1 and SINGLESPEED <30.9> enables only 10Mbps data rate ...

Page 23

STATUS REGISTERS Status Registers Register 27 ADDR 11011 (bin) 1B (hex) All bits are Read Only Bit Name Description 15 FOFORCELO This bit set high when the fiber optic input PLL follows the local oscillator 14 FOBADFREQ This bit set ...

Page 24

... OPERATING CONDITIONS Power Supply Voltage Range ............................ 3.3V ±5% All VCC supply pins must be within 0.1V of each other Operating Temperature Range ......................................... ML6652CH/ML6652CM ............................... 0°C to 70°C ML6652EH/ML6652EM ............................ -20°C to 85°C CONDITIONS RTTP= 2KΩ RTOP=1.4KΩ Current into all VCC pins RTOP=1.4KΩ Current into all VCC pins RTTP= 2KΩ ...

Page 25

ELECTRICAL TABLES (CONTINUED) SYMBOL PARAMETER 3-LEVEL CONFIGURATION INPUTS: SPEED AND DUPLEX High Input Level Middle Input Level Low Input Level 4-LEVEL CONFIGURATION INPUTS: PECLTP, PECLQU, AF4LIW, AD32, AD10 High Input Level Middle High Input Level Middle Low Input Level Low ...

Page 26

ELECTRICAL TABLES (CONTINUED) SYMBOL PARAMETER TWISTED PAIR RECEIVER: TPINP, TPINN, REQSD Common-Mode Voltage Differential Input Resistance REQSD Input Current TWISTED PAIR TRANSMITTER: TPOUTP, TPOUTN, RTTP Differential Peak Output Current Differential Current Error Differential Peak Output Current Average Total Output Current ...

Page 27

ELECTRICAL TABLES (CONTINUED) SYMBOL PARAMETER TWISTED PAIR RECEIVER: TPINP AND TPINN Signal Detect Assertion Threshold Signal Detect De-assertion Threshold Amplitude Sensitivity Threshold Packet Activity Assertion Threshold Packet Activity De-assertion Threshold TWISTED PAIR TRANSMITTER: TPOUTP AND TPOUTN Differential Rise and Fall ...

Page 28

... PART NUMBER TEMPERATURE RANGE ML6652CH 0°C to 70°C ML6652EH -20°C to 85°C ML6652CM 0°C to 70°C ML6652EM -20°C to 85°C Headquarters: 2050 Concourse Drive, San Jose, CA 95131 (408) 433-5200 www.microlinear.com 28 Package: H44-10 44-Pin ( 1mm) TQFP 0º - 8º 34 0.394 BSC ...

Related keywords