K4X51323PC-8GC3 Samsung, K4X51323PC-8GC3 Datasheet
K4X51323PC-8GC3
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K4X51323PC-8GC3 Summary of contents
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... K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Mobile-DDR SDRAM 16M x32 1 Preliminary Revision 0.6 October 2005 ...
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... K4X51323PC - 7(8)E/G Document Title 16M x32 Mobile-DDR SDRAM Revision History Revision No. History 0.0 - First version for target specification 0.1 - Insertion of PKG dimension of 90FBGA JEDEC Standard type. 0.2 - Preliminary Datasheet - Insertion DC Current value. 0.3 - Changing Frequency from DDR333/DDR266 to DDR266/DDR222. - Updating DC current value. - Changing expression of PKG dimension. 0.4 - Changing format with JEDEC standard type. ...
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... K4X51323PC - 7(8)E/G 16M x32 Mobile-DDR SDRAM FEATURES • 1.8V power supply, 1.8V I/O power • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • 1 /CS • 1 CKE • Differential clock inputs(CK and CK) • MRS cycle with address key programs ...
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... K4X51323PC - 7(8)E/G FUNCTIONAL BLOCK DIAGRAM Bank Select CK, CK ADD LCKE LRAS LCBR LWE CK, CK CKE CS 32 CK, CK Data Input Register Serial to parallel 64 2Mx64 2Mx64 2Mx64 2Mx64 Column Decoder Latency & Burst Length Programming Register LCAS LWCBR Timing Register RAS CAS WE 4 Preliminary ...
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... K4X51323PC - 7(8)E/G Package Dimension and Pin Configuration *1 < Bottom View < Top View > #A1 Ball Origin Indicator > DDQ C V SSQ D V DDQ E V SSQ CKE ...
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... K4X51323PC - 7(8)E/G Input/Output Function Description SYMBOL TYPE CK, CK Input Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from CK/CK. CKE Input Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers ...
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... K4X51323PC - 7(8)E/G Functional Description POWER POWER APPLIED ON PRECHARGE ALL BANKS EMRS MRS POWER DOWN WRITEA WRITE WRITEA WRITEA PRE DEEP CKEH POWER DOWN PARTIAL SELF REFRESH DEEP POWER DOWN REFS REFSX MRS IDLE REFA ALL BANKS PRECHARGED CKEL CKEH ACT CKEH ROW ...
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... K4X51323PC - 7(8)E/G Mode Register Definition Mode Register Set(MRS) The mode register is designed to support the various operating modes of DDR SDRAM. It includes Cas latency, addressing mode, burst length, test mode and vendor specific options to make DDR SDRAM useful for variety of applications. The default value of the mode register is not defined, therefore the mode register must be written in the power up sequence of DDR SDRAM ...
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... K4X51323PC - 7(8)E/G Burst address ordering for burst length Starting Burst Address Length (A3, A2, A1, A0) xxx0 2 xxx1 xx00 xx01 4 xx10 xx11 x000 x001 x010 x011 8 x100 x101 x110 x111 0000 10, 11, 12, 13, 14,15 0001 10, 11, 12, 13, 14,15, 0 ...
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... K4X51323PC - 7(8)E/G Extended Mode Register Set(EMRS) The extended mode register is designed to support partial array self refresh or driver strength control. EMRS cycle is not mandatory and the EMRS command needs to be issued only when either PASR used. The default state without EMRS command issued is half driver strength, and Full array refreshed ...
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... K4X51323PC - 7(8)E/G Internal Temperature Compensated Self Refresh (TCSR) Note : 1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the three temperature ranges ; 45 °C and 85 ° the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. ...
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... K4X51323PC - 7(8)E/G Absolute maximum ratings Parameter Voltage on any pin relative Voltage on V supply relative Voltage on V supply relative to V DDQ Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. ...
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... K4X51323PC - 7(8)E/G DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to V Parameter Symbol Operating Current tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH HIGH between valid commands; IDD0 (One Bank Active) address inputs are SWITCHING; data bus inputs are STABLE all banks idle, CKE is LOW HIGH, tCK = t CKmin ; address and control inputs are IDD2P SWITCHING ...
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... K4X51323PC - 7(8)E/G AC Operating Conditions & Timming Specification Parameter/Condition Input High (Logic 1) Voltage, all inputs Input Low (Logic 0) Voltage, all inputs Input Crossing Point Voltage, CK and CK inputs Note : 1. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. ...
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... K4X51323PC - 7(8)E/G AC Timming Parameters & Specifications Parameter Clock cycle time Row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Active delay Last data in to Read command Col. address to Col. address delay ...
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... K4X51323PC - 7(8)E/G Parameter Refresh interval time Mode register set cycle time Power down exit time CKE min. pulse width(high and low pulse width) Auto refresh cycle time Exit self refresh to active command Data hold from DQS to earliest DQ edge Data hold skew factor ...
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... K4X51323PC - 7(8)E/G Note : 1. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate (V/ns) 1.0 0.8 0.6 This derating table is used to increase t 2. Minimum 3CLK of tDAL(= tWR + tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP. 3. tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25°C). ...
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... K4X51323PC - 7(8)E/G AC Operating Test Conditions Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input signal minimum slew rate Output timing measurement reference level Output load condition 1.8V 13.9KΩ Output 20pF 10.6KΩ Figure.6 DC Output Load Circuit Input/Output Capacitance (V DD Parameter Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) Input capacitance( CK Data & ...
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... K4X51323PC - 7(8)E/G AC Overshoot/Undershoot Specification for Address & Control Pins Parameter Maximum peak Amplitude allowed for overshoot area Maximum peak Amplitude allowed for undershoot area Maximum overshoot area above VDD Maximum undershoot area below VSS V DD Volts ( Figure.8 AC Overshoot and Undershoot Definition for Address and Control Pins ...
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... K4X51323PC - 7(8)E/G Command Truth Table (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) COMMAND Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & ...
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... K4X51323PC - 7(8)E/G Functional Truth Table Current State CS RAS CAS PRECHARGE STANDBY ACTIVE STANDBY READ ...
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... K4X51323PC - 7(8)E/G Functional truth table Current State CS RAS CAS WRITE READ with AUTO PRECHARGE (READA WRITE with AUTO RECHARGE ...
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... K4X51323PC - 7(8)E/G Functional truth table Current State CS RAS CAS PRECHARGING L H (DURING tRP ROW L H ACTIVATING L H (FROM ROW ACTIVE tRCD WRITE L H RECOVERING L H (DURING tWR OR tCDLR ...
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... K4X51323PC - 7(8)E/G Functional truth table Current State CS RAS CAS RE FRESHING MODE REGISTER SETTING Address L X Burst Stop X BA, CA, A10 READ/WRITE H BA, RA Active L BA, A10 PRE/PREA ...
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... K4X51323PC - 7(8)E/G Functional truth table CKE CKE Current State CS n-1 n SELF REFRESHING POWER DOWN DEEP POWER DOWN ALL BANKS IDLE ...