SM5844AF Nippon Precision Circuits Inc, SM5844AF Datasheet

no-image

SM5844AF

Manufacturer Part Number
SM5844AF
Description
Manufacturer
Nippon Precision Circuits Inc
Datasheet
OVERVIEW
The
asynchronous sample rate converter LSI. It reads 16
or 20-bit word length input data, and writes 16, 18,
or 20-bit word length output data. It also features a
built-in digital deemphasis filter and digital
attenuator.
The SM5844AF operates from a 5 V supply, and is
available in 44-pin QFPs.
FEATURES
Functions
NIPPON PRECISION CIRCUITS LTD.
Left/right-channel processing (stereo)
Input sample rate (fsi) ranges
• 24 to 48 kHz (256fsi mode)
• 27 to 55 kHz (384fsi mode)
Output sample rate (fso) range
• 20 to 100 kHz
Sample rate conversion ratio (fso/fsi)
• 0.5 to 2.0 times
Asynchronous input and output timing (clock
inputs)
System clock inputs (input and output clocks
independent)
• 256fsi or 384fsi input system clock
• 256fso or 384fso output system clock
Deemphasis filter
• IIR-type filter
• 44.1, 48 or 32 kHz
Digital attenuator
• 11-bit data for 1025 levels
• Smooth, incremental attenuation change
• +12 dB gain shift function
Direct mute function
Through mode operation
• Input to output direct
Output data clocks (LRCO, BCKO)
• External input (slave mode)
• Output system clock generated internally
CMOS-level input/outputs
5 V (standard) single supply
44-pin QFP
Molybdenum-gate CMOS process
(master mode)
SM5844AF
is
a
digital
audio
signal,
Asynchronous Sample Rate Converter
APPLICATIONS
PINOUT
PACKAGE DIMENSIONS
Unit: mm
44-pin QFP
Digital audio equipment, sample rate conversion
(audiovisual amplifiers, CD-R, DAT, MD and 8
mm VTRs)
Commercial recording/editing equipment, sample
rate conversion
Input data jitter elimination
BCKI
IFM1
IFM2
ICKSL
LRCI
ICLK
DI
12.80 0.30
0.80
10.00
+ -
NIPPON PRECISION CIRCUITS—1
0.35 0.10
+ -
SM5844AF
0.60 0.20
+ -
TST2N
TST1N
STATE
VSS
RSTN
IISN
OW20N

Related parts for SM5844AF

SM5844AF Summary of contents

Page 1

... LSI. It reads 16 or 20-bit word length input data, and writes 16, 18, or 20-bit word length output data. It also features a built-in digital deemphasis filter and digital attenuator. The SM5844AF operates from supply, and is available in 44-pin QFPs. FEATURES Functions Left/right-channel processing (stereo) Input sample rate (fsi) ranges • ...

Page 2

... Output S/N ratio (theoretical values) S/N ratio Output signal word 16-bit input word length length 16 bits 94 bits 97 bits 97.7 dB SM5844AF Interfaces Input data format • 2s-complement, L/R alternating, serial • Normal format (non IIS sample rate Output data format • ...

Page 3

... Filter characteristic select TST1N TST2N OW18N Output format OW20N controller IISN SLAVE OCLK Output-stage divider OCKSL THRUN DMUTE Mute generator SM5844AF IFM1 IFM2 Input timing controller Output operation timing controller Dither Output-stage clock select LRCO BCKO BCKI DI Input data interface Arithmetic operations ...

Page 4

... S TAT SM5844AF Description Data input Input bit clock Input word clock (fsi) Input system clock input Input system clock (ICLK) select. 384fsi when HIGH, and 256fsi when LOW . Input format select ...

Page 5

... arameter Supply voltage range Operating temperature range SM5844AF Description Reset pin 0 V ground pin and LRCO mode set. Outputs (master mode) when LOW , and inputs (slave mode) when HIGH. DOUT through mode set. Normal mode when HIGH, and through mode when LOW . ...

Page 6

... P arameter -level clock pulsewidth HIGH-level clock pulsewidth Clock pulse cycle ICLK and OCLK timing ICLK OCLK t CWH SM5844AF = Condition 5 ...

Page 7

... HIGH-level pulsewidth pulse cycle Last BCKO rising edge to LRCO edge LRCO edge to first BCKO rising edge clock inputs exceeding 64fso cannot be detected, and will cause incorrect operation. SM5844AF ...

Page 8

... MLEN hold time -level pulsewidth MLEN HIGH-level pulsewidth 1. t and t are the input waveform transition times measured between 0. MDT, MCK, MLEN timing MDT t MDS MCK MLEN SM5844AF t BCY2 t BCWH2 t BL2 Rating typ t – – ...

Page 9

... delay time (OCKSL = HIGH DOUT and LRCO delay time SLAVE = HIGH (inputs arameter DOUT delay time SM5844AF – – ...

Page 10

... DOUT, BCKO, LRCO timing OCLK BCKO sbL1 sbL2 BCKO bdH bdL DOUT t bdH LRCO SM5844AF sbH1 sbH2 t BOWH t BOCY t bdL t LOCH t LROOY t BOWL t LOCL NIPPON PRECISION CIRCUITS—10 ...

Page 11

... Deemphasis filter frequency characteristic Phase 100 SM5844AF 48k 44.1k 44.1k 32k 0.400 0.450 0.500 Frequency (fs) 48.0, 44.1 and 32 kHz Attenuation 200 500 1k 2K Frequency (Hz) Up conversion 0.550 0.600 0.650 0 48.0 kHz 44.1 kHz 32 kHz – ...

Page 12

... When MCOM is HIGH, serial data received on MDT, MCK and MLEN sets the attenuation data and control flag data. When MCOM is LOW, the logic levels on FSI1, FSI2 and DEEM select the device function. SM5844AF W ord length Data position 16 bits Rear packed 20 bits ...

Page 13

... HIGH Not used MCK MLEN Figure 2. Mode flag data format (B1 = HIGH) SM5844AF latched into the mode register on the rising edge of the latch enable clock MLEN. The mode register addressed is determined by the 1st bit of the 12 data bits before MLEN goes HIGH. If this bit is LOW, then the data is read into the attenuation data register as shown in fi ...

Page 14

... SM5844AF Mode function select P arameter ...

Page 15

... 60.206 12.041 0.0085 400H (to 7FFH) 0 SM5844AF When the leading bit is 0 (B1 = LOW), the following 11 bits are read into the attenuation register and used as an unsigned integer in MSB first format. See figure ...

Page 16

... The time taken to reduce the gain from 0 dB ( (1024/fso), which corresponds to approximately 23.2 ms when fso = 44.1 kHz. Level Level 3 Gain Level 2 t Level 4 Figure 4. Attenuator operation example SM5844AF Level 5 Time NIPPON PRECISION CIRCUITS—16 ...

Page 17

... 20th Note that when THRUN is LOW, LRCO and BCKO are not guaranteed to be synchronized to the STATE output. SM5844AF automatically selected for output. Output data is in 20-bit front-packed format. Content 9 18th 1.0 times 2.0 times (1/2 conversion rate ratio) 0.5 times (2.0 conversion rate ratio) Selected fi ...

Page 18

... RSTN and VSS. Otherwise, a capacitor value should be chosen such that RSTN does not go HIGH until after LRCI and ICLK have stabilized. SM5844AF Output system clock (OCLK, OCKSL) The output system clock can be set to run at either 256fso or 384fso, where fso is the input frequency on LRCO ...

Page 19

... bits bits SM5844AF Output Timing Calculation The output timing is calculated to maintain the desired ratio between the output data cycle and the input data cycle. Filter Characteristic Selection Conversion rates from 0.5 to 2.0 times are supported using the following 4 filter types. ...

Page 20

... Audio data input timing (front-packed 20-bit word, IFM1 = HIGH, IFM2 = LOW) Left-channel data MSB BCKI LRCI All data bits after the LSB (20th bit) are ignored. Accordingly, more than 20 BCKI cycles are required. SM5844AF 1/fs Left-channel data LSB 1/fs ...

Page 21

... BCKO LRCO Audio data output timing (rear-packed 18-bit word) MSB DOUT 1 2 BCKO LRCO Audio data output timing (rear-packed 20-bit word) MSB DOUT 1 2 BCKO LRCO SM5844AF 1/fs Left-channel data MSB 1/fso Left-channel data LSB MSB 1/fso Left-channel data ...

Page 22

... State Data Output Timing State data output timing (IISN = HIGH) State data MSB STATE 1 2 BCKO LRCO State data output timing (IISN = LOW) State data MSB STATE 1 2 BCKO LRCO SM5844AF 1/fso LSB MSB 1/fso Left-channel data LSB MSB ...

Page 23

... OUTPUT 1/fs LRCI Serial data input t input LRCO 1/fso t INPUT SM5844AF been read out completely (on the rising edge of LRCO). The delay between input and output is given OUTPUT INPUT 49 ±2 Serial data output t – t ...

Page 24

... VCOOUT LRCK BCK DATA MODE EMP OCKSL 384fs 16.9344 MHz OCLK LRCO BCKO DOUT IISN OW18N OW20N THRUN SLAVE ICLK ICKSL LRCI BCKI SM5844AF DI MCOM MLEN/DEEM MDT/FSI1 1FM1 MCK/FSI2 1FM2 øA WCI BCI DIN DIT YM3613 SEL NIPPON PRECISION CIRCUITS—24 ...

Page 25

... OCLK= 59ns(fs= 44.1kHz), OCKSL= H(384fs), BCKO(64fso)= 354ns, OW20N LRCO BCKO DOUT 100ns 354ns SM5844AF When tbdH2, tbdL2 is maximum 100ns, ideal timing may not be attained for the following devise, depending on the OCLK cycle (example 1). Please use considering the timing in the following examples in the slave mode. ...

Page 26

... Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS LTD. SM5844AF NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2 chome Koto-ku, Tokyo 135-8430, Japan ...

Related keywords