SAF-C165-LM Siemens Semiconductor Group, SAF-C165-LM Datasheet
SAF-C165-LM
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SAF-C165-LM Summary of contents
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Microcomputer Components 16-Bit CMOS Single-Chip Microcontroller C165 Data Sheet 09.94 ...
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C16x-Family of High-Performance CMOS 16-Bit Microcontrollers Preliminary C165 16-Bit Microcontroller High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20-MHz CPU Clock 500 ns Multiplication (16 Enhanced Boolean Bit Manipulation Facilities Additional Instructions to Support HLL ...
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... Figure 1 Logic Symbol Ordering Information Type Ordering Code SAB-C165-RM Q67121-D... SAB-C165-LM Q67121-C862 SAF-C165-LM Q67121-C923 Note: The ordering codes (Q67121-D...) for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Semiconductor Group C165 Package Function P-MQFP-100-2 16-bit microcontroller with 2 KByte RAM and 4 KByte ROM Temperature range 0 to +70 ˚ ...
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Ordering Information Type Ordering Code SAB-C165-RF Q67121-D... SAB-C165-LF Q67121-C941 Note: The ordering codes (Q67121-D...) for the Mask-ROM versions are defined for each product after verification of the respective ROM code. Pin Configuration TQFP Package (top view) Figure 2 Semiconductor Group ...
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Pin Configuration MQFP Package (top view) Figure 3 Semiconductor Group C165 4 C165 ...
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Pin Definitions and Functions Symbol Pin Input (I) No. Output (O) P5.10 – 100 I P5. 100 XTAL1 7 I XTAL2 8 O P3.0 – ...
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Pin Definitions and Functions (cont’d) Symbol Pin Input (I) No. Output (O) P4.0 – 28, I/O P4 ... ... WR WRL READY 37 I ALE 38 ...
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Pin Definitions and Functions (cont’d) Symbol Pin Input (I) No. Output (O) PORT0: I/O P0L.0 – 43 – P0L.7, 50 P0H – P0H.7 60 PORT1: I/O P1L.0 – P1L.7, 68 P1H 70, P1H.7 ...
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Pin Definitions and Functions (cont’d) Symbol Pin Input (I) No. Output (O) P6.0 – I/O P6 ... ... P2.8 – I/O P2. ...
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Functional Description The architecture of the C165 combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the ...
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Memory Organization The memory space of the C165 is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire ...
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Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask ...
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The CPU disposes of an actual register context consisting wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be ...
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Interrupt System With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal program execution), the C165 is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of ...
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Source of Interrupt or PEC Service Request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 ...
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The C165 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...
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General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...
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Figure 6 Block Diagram of GPT1 Semiconductor Group 17 C165 ...
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Figure 7 Block Diagram of GPT2 Parallel Ports The C165 provides I/O lines which are organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable ...
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... Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’ ...
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Instruction Set Summary The table below lists the instructions of the C165 in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and ...
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Instruction Set Summary (cont’d) Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Semiconductor ...
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Special Function Registers Overview The following table lists all SFRs which are implemented in the C165 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the ...
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Special Function Registers Overview (cont’d) Name Physical 8-Bit Address Address CRIC b FF6A B5 H CSP FE08 04 H DP0L b F100 DP0H b F102 DP1L b F104 DP1H b F106 ...
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Special Function Registers Overview (cont’d) Name Physical 8-Bit Address Address P5 b FFA2 FFCC E6 H PECC0 FEC0 60 H PECC1 FEC2 61 H PECC2 FEC4 62 H PECC3 FEC6 63 H PECC4 FEC8 64 H ...
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Special Function Registers Overview (cont’d) Name Physical 8-Bit Address Address SSCRB F0B2 SSCRIC b FF74 BA H SSCTB F0B0 SSCTIC b FF72 B9 H STKOV FE14 0A H STKUN FE16 0B H SYSCON b ...
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Special Function Registers Overview (cont’d) Name Physical 8-Bit Address Address XP3IC b F19E ZEROS b FF1C The system configuration is selected during reset. Note: The Interrupt Control Registers XPnIC are prepared to control interrupt ...
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... Absolute Maximum Ratings Ambient temperature under bias ( SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165-RF ..................................... ˚C SAF-C165-LM............................................................................................................ – ˚C T Storage temperature ( ) ....................................................................................... – 150 ˚C ST Voltage on V pins with respect to ground ( CC Voltage on any pin with respect to ground ( Input current on any pin during overload condition.................................................. – Absolute sum of all input currents during overload condition ...
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Parameter Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (all other outputs) Output high voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) 1) Output high voltage (all other outputs) ...
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Notes 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2) The maximum current may be drawn while ...
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Testing Waveforms AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’. Timing measurements are made at Figure 9 Input Output Waveforms For timing purposes a port pin is no ...
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... AC Characteristics External Clock Drive XTAL1 +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165- -40 to +85 ˚C for SAF-C165-LM A Parameter Symbol Oscillator period TCL High time Low time t t Rise time t Fall time Figure 11 External Clock Drive XTAL1 ...
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... +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165- -40 to +85 ˚C for SAF-C165- (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 (for Port 6, CS) = 100 ALE cycle time = 6 TCL + 2 Parameter ALE high time ...
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Parameter Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR ALE falling edge low to Valid Data In CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW ...
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ALE CSx A23-A16 (A15-A8) BHE t Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 12-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group ...
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ALE t 38 CSx A23-A16 (A15-A8) BHE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 12-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group ...
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ALE CSx A23-A16 (A15-A8) BHE t Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 12-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group ...
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ALE t 38 CSx A23-A16 (A15-A8) BHE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 12-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group ...
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... +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165- -40 to +85 ˚C for SAF-C165- (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 (for Port 6, CS) = 100 ALE cycle time = 4 TCL + 2 Parameter ALE high time ...
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Parameter Address hold after RD, WR ALE falling edge low to Valid Data In CS hold after RD, WR ALE falling edge to RdCS, WrCS (with RW-delay) ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to ...
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ALE CSx A23-A16 A15-A0 BHE t Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 13-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group t 16 ...
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ALE t 38 CSx A23-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 13-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor ...
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ALE CSx A23-A16 A15-A0 BHE t Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 13-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group t 16 ...
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ALE t 38 CSx A23-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 13-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor ...
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... +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165- -40 to +85 ˚C for SAF-C165- (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 (for Port 6, CS) = 100 pF L Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time ...
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... MTTC waitstate this delay is zero. 7) The next external bus cycle may start here. Semiconductor Group READY 1) waitstate order to be safely synchronized. This is guaranteed C165 6) MUX/Tristate see 6) ...
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... +70 ˚C for SAB-C165-LM, SAB-C165-RM, SAB-C165-LF, SAB-C165- -40 to +85 ˚C for SAF-C165- (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 (for Port 6, CS) = 100 pF L Parameter HOLD input setup time to CLKOUT CLKOUT to HLDA high ...
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CLKOUT t 61 HOLD HLDA 1) BREQ CSx (On P6.x) Other Signals Figure 15 External Bus Arbitration, Releasing the Bus Notes 1) The C165 will complete the currently running bus cycle before granting bus access. 2) This is the first ...
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CLKOUT HOLD HLDA t 62 BREQ CSx (On P6.x) Other Signals Figure 16 External Bus Arbitration, (Regaining the Bus) Notes 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the ...