SAB-C515C-LM Siemens Semiconductor Group, SAB-C515C-LM Datasheet
SAB-C515C-LM
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SAB-C515C-LM Summary of contents
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Microcomputer Components 8-Bit CMOS Microcontroller C515C Data Sheet 07.97 ...
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C515C Data Sheet Revision History : Previous Releases : Page Subjects (changes since last revision) 4 SSC transfer rate at 10 MHz = 2.5 MHz 19 Figure reference corrected 52, 53 Power saving modes : description of hardware power down ...
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... CMOS Microcontroller Advance Information • Full upward compatibility with SAB 80C515A • 64k byte on-chip ROM (external program execution is possible) • 256 byte on-chip RAM • 2K byte of on-chip XRAM • 64K byte external data memory • Superset of the 8051 architecture with 8 datapointers • ...
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... RFI related improvements. With a maximum external clock rate of 10 MHz it achieves a 600 ns instruction cycle time ( MHz). The C515C is mounted in a P-MQFP-80 package. Ordering Information Type Ordering Code SAB-C515C-LM Q67121-C1066 SAF-C515C-LM Q67121-C1058 SAB-C515C-8RM Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (10 MHz) ...
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Figure 2 Logic Symbol Semiconductor Group 5 C515C 1997-07-01 ...
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Figure 3 C515C Pin Configuration (P-MQFP-80-1, Top View) Semiconductor Group 6 C515C 1997-07-01 ...
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Table 1 Pin Definitions and Functions Symbol Pin Number P-MQFP-80 RESET 1 VAREF 3 VAGND 4 P6.0-P6.7 12 Input O = Output Semiconductor Group I/O*) Function I RESET A low level on this pin for the duration ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-80 P3.0-P3.7 15- Input O = Output Semiconductor Group I/O*) Function I/O Port 8-bit quasi-bidirectional I/O ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-80 P7.0 / INT7 23 P1.0 - P1.7 31- Input O = Output Semiconductor Group I/O*) Function I/O Port ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-80 XTAL2 36 XTAL1 37 P2.0-P2.7 38-45 CPUR Input O = Output Semiconductor Group I/O*) Function I XTAL2 Input to the inverting oscillator amplifier and input ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-80 PSEN 47 ALE P0.0-P0.7 52-59 P5.0-P5.7 67- Input O = Output Semiconductor Group I/O*) Function O The Program Store Enable output is a ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-80 HWPD 69 P4.0-P4.7 72-74, 76- PE/SWD Input O = Output Semiconductor Group I/O*) Function I Hardware Power ...
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Table 1 Pin Definitions and Functions (cont’d) Symbol Pin Number P-MQFP-80 VSSCLK 13 VCCCLK 14 VCCE1 32 VCCE2 68 VSSE1 35 VSSE2 70 VCC1 33 VSS1 34 VCCEXT 50 VSSEXT 51 N. Input O = ...
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Figure 4 Block Diagram of the C515C Semiconductor Group 14 C515C 1997-07-01 ...
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CPU The C515C is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting ...
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Memory Organization The C515C CPU manipulates data and operands in the following five address spaces: – Kbyte of internal/external program memory – Kbyte of external data memory – 256 bytes of internal data memory ...
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... Global XRAM/CAN controller access enable/disable control XMAP0 = 0 : The access to XRAM and CAN controller is enabled. XMAP0 = 1 : The access to XRAM and CAN controller is disabled (default Bit XMAP0 is hardware protected reset once (XRAM/CAN controller access enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit again. ...
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MOVX DPTR a)P0/P2 Bus @DPTR < b)RD/WR active XRAM/CAN c)ext.memory address is used range DPTR a)P0/P2 Bus (RD/WR-Data) XRAMCAN b)RD/WR address inactive range c)XRAM is used MOVX XPAGE a)P0 Bus @ Ri < P2 I/O XRAMCAN b)RD/WR active addr.page ...
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Reset and System Clock The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (12 oscillator periods) while the oscillator ...
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Multiple Datapointers As a functional enhancement to the standard 8051 architecture, the C515C contains eight 16-bit datapointers instead of only one datapointer. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer ...
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Enhanced Hooks Emulation Concept The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of ...
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Special Function Registers The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions : the standard special function register area and ...
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... SYSCON 2) System Control Register 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved 4) This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set. ...
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... DB7 Message Data Byte 7 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by a reset operation. “ ...
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... PCON1 Power Control Register 1 Modes 1) Bit-addressable special function registers 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) “X“ means that the value is undefined and the location is reserved 4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. ...
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... IEN0 means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. Semiconductor Group Bit 6 Bit 5 Bit 4 Bit 3 .6 ...
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... H T2PS CA H CRCL CRCH TL2 TH2 means that the value is undefined and the location is reserved 2) Bit-addressable special function registers Semiconductor Group Bit 6 Bit 5 Bit 4 Bit – – – – ...
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... XXXX- – XXX1 means that the value is undefined and the location is reserved 2) Bit-addressable special function registers 3) This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set. Semiconductor Group Bit 6 Bit 5 Bit 4 Bit 3 ...
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Table 5 Contents of the CAN Registers in numeric order of their addresses Addr. Register Content n=1-F H after 2) 1) Reset F700 F701 F702 F704 H BTR0 ...
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Table 5 Contents of the CAN Registers in numeric order of their addresses (cont’d) Addr. Register Content n=1-F H after 2) 1) Reset F7n7 H DB0 XX H F7n8 H DB1 XX H F7n9 H DB2 XX H F7nA H ...
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... Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte IL IH instructions. Nevertheless possible to use port 6 simultaneously for analog and digital input. However, care must be taken that all bits of P6 that have an undetermined value caused by their analog function are masked ...
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Port Structure Selection of Port 5 After a reset operation of the C515C, the quasi-bidirectional 8051-compatible port structure is selected. For selection of the bidirectional (CMOS) port 5 structure the bit PMOD of SFR SYSCON must be set. Because each ...
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Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 6 : Table 6 Timer/Counter 0 and 1 Operating Modes Mode Description 0 8-bit timer/counter with a divide-by-32 prescaler ...
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Timer/Counter 2 with Compare/Capture/Reload The timer 2 of the C515C provides additional compare/capture/reload features. which allow the selection of the following operating modes: – Compare : PWM signals with 16-bit/600 ns resolution – Capture : up to ...
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Timer 2 Operating Modes The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag ...
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Timer 2 Compare Modes The compare function of a timer/register combination operates as follows : the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the ...
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Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the new value will not appear at the output pin until the next compare match occurs. Thus, it can ...
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Serial Interface (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 7. Table 7 USART Operating Modes SCON Mode SM0 SM1 ...
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Figure 15 Block Diagram of Baud Rate Generation for the Serial Interface Table 8 below lists the values/formulas for the baud rate calculation of the serial interface with its dependencies of the control bits BD and SMOD. Table 8 Serial ...
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SSC Interface The C515C microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is compatible to the popular SPI serial bus interface. Figure 16 shows the block diagram of the SSC. The central element of the SSC is ...
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CAN Controller The on-chip CAN controller is the functional heart which provides all resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer ...
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The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from ...
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A/D Converter The C515C includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity ...
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Figure 19 A/D Converter Block Diagram Semiconductor Group 44 C515C 1997-07-01 ...
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Interrupt System The C515C provides 17 interrupt sources with four priority levels. Seven interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter, SSC interface, CAN controller), and ten interrupts may be ...
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Figure 20 Interrupt Request Sources (Part 1) Semiconductor Group 46 C515C 1997-07-01 ...
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Figure 21 Interrupt Request Sources (Part 2) Semiconductor Group 47 C515C 1997-07-01 ...
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Figure 22 Interrupt Request Sources (Part 3) Semiconductor Group 48 C515C 1997-07-01 ...
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Table 9 Interrupt Source and Vectors Interrupt Source External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Channel Timer 2 Overflow / Ext. Reload A/D Converter External Interrupt 2 External Interrupt 3 External Interrupt 4 External ...
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Fail Save Mechanisms The C515C offers two on-chip peripherals which monitor the program flow and ensure an automatic "fail-safe" reaction for cases where the controller’s hardware fails or the software hangs up: – A programmable watchdog timer (WDT) with variable ...
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Oscillator Watchdog The oscillator watchdog unit serves for four functions: – Monitoring of the on-chip oscillator's function The watchdog supervises the on-chip oscillator's frequency lower than the frequency of the auxiliary RC oscillator in the watchdog unit, ...
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Figure 24 Block Diagram of the Oscillator Watchdog Power Saving Modes The C515C provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the ...
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Slow-down mode The controller keeps up the full operating functionality, but its normal clock frequency is internally divided by 32. This slows down all parts of the controller, the CPU and all peripherals, to 1/32-th of their normal operating ...
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Absolute Maximum Ratings Ambient temperature under bias ( Storage temperature ( T ) .......................................................................... – 150 C stg V Voltage on pins with respect to ground ( CC Voltage on any pin with respect to ground ( ...
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... V 0.9 OH3 CC I – – – – LI2 I – LI3 I – LI4 C – – for the SAB-C515C-8R for the SAF-C515C-8R for the SAH-C515C-8R Unit Test Condition max. 0.2 V – 0.1 V – 0.2 – 0.3 V – 0.2 + 0.1 V – 0.3 V – 0.5 V – ...
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... (active mode) is measured with: CC XTAL2 driven with CLCH CHCL EA = PE/SWD = Port 0 = Port (idle mode) is measured with all output pins disconnected and with all peripherals disabled; CC XTAL2 driven with CLCH CHCL RESET = Port0 = CC SS ...
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Figure 25 ICC Diagram Power Supply Current Calculation Formulas Parameter Active mode Idle mode Active mode with slow-down enabled Idle mode with slow-down enabled Note : f is the oscillator ...
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... S ADCC min = 500 ns ADC = OSC CLP 58 for the SAB-C515C-8R for the SAF-C515C-8R for the SAH-C515C-8R Unit Test Condition Prescaler 8 2) Prescaler 4 ns Prescaler 8 3) Prescaler 4 4) LSB ...
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Notes may exeed AIN AGND these cases will be X000 or X3FF H 2) During the sample time the input capacitance C internal resistance of the analog source must allow the capacitance to reach their ...
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... PXIZ – PXAV t – 180 AVIV t 0 AZPL 60 C515C for the SAB-C515C-8R for the SAF-C515C-8R for the SAH-C515C-8R Limit Values Variable Clock 1/CLP = 2 MHz to 10 MHz min. max. CLP - 40 – TCL -25 – Hmin TCL -25 – Hmin – 2 CLP - 87 TCL -20 – ...
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External Data Memory Characteristics Parameter RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to ...
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SSC Interface Characteristics Parameter Clock Cycle Time : Master Mode Slave Mode Clock high time Clock low time Data output delay Data output hold Data input setup Data input hold TC bit set delay External Clock Drive at XTAL2 Parameter ...
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ALE PSEN Port 0 Port 2 Figure 26 Program Memory Read Cycle ALE PSEN RD t AVLL from Port 0 Port 2 Figure 27 Data Memory Read Cycle Semiconductor Group t LHLL t t AVLL PLPH t ...
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ALE PSEN WR t AVLL from Port DPL Port 2 Figure 28 Data Memory Write Cycle Figure 29 External Clock Drive at XTAL2 Semiconductor Group t t LLWL WLWH t QVWX t LLAX2 t ...
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SCLK t SCL SCLK t D STO SRI MSB TC Notes : Shown is the data/clock relationship for CPOL=CPHA=1. The timing diagram is valid for the other cases accordingly. In the case of slave mode and ...
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ROM Verification Mode 1 Parameter Address to valid data Figure 31 ROM Verification Mode 1 Semiconductor Group Symbol Limit Values min. t – AVQV 66 C515C Unit max. 5 CLP ns 1997-07-01 ...
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ROM Verification Mode 2 Parameter ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency ALE Port 0 P3.5 Figure 32 ROM Verification Mode 2 Semiconductor Group Symbol min. t ...
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Inputs during testing are driven at Timing measurements are made at Figure 33 AC Testing: Input, Output Waveforms V +0.1 V Load V Load -0 Load For timing purposes a port ...
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P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Package) Figure 36 Package Outlines Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” SMD = Surface Mounted Device Semiconductor Group 69 C515C Dimensions in mm ...