NS32CG16V-15 National Semiconductor, NS32CG16V-15 Datasheet
NS32CG16V-15
Available stocks
Related parts for NS32CG16V-15
NS32CG16V-15 Summary of contents
Page 1
... BLock Transfer) operations and other special graphics func- tions make the device the ideal choice to handle a variety of page description languages such as Postscript PCL TM Block Diagram Series 32000 is a registered trademark of National Semiconductor Corporation EP TM Embedded System Processors TM are trademarks of National Semiconductor Corporation ...
Page 2
PRODUCT INTRODUCTION 1 1 NS32CG16 Special Features 2 0 ARCHITECTURAL DESCRIPTION 2 1 Register Set General Purpose Registers Address Registers Processor Status Register Configuration Register 2 ...
Page 3
Appendix A INSTRUCTION FORMATS Appendix B INSTRUCTION EXECUTION TIMES B 1 Basic and Floating-Point Instructions Equations Notes on Table Use Calculation of the Execution Time TEX for Basic Instructions B 1 ...
Page 4
CPU Block Diagram NS32FX16 Internal Registers Processor Status Register (PSR) Configuration Register (CFG) NS32CG16 Run-Time Environment General Instruction Format Index Byte Format Displacement Encodings Correspondence between Linear and Cartesian Addressing 32-Pixel by 32-Scan Line Frame Buffer Overlapping BITBLT Blocks B ...
Page 5
List of Illustrations Cycle Extension of a Read Cycle Slave Processor Read Cycle Slave Processor Write Cycle NS32FX16 and FPU Interconnections Memory Interface HOLD Timing Bus Initially Idle HOLD Timing Bus Initially Not Idle Connection Diagram Test Loading Configuration Output ...
Page 6
Product Introduction The NS32CG16 is a high speed CMOS microprocessor in the Series 32000 EP family The NS32CG16 is software-compatible with all other CPUs in the family The device incorporates all of the Series 32000 advanced architectural features ...
Page 7
Product Introduction (Continued) Below is a summary of the instructions that are directly ap- plicable to graphics along with their intended use Instruction Application BBAND The BITBLT group of instructions provide a BBOR method of quickly imaging characters ...
Page 8
Architectural Description FP Frame Pointer The FP register is used by a procedure to access parameters and local variables on the stack The FP register is set up on procedure entry with the ENTER instruction and restored on ...
Page 9
Architectural Description 2 2 MEMORY ORGANIZATION The main memory of the NS32CG16 is a uniform linear ad- dress space Memory locations are numbered sequentially 24 starting at zero and ending The number specify- b ing ...
Page 10
Architectural Description Note Dashed lines indicate information copied to register during transfer of control between modules FIGURE 2-4 NS32CG16 Run-Time Environment 2 4 INSTRUCTION SET General Instruction Format Figure 2-5 shows the general format of ...
Page 11
Architectural Description FIGURE 2-6 Index Byte Format Addressing Modes The NS32CG16 CPU generally accesses an operand by cal- culating its Effective Address based on information avail- able when the operand accessed The ...
Page 12
Architectural Description TABLE 2-1 NS32CG16 Addressing Modes ENCODING MODE Register 00000 Register 0 00001 Register 1 00010 Register 2 00011 Register 3 00100 Register 4 00101 Register 5 00110 Register 6 00111 Register 7 Register Relative 01000 Register ...
Page 13
Architectural Description Instruction Set Summary Table 2-2 presents a brief description of the NS32CG16 instruction set The Format column refers to the Instruction Format tables (Appendix A) The Instruction column gives the instruction as coded ...
Page 14
Architectural Description TABLE 2-2 NS32CG16 Instruction Set Summary (Continued) INTEGER COMPARISON Format Operation Operands 4 CMPi gen gen 2 CMPQi short gen 7 CMPMi gen gen disp LOGICAL AND BOOLEAN Format Operation Operands 4 ANDi gen gen 4 ...
Page 15
Architectural Description TABLE 2-2 NS32CG16 Instruction Set Summary (Continued) STRINGS String instructions assign specific functions to the General Purpose Registers R4 Comparison Value R3 Translation Table Pointer R2 String 2 Pointer R1 String 1 Pointer R0 Limit Count ...
Page 16
Architectural Description TABLE 2-2 NS32CG16 Instruction Set Summary (Continued) FLOATING POINT Format Operation Operands 11 MOVf gen gen 9 MOVLF gen gen 9 MOVFL gen gen 9 MOVif gen gen 9 ROUNDfi gen gen 9 TRUNCfi gen gen ...
Page 17
Architectural Description 2 5 GRAPHICS SUPPORT The following sections provide a brief description of the NS32CG16 graphics support capabilities Basic discussions on frame buffer addressing and BITBLT operations are also provided More detailed information on the NS32CG16 graphics ...
Page 18
Architectural Description Frame Buffer Architecture There are two basic types of frame buffer architectures plane-oriented or pixel-oriented BITBLT takes advantage of the plane-oriented frame buffer architecture’s attribute of multiple adjacent pixels-per-word facilitating the movement ...
Page 19
Architectural Description (a) FIGURE 2-10 Overlapping BITBLT Blocks The left mask and the right mask are 0000 1111 1111 1111 and 1111 1111 0000 0000 respectively Note 1 Zeros in either the left mask or the right mask ...
Page 20
Architectural Description curs any time the screen is moved in a purely vertical direc- tion as in scrolling text It should be noted that in both of these cases the choice of horizontal BITBLT direction may be made ...
Page 21
Architectural Description This instruction can be used within the inner loop of a block OR operation Its use assumes that the source data is ‘clean’ and does not need masking The BITWT format is shown in Figure 2-12 ...
Page 22
Architectural Description Set Bit String Syntax SBITS Setup R0 base address of the destination R1 starting bit offset (signed) R2 number of bits to set (unsigned) R3 address of string look-up table Note When the instruction terminates the ...
Page 23
Architectural Description Magnifying Compressed Data Restoring data is just one application of the SBITS and SBITPS instructions Multiplying the ‘‘length’’ operand used by the SBITS and SBITPS instructions causes the resulting pattern to ...
Page 24
Functional Description Completed Instructions When an exception is recognized after an instruction is completed the CPU has performed all of the operations for that instruction and for all other instructions executed since the last ...
Page 25
Functional Description The CPU next sends the Operation Word while applying Status Code 1101 (Transfer Slave Operand Upon receiving it the Slave Processor decodes it and at this point both the CPU and the ...
Page 26
Functional Description The Operand class columns give the Access Class for each general operand defining how the addressing modes are interpreted (see Series 32000 Instruction Set Reference Manual) The Operand Issued columns show the sizes of the oper- ...
Page 27
Functional Description This process is illustrated in Figure 3-13a from the view- point of the programmer FIGURE 3-5 Exception Acknowledge Sequence (Continued) Details on the sequences of events in processing interrupts and traps are given in the following ...
Page 28
Functional Description Returning from an Exception Service Procedure To return control to an interrupted program one of two in- structions can be used RETT (Return from Trap) and RETI (Return from Interrupt) RETT is used ...
Page 29
Functional Description FIGURE 3-7 Return from Interrupt (RETI) Instruction Flow Vectored Mode Non-Cascaded Case In the Vectored mode the CPU uses an Interrupt Control Unit (ICU) to prioritize interrupt requests Upon ...
Page 30
Functional Description Unit (ICU) to transparently support cascading Figure 3-9 shows a typical cascaded configuration Note that the Inter- rupt output from a Cascaded ICU goes to an Interrupt Re- quest input of the Master ICU which is ...
Page 31
Functional Description FIGURE 3-9 Cascaded Interrupt Control Unit Connections (Continued 9424 – 18 ...
Page 32
Functional Description Non-Maskable Interrupt The Non-Maskable Interrupt is triggered whenever a falling edge is detected on the NMI pin The CPU performs an ‘‘Interrupt Acknowledge’’ bus cycle from Address FFFF00 when processing of this interrupt ...
Page 33
Functional Description FIGURE 3-10 Exception Processing Flowchart (Continued 9424 – 19 ...
Page 34
Functional Description Exception Acknowledge Sequences Detailed Flow For purposes of the following detailed discussion of excep- tion acknowledge sequences a single sequence called ‘‘service’’ is defined in Figure 3-11 Upon detecting any interrupt request or ...
Page 35
Functional Description TABLE 3-2 Summary of Exception Processing Exception Interrupt UND SLAVE SVC DVZ FLG BPT ILL TRC 3 3 DEBUGGING SUPPORT The NS32CG16 provides features to assist in program de- bugging Besides the Breakpoint (BPT) instruction that ...
Page 36
Functional Description During prototype using wire-wrap or similar methods the capacitors should be soldered directly to the power pins of the NS32CG16 socket or as close as possible with very short leads Recommended bypass for production in printed ...
Page 37
Functional Description FIGURE 3-14 Recommended Reset Connections TABLE 3-3 External Oscillator Specifications Crystal Characteristics Type Tolerance 0 005% at Stability 0 01% from Resonance 20 MHz or 30 MHz Fundamental (Parallel) 30 MHz Third Overtone ...
Page 38
Functional Description Tracing is disabled Supervisor mode is enabled Supervisor stack space is used when the TOS addressing mode is indicated No trace traps are pending Only NMI is enabled Maskable interrupts are disabled BPU is inactive high ...
Page 39
Functional Description A full-speed bus cycle is performed in four cycles of the CTTL clock signal labeled T1 through T4 Clock cycles not associated with a bus cycle are designated Ti (for ‘‘idle’’) During T1 the CPU applies ...
Page 40
Functional Description (Continued) FIGURE 3-18 Read Cycle Timing 9424 – 12 ...
Page 41
Functional Description (Continued) FIGURE 3-19 Write Cycle Timing 9424 – 13 ...
Page 42
Functional Description At this time the signals TSO (Timing State Output) DBE (Data Buffer Enable) and either RD (Read Strobe (Write Strobe) will also be activated The T3 state provides for access time requirements and it ...
Page 43
Functional Description FIGURE 3-20 Cycle Extension of a Read Cycle (Continued 9424 – 14 ...
Page 44
Functional Description Instruction Fetch Cycles Instructions for the NS32CG16 CPU are ‘‘prefetched’’ that is they are input before being needed into the next available entry of the eight-byte instruction Queue The CPU performs two ...
Page 45
Functional Description Cycle Status Address A Non-Maskable Interrupt Control Sequence Interrupt Acknowledge 1 0100 FFFF00 16 Interrupt Return None Performed through Return from Trap (RETT) instruction B Non-Vectored Interrupt Control Sequence Interrupt Acknowledge 1 0100 FFFE00 16 Interrupt ...
Page 46
Functional Description Slave Processor Bus Cycles A Slave Processor bus cycle always takes exactly two clock cycles labeled T1 and T4 (see Figures 3-21 and 3-22 ) Dur- ing a Read cycle SPC is ...
Page 47
Functional Description FIGURE 3-23 NS32CG16 and FPU Interconnections (Continued 9424 – 73 FIGURE 3-24 Memory Interface TABLE 3-5 Bus Cycle Categories Category Even Byte Odd Byte Even Word Accesses of operands requiring more than one bus ...
Page 48
Functional Description Cycle Type Address 1 Odd Byte A 2 Even Byte Even Double-Word Access Sequence 1 Even Word A 1 Even Word Odd Double-Word Access Sequence 1 Odd Byte ...
Page 49
Functional Description Bus Access Control The NS32CG16 CPU has the capability of relinquishing its control of the bus upon request from a DMA controller or another CPU This capability is implemented by means of ...
Page 50
Functional Description FIGURE 3-26 HOLD Timing Bus Initially Not Idle (Continued 9424– 76 ...
Page 51
Functional Description Instruction Status In addition to the four bits of Bus Cycle status (ST0– 3) the NS32CG16 CPU also presents Instruction Status informa- tion on three separate pins These pins differ from ST0 ...
Page 52
Device Specifications (Continued) 1100 Read for Effective Address 1101 Transfer Slave Operand 1110 Read Slave Status Word 1111 Broadcast Slave User Supervisor User or Supervisor Mode status High indicates User Mode low indicates Supervisor Mode ...
Page 53
... Device Specifications (Continued) Order Number NS32CG16V-10 or NS32CG16V-15 68-Pin PCC Package Bottom View NS Package Number V68A FIGURE 4-1 Connection Diagram 9424 – 29 ...
Page 54
... Device Specifications 4 2 ABSOLUTE MAXIMUM RATINGS If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Temperature Under Bias Storage Temperature ELECTRICAL CHARACTERISTICS T Symbol Parameter V High Level Input Voltage IH V Low Level Input Voltage ...
Page 55
Device Specifications 4 4 TEST LOADING CHARACTERISTICS High Level Capacitive Signal Name Output Voltage Loading ( HBE ST0– ILO HLDA PFS BPU RST0 ...
Page 56
Device Specifications Timing Tables Output Signals Internal Propagation Delays NS32CG16-10 and NS32CG16-15 Name Figure Description t 4-15 CTTL Clock Period CTp t 4-15 CTTL High Time CTh (Both ...
Page 57
Device Specifications Output Signals Internal Propagation Delays NS32CG16-10 and NS32CG16-15 (Continued) Name Figure Description t 4-7 AD0–AD15 Floating ALf (Caused by HOLD) t 4-7 A16–A23 Floating AHf t 4-5 4-8 Address Bits 0–15 ALnf ...
Page 58
Device Specifications Output Signals Internal Propagation Delays NS32CG16-10 and NS32CG16-15 (Continued) Name Figure Description t 4-5 TSO Signal Active TSOa t 4-5 TSO Signal Inactive TSOia t 4-5 RD Signal Active RDa t 4-5 ...
Page 59
Device Specifications Input Signal Requirements NS32CG16-10 and NS32CG16-15 Name Figure Description t 4-15 OSCIN Clock Period Xp t 4-15 OSCIN High Time Xh (External Clock) t 4-15 OSCIN Low Time Xl t 4-5 4-11 ...
Page 60
Device Specifications (Continued TIMING DIAGRAMS FIGURE 4-5 Read Cycle 9424 – 32 ...
Page 61
Device Specifications (Continued) FIGURE 4-6 Write Cycle 9424 – 33 ...
Page 62
Device Specifications (Continued) FIGURE 4-7 HOLD Acknowledge Timing (Bus Initially Not Idle) Note When the bus is not idle HOLD must be asserted before the rising edge of CTTL of the timing state that precedes state T4 in ...
Page 63
Device Specifications (Continued) FIGURE 4-8 HOLD Timing (Bus Initially Idle 9424 – 35 ...
Page 64
Device Specifications (Continued) FIGURE 4-9 DMAC Initiated Bus Cycle Note 1 ADS must be deactivated before state T4 of the DMA controller cycle Note 2 During a DMA cycle WAIT1–2 must be kept inactive unless they are monitored ...
Page 65
Device Specifications (Continued) FIGURE 4-10 Slave Processor Write Timing After transferring the last operand to the FPU the CPU turns OFF the output driver and holds SPC high with an internal 9424 – 37 ...
Page 66
Device Specifications (Continued) Note ILO may be asserted more than one clock cycle before the beginning of an interlocked access FIGURE 4-14 ILO Signal Timing FIGURE 4-15 Clock Waveforms 9424– 9424– 47 ...
Page 67
Device Specifications (Continued) Note 1 Once INT is asserted it must remain asserted until it is acknowledged Note 2 INTA is the Interrupt Acknowledge bus cycle (not a CPU signal) Refer to Section and Table ...
Page 68
Device Specifications (Continued) Note 1 During Reset the HOLD signal must be kept high Note 2 After RSTI is deasserted the first bus cycle will be an instruction fetch at address zero FIGURE 4-19 Non-Power-On Reset 68 TL ...
Page 69
Appendix A Instruction Formats NOTATIONS i Integer Type Field (Byte (Word (Double Word Floating-Point Type Field (Std Floating 32 bits (Long Floating 64 ...
Page 70
Appendix A Instruction Formats short Format 5 MOVS 0000 BITWT b CMPS 0001 TBITS b SETCFG 0010 BBAND b ...
Page 71
Appendix A Instruction Formats Format 14 Trap (UND) Always Format 15 Trap (UND) Always Format 16 Trap (UND) Always Format 17 Trap (UND) Always Note 1 Opcode not defined CPU treats like MOVf First operand has access class of read ...
Page 72
Appendix B Instruction Execution Times This section provides the necessary information to calculate the instruction execution times for the NS32CG16 The following assumptions are made The entire instruction with all displacements and imme- Y diate operands is assumed to be ...
Page 73
Appendix B Instruction Execution Times TOPi If operand register or is immediate then TOPi 0 e else if i byte then TOPi TOPB e e else if i word then TOPi TOPW e e else (i double-word) ...
Page 74
Appendix B Instruction Execution Times TEX Calculation Operand register operand memory This means that we have to use the table values for the case The following parameter values are obtained from Table B-2 ...
Page 75
Appendix B Instruction Execution Times TABLE B-1 Basic Instructions (Continued) Mnemonic TEA1 TEA2 TOPB BICPSRB 1 1 BICPSRW 1 BISPSRB 1 1 BISPSRW 1 BPT BR BSR CASEi 1 CBITi CBITIi CHECKi ...
Page 76
Appendix B Instruction Execution Times TABLE B-1 Basic Instructions (Continued) Mnemonic TEA1 TEA2 TOPB INDEXi 1 1 INSi INSSi 1 1 JSR 1 JUMP 1 LPRi 1 LSHi MEIi 1 1 MODi 1 1 ...
Page 77
Appendix B Instruction Execution Times TABLE B-1 Basic Instructions (Continued) Mnemonic TEA1 TEA2 TOPB REMi 1 1 RESTORE RET RETI 1 2 RETT ROTi RXP Scondi 1 1 SAVE SBITi SBITIi 1 1 ...
Page 78
Appendix B Instruction Execution Times TABLE B-2 Floating-Point Instructions CPU Portion Mnemonic TEA1 TEA2 TOPD ADDf SUBf 1 f MULf DIVf MOVf ABSf 1 f NEGf MOVFL 1 1 ...
Page 79
Appendix B Instruction Execution Times B 2 SPECIAL GRAPHICS INSTRUCTIONS This section provides the execution times for the special graphics instructions Table B-3 lists the average instruction execution times for different shift values and for a no-wait- state system design ...
Page 80
Appendix B Instruction Execution Times TABLE B-3 Average Instruction Execution Times with No Wait-States (Continued) Instruction Number of Clock Cycles BITWT shift 28 a EXTBLT (11 a ...
Page 81
81 ...
Page 82
... Physical Dimensions inches (millimeters) Order Number NS32CG16V-10 or NS32CG16V-15 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or ...