AL116 Broadcom Corporation, AL116 Datasheet
AL116
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AL116 Summary of contents
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... Gigabit Ethernet ready Product Description The AL116 is an eight-port 10/100 Mbit/s dual speed Ethernet switch. A low-cost and scalable solution for ports is achieved through the use of low-cost buffer memory and Allayer’s TM proprietary RoX architecture. In addition, the AL116 supports VLAN and multiple link aggregation trunks ...
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This document contains proprietary information which shall not be reproduced, transferred to other documents, or used for any other purpose without the prior written consent of Allayer Communications. Disclaimer Allayer Communications reserves the right to make changes, without notice, in ...
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... AL116 Overview ..................................................................................................... 5 2. Pin Descriptions....................................................................................................... 7 3. Functional Description........................................................................................... 22 3.1 RoX Interface................................................................................................. 22 3.2 Data Reception............................................................................................... 22 3.2.1 Illegal Frame Length.............................................................................. 22 3.2.2 Long Frames .......................................................................................... 23 3.2.3 False Carrier Events ............................................................................... 23 3.2.4 Frame Filtering....................................................................................... 23 3.3 Frame Forwarding.......................................................................................... 24 3.3.1 Broadcast Storm Control........................................................................ 24 3.3.2 Frame Transmission............................................................................... 25 3.3.3 Frame Generation................................................................................... 25 3.4 Half Duplex Mode Operation ........................................................................ 25 3.5 Secure Mode Operation ................................................................................. 26 3.6 Address Learning ........................................................................................... 26 3.6.1 Address Aging........................................................................................ 27 3 ...
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... EEPROM MAP...................................................................................... 45 3.18 SGRAM Interface .......................................................................................... 48 4. Register Description .............................................................................................. 49 5. Timing Requirements............................................................................................. 66 6. Electrical Specifications ........................................................................................ 75 7. AL116 Mechanical Data........................................................................................ 76 8. Appendix I (VLAN Mapping Work Sheet) ........................................................... 77 9. Appendix II (Port to Trunk Port Assignment Work Sheet) ................................... 78 10. Appendix III (Suggested Memory Components)................................................... 79 5/00 Reference Only / Allayer Communications 4 ...
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... With this method of flow control, the switch will generate a jam signal when the receive-buffer is full. The sending station will not transmit until the line is clear. In the full-duplex mode, the AL116 utilizes IEEE 802.3x as the flow control mechanism. ...
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... AL116 Pin Diagram Figure 2 Pin Diagram (Top View) 5/00 Reference Only / Allayer Communications 6 ...
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... Pin Descriptions The AL116 also supports RMII interface. When RMII interface is used TXD3, TXD2, TXCLK, RXDV, RXER, and COL should be left unconnected. The RXCLK should be connected to the reference clock. A RXCLK is provided for each individual port to reduce clock skew. PIN NAME PIN NO. ...
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PIN NAME PIN NO. M1TXD3 M1TXD2 M1TXD1 M1TXD0 M1TXEN M1TXCLK M1RXD3 M1RXD2 M1RXD1 M1RXD0 M1RXDV M1RXCLK M1RXER M1CRS M1COL 5/00 Table 2: RMII/MII Interface (Port 1) I Transmit Data - NRZ data to be transmitted to N2 transceiver. ...
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PIN NAME PIN NO. M2TXD3 AB3 M2TXD2 AB2 M2TXD1 AB1 M2TXD0 AC3 M2TXEN AC2 M2TXCLK AC1 M2RXD3 AE3 M2RXD2 AF1 M2RXD1 AE1 M2RXD0 AE2 M2RXDV AD1 M2RXCLK AD2 M2RXER AD3 M2CRS AA3 M2COL AA1 5/00 Table 3: RMII/MII Interface (Port ...
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PIN NAME PIN NO. M3TXD3 AD9 M3TXD2 AE9 M3TXD1 AF9 M3TXD0 AD10 M3TXEN AE10 M3TXCLK AF10 M3RXD3 AF12 M3RXD2 AD12 M3RXD1 AC12 M3RXD0 AF11 M3RXDV AE11 M3RXCLK AD11 M3RXER AC11 M3CRS AD8 M3COL AF8 5/00 Table 4: RMII/MII Interface (Port ...
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PIN NAME PIN NO. M4TXD3 AD16 M4TXD2 AE16 M4TXD1 AF16 M4TXD0 AD17 M4TXEN AE17 M4TXCLK AF17 M4RXD3 AF19 M4RXD2 AD19 M4RXD1 AC19 M4RXD0 AF18 M4RXDV AE18 M4RXCLK AD18 M4RXER AC18 M4CRS AD15 M4COL AF15 5/00 Table 5: RMII/MII Signal (Port ...
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PIN NAME PIN NO. M5TXD3 AF26 M5TXD2 AE26 M5TXD1 AD25 M5TXD0 AC24 M5TXEN AC25 M5TXCLK AC26 M5RXD3 AA26 M5RXD2 AA24 M5RXD1 AA23 M5RXD0 AB26 M5RXDV AB25 M5RXCLK AB24 M5RXER AB23 M5CRS AE24 M5COL AE25 5/00 Table 6: RMII/MII Signal (Port ...
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PIN NAME PIN NO. M6TXD3 T24 M6TXD2 T25 M6TXD1 T26 M6TXD0 R24 M6TXEN R25 M6TXCLK R26 M6RXD3 N26 M6RXD2 N24 M6RXD1 N23 M6RXD0 P26 M6RXDV P25 M6RXCLK P24 M6RXER P23 M6CRS U24 M6COL U26 5/00 Table 7: RMII/MII Signal (Port ...
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PIN NAME PIN NO. M7TXD3 H24 M7TXD2 H25 M7TXD1 H26 M7TXD0 G24 M7TXEN G25 M7TXCLK G26 M7RXD3 E26 M7RXD2 E24 M7RXD1 E23 M7RXD0 F26 M7RXDV F25 M7RXCLK F24 M7RXER F23 M7CRS J24 M7COL J26 5/00 Table 8: RMII/MII Signal (Port ...
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PIN NAME PIN NO. RID31 RID30 RID29 RID28 RID27 RID26 RID25 RID24 RID23 RID22 RID21 RID20 RID19 RID18 RID17 RID16 RID15 RID14 RID13 RID12 RID11 RID10 RID9 RID8 RID7 RID6 RID5 RID4 RID3 AA4 RID2 AD4 RID1 AE4 RID0 AF4 ...
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PIN NAME PIN NO. ROD31 B24 ROD30 A25 ROD29 B26 ROD28 B25 ROD27 C26 ROD26 C25 ROD25 D26 ROD24 D25 ROD23 D24 ROD22 K26 ROD21 K25 ROD20 K24 ROD19 L26 ROD18 L25 ROD17 L24 ROD16 M26 ROD15 M25 ROD14 M24 ...
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PIN NAME PIN NO. PBD31 PBD30 PBD29 PBD28 PBD27 PBD26 PBD25 PBD24 PBD23 PBD22 PBD21 PBD20 PBD19 PBD18 PBD17 PBD16 PBD15 PBD14 PBD13 PBD12 PBD11 PBD10 PBD9 PBD8 PBD7 PBD6 PBD5 PBD4 PBD3 PBD2 PBD1 PBD0 PBA10_9 PBA9_8 PBANC8 5/00 ...
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PIN NAME PIN NO. PBA7 PBA6 PBA5 PBA4 PBA3 PBA2 PBA1 PBA0 PBCS# PBRAS# PBCAS# PBWE# PBCLK Table 12: External Address Table SRAM Interface PIN NAME ETD15 ETD14 ETD13 ETD12 ETD11 ETD10 ETD9 ETD8 ETD7 ETD6 ETD5 ETD4 ETD3 ETD2 ...
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Table 12: External Address Table SRAM Interface (Continued) PIN NAME ETA15 ETA14 ETA13 ETA12 ETA11 ETA10 ETA9 ETA8 ETA7 ETA6 ETA5 ETA4 ETA3 ETA2 ETA1 ETA0 ETADSC# ETADV# ETGW# ETOE# ETCLK PIN NAME PIN NUMBER EEDIO EECLK PIN NAME PIN ...
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PIN NAME PIN NUMBER DEVID1 DEVID0 RESET# TESTMODE SRL EPBYPASS SYSCLK TRST TMS TDO TDI TCLK PIN NAME GND A4, A6, A18, A19, A23, A24, A26, B1, B2, B3, B12, B15, B23, C1, C3, C10, C12, C15, D10, D17, D18, ...
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PIN NAME VccM NC E5, E6, E8, E10, E18, E19, G22, J5, J22, L5, N5, P5, R22, U5, U22, V5, AB5, AB7, AB8, AB10, AB13, MXTXD3 10/100 MAC MXTXD2 MXTXD1 10/100 MAC MXTXD0 MXTXEN 10/100 MAC MXTXCLK MXRXD3 10/100 MAC ...
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... The port will go into the receive-state when RX_DV in the MII interface is asserted. The MII presents the received data in four-bit nibbles that are synchronous to the receive clock (25 MHz or 2.5 MHz). The AL116 will then attempt to detect the occurrence of the SFD (10101011) pattern. All preamble data prior to SFD are discarded. Once SFD is detected, the frame data is forwarded and stored in the buffer of the switch ...
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... Long Frames The AL116 can handle frames up to 1536 bytes. All frames longer than 1536 bytes will be discarded. If the port continued to receive data after the 1536 If the port is in half-duplex mode, the port will no longer be able to transmit or receive data during the long frame reception. ...
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... Flood Control option (System Configuration register 00). If Flood Control is disabled, the frame will be forwarded to all ports (except the receiving port) within the same VLAN as the receiving port. If the Flood Control option is enabled, the AL116 will forward the frame only to the uplink port specified at the receiving port. ...
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... Frame Transmission AL116 transmits all frames in accordance to IEEE 802.3 standard. The AL116 will send the frames with a guaranteed minimum inter-packet/frame gap (IPG) of 96BT, even the received frames have an IPG less than the minimum requirement. The AL116 also supports transmission of frames with an IPG of 64BT (optional) ...
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... The source address retrieved from the received frame is automatically stored buffer. The AL116 will then check for error and security violation, and perform a SA search. If there is no error or security violation, the chip will store the source address in the address lookup table. If the SA has been previously stored in another port’ ...
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... If the security option is selected for the port, AL116 will consider this as a security violation. If port is a non-protected port, the AL116 will delete the SA from the previous port’s address table and update it to the current port’ ...
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VLAN Set Up Example A VLAN set up worksheet is provided in Appendix I. Simply by marking the ports you wish to send broadcast frame to, you can complete the VLAN map easily. Let’s assume we want to set up ...
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... One of the requirements for transmission is that the frames being transmitted must not be out of order. Therefore, some sort of load balancing among the links of the trunk has to be deployed. The AL116 offers two alternative load balancing methods which are selected in the System Configuration Register I (register 00). ...
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... VLAN. In essence, the AL116 treats a trunk as any single port within the same VLAN. If the ports traffic is evenly distributed among all the trunk ports, load balancing is achieved and the aggregate bandwidth of the trunk can be as high as 800 Mbit/s (full-duplex) ...
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Port Based Trunk Loading For port-based load balancing, a trunk port must be assigned to each port for all defined trunks. The port assignment is done by programming Port to Trunk Port registers ( recommended ...
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TRUNK PORT 7 Trunk 7 6 Bits 5 15 Trunk 6 2 Bits 1 13 Trunk 5 6 Bits 5 11 Trunk 4 2 Bits Trunk ...
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Table 18: Trunking Port Assignment (Continued) TRUNK PORT 3 Trunk 2 2 Bits Trunk 1 6 Bits Trunk 0 2 Bits 5/00 BIT VALUE 11 10 ...
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... MAC Based Load Balancing For MAC address based load balancing, there is no need to assign a port to a trunk port. The AL116 dynamically assigns MAC address to the trunk port. MAC address based trunks must consist of four trunk ports. The bits are chosen for their randomness. The statistically random bits will ensure good load balancing among all four trunk ports. The following is a procedure to set up the trunk ...
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... The AL116 has the capability to support implementation of the Spanning Tree Protocol. All ports can be programmed the port state as required by the spanning tree protocol. If the Spanning Tree Protocol option is enabled, the AL116 will forward the frame as below. • If the port is in the Block-N-Listen State or the Learning State, the frame is forwarded to the CPU BPDU frame ...
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... The IPG of the jamming signal can be programmed be either 64BT or 96BT. Collision Based backpressure is generated by the AL116, only when the switch port receives a frame. The AL116 will cease to jam the line when the line is idle. ...
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... AL116 are stored into the shared memory buffer, and are lined up in the transmission queues of corresponding destination port. Each port of the AL116 has an input frame queue, and a dedicated queue to buffer the locally generated management event messages. Each output port maintains an output frame queue for, and a dedicated multicast queue for outgoing multicast frame parking ...
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... TXD0, TXD1, RXD0, RXD1, TXEN and CRS. The RXCLK pin is the common reference clock at 50 MHz. The AL116 provides a clock pin for each port to minimize clock skew effect. Note: When RMII is used, all other pins in the MII interface should be left unconnected ...
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... AL116 can set the port operation mode manually through the MDIO interface (see EEPROM section for programming the AL116 CPU is used to reprogram the PHY via AL116, the operating mode is changed without reset or powered down. In order to ensure the link is operating in the desired mode, the PHY should renegotiate either through a command or unplugging the RJ45 ...
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... Unfortunately, such register addresses are vendor specific. The AL116 provides a register (register 05) to specify the register address of the PHY to for the AL116 to read. The AL116 will read from that register and configure the port operation accordingly. ...
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... AL116 will be initialized by the CPU attached to the management device on the RoX ring initialization command is received, the device will not operate. If the reset pin is held low, the AL116’s EEPROM interface will go into a high impedance state. This feature is very useful for reprogramming the EEPROM during installation or reconfiguration. ...
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... EEPROM. The most significant four bits of the EEPROM address are the device type identifier. These four bits are 1010. The EEPROM device address should be set to the device ID number. The EECLK is an output from the AL116. EEDIO is an input if the AL116 is reading the EEPROM or an output writing to it. (See Figure 7 through 10). EECLK ...
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... AL116 as an EEPROM. The read and write timing is the same as an EEPROM. Because you read as well as write to the AL116, status of the register can be read from the AL116. This will serve as a very useful tool for diagnostic of an unmanaged switch. ...
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... AL116 AL116 AL116 AL116 Figure 10 Programming the EEPROM with a Parallel Port 5/00 Reset EECLK EEPROM EEDIO Reset EECLK EEPROM EEDIO Reset EECLK EEPROM EEDIO Reset EECLK EEPROM EEDIO Reference Only / Allayer Communications Parallel Port 44 ...
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... Note: The specific bits in the register are referenced by a “X.Y” notation, where X is the register number and Y is the bit number. Table 20 shows the EEPROM addresses map cross-referenced to the register/bit set of the AL116. Addresses 00 through 6D are for configuring the device. They are downloaded by the AL116 during reset or power up ...
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... Table 21: AL116 EEPROM Mapping (Continued) 10-11 Monitored Src Host II [31:16] 12-13 Monitored Src Host III [15:0] 14-15 Monitored Dst Host I [47:32] 16-17 Monitored Dst Host II [31:16] 18-19 Monitored Dst Host III [15:0] 1A-1B Port 0 Configuration I 1C-1D Port 0 Configuration II 1E-1F Port 1 Configuration I 20-21 Port 1 Configuration II 22-23 Port 2 Configuration I 24-25 Port 2 Configuration II 26-27 Port 3 Configuration I 28-29 Port 3 Configuration II 2A-2B Port 4 Configuration I 2C-2D Port 4 Configuration II ...
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... Table 21: AL116 EEPROM Mapping (Continued) 4C-4D Port 4 VLAN Map II 4E-4F Port 5 VLAN Map I 50-51 Port 5 VLAN Map II 52-53 Port 6 VLAN Map I 54-55 Port 6 VLAN Map II 56-57 Port 7 VLAN Map I 58-59 Port 7 VLAN Map II 5A-5B Reserved 5C-5D Checksum 5E-5F Port 0 to Trunk Port Assignment 60-61 Port 1 to Trunk Port Assignment 62-63 Port 2 to Trunk Port Assignment ...
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... All ports of the AL116 work in Store-And-Forward mode so that all ports can support both 10 Mbit/s and 100 Mbit/s data speed. The AL116 utilize a central memory buffer pool, which is shared by all ports within the same device. After a frame is received passed across the SGRAM interface and stored in the buffer ...
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Register Description REGISTER 5/00 Table 22: Register Table Summary REGISTER DESCRIPTION ...
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Table 22: Register Table Summary Port 7 Configuration I ...
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Table 22: Register Table Summary System Status Register Port 0 Operation Status Port 1 Operation Status Port 2 Operation Status Port 3 Operation Status ...
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... PInMon 8 POutMon 5/00 CPU Present. This bit is set by the AL116, when it detects the EEPROM is absent. The device will assume the CPU is present. Flooding Control. Controls the forwarding of unicast frames with unknown destination received from the non-uplink ports. 0: Disable. Frames received with an unknown unicast destination MAC address will be forwarded to all the ports (excluding the receiving port) within the VLANs specified at the receiving port ...
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... L2Trunk 2 TimeoutEN 1~0 Reserved 5/00 CPU Configuration Ready. This bit is set by the AL116 when the AL116 is initialized by the CPU. 0: Not initialized. 1: Register file initialization done. Network Management Enable Control. 0: Disable. The device will not generate MIB events. 1: Enable. The device will generate MIB events and propagate them onto the ring ...
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... Disable. Device will perform the IEEE standard exponential back off algorithm when a collision occurs. 1: Enable. When collisions occur, the AL116 will back off slots. Retry on Excessive Collision. 0: Normal collision handling. 1: Retry transmission after 16 consecutive collisions. Select the bits position for MAC address to trunk assignment. ...
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Table 25: System Configuration Register III (Register 02) (Continued) 10 SlowAge 9 BpIPG84 8 IPG64 7~6 PRate 5 SG16M 4 BPCOL 3 ETEnb 2 ET16K 1 MCTrap 0 FlowCtrlBC Reserved Register (Register 03) This register is reserved for Allayer’s use. ...
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Vendor Specific PHY Register (Register 05) This register is used to program vendor specific PHY options also used for programming the Vendor Specific PHY register location and bit location of the operation status. Table 26: Vendor Specific PHY ...
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RMON Source and Destination Registers (Registers 07 to 0C) These registers are used by the RMON manager for frame counting. The RMON manager counts the frames to (destination) and from (source) these MAC addresses stored in the register. The 48 ...
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BIT NAME 15~10 UpLinkID 9 Tmember 8 Reserved 7 StormCTL 6 Security 5 CPUOn 4 LrnDis 5/00 Table 30: Port Configuration Register I Uplink ID associated with the port. 0XXYYY: Port ID with XX as the device ID and YYY ...
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Table 30: Port Configuration Register I (Continued) 3~2 PortST 1~0 Reserved BIT NAME 15~12 Reserved 11 FlowCtrlFdEn 10 FlowCtrlHdEn 9~6 MDIOCfg[3:0] 5 MDIODis 4 LinkUp 3 PrtMode100F 2 PrtMode100H 1 PrtMode 10F 0 PrtMode 10H 5/00 Port State Control. 00: ...
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Port VLAN Map Registers (Registers 1D to 2C) These registers provide the VLAN map for each port. A VLAN worksheet is provided in Appendix I. Table 32: Port VLAN Map Registers (Registers 1D to 2C) REGISTER BIT 1D Port0 15~8 ...
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Port Trunk Port Assignment Registers (Registers 2D to 34) The Port to Trunk Port assignment register assigns a port to a trunk for port-based load balancing trunking. Please see example in the trunking section. A port to trunk port work ...
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... Port 2, 11: Port 3 NAME EEPROM Time Out. 0: EEPROM initialized the device. 1: Device is ready to be programmed by the CPU. EEPROM Checksum Error. SGRAM Initialization Done. SRAMinit SRAM Initialization Done. REGinit Register Initialization Done. Traffic Counter. Reserved Chip ID 0000: AL116 Reference Only / Allayer Communications DESCRIPTION DESCRIPTION 62 ...
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Port Operation Status Registers (Register 3A to 41) Registers are status indication on a per port basis. These are read only register. Port 0 port status is in register 3A; Port 1 register 3B…and port 7 register ...
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Table 35: Port Operation Status Registers (Register 3A to 41) (Continued) 4 FalseCRS 3 Underflow 2 TimeOut 1~0 PortMode Indirect Resource Access Command Register (Register 42) This register is used for managing the resource of the switch. Table 36: Indirect ...
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... NAME 15~0 IRAData BIT NAME 15~8 CheckSum 7~0 Reserved 5/00 Indirect Resource Access Data 1. Indirect Resource Access Data 2. Indirect Resource Access Data 3. Indirect Resource Access Data 4. Table 41: Check Sum (Register 47) Check Sum value of AL116 register contents. Reference Only / Allayer Communications DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 65 ...
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Timing Requirements SYMBOL t TXCLK to TXD valid time. tdv t TXCLK to TXEN valid time. txev SYMBOL t TXCLK to TXD valid time. tdv t TXCLK to TXEN valid time. txev Note: Delays are assuming 10pf loading on ...
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SYMBOL t RX_DV, RXD, RX_ER, setup rxds time. t RX_DV, RXD, RX_ER hold time. rxdh SYMBOL t RX_DV, RXD, RX_ER, setup rxds time. t RX_DV, RXD, RX_ER hold time. rxdh RXCLK RXDV RXD Figure 12 RMII/MII Receive Timing Diagram 5/00 ...
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SYMBOL t Setup time. roxs t Hold time. roxh RICLK RID Figure 13 RoX II Bus Timing Table 47: PHY Management (MDIO) Read Timing SYMBOL t MDC high time ch t MDC low time cl t MDC period mc t ...
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SYMBOL t MDC high time ch t MDC low time cl t MDC period mc t MDIO output delay d MDC MDIO Figure 15 PHY Management Write Timing SYMBOL t Access hold time AH t Access setup time AS t ...
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PBCLK CKH CKS CKE Precharge NOP Command BANK t Address RP Don't Care Figure 16 SGRAM Refresh Timing 5/00 t CHI Auto NOP Refresh t RC Reference Only / Allayer Communications t ...
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SYMBOL t Access time AC t Access hold time AH t Access setup time AS t PBCS#, PBRAS#, PBWE# hold CH time t Clock high level width CHI t System clock cycle time CK t CKE hold time CKH t ...
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CK PBCLK t tCKS CKH CKE Command Active NOP A0-A7 ROW column m A8 ROW PBBA BANK 0 PBD t (Bank 0) RCD t RAS Figure 17 SGRAM Read Timing ...
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SYMBOL t Access hold time AH t Access setup time AS t PBCS#, PBRAS#, PBWE# hold CH time t Clock high level width CHI t System clock cycle time CK t CKE hold time CKH t CKE setup time CKS ...
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CK CHI PBCLK t t CKS CKH CKE Command Active NOP A0-A7 ROW column m A8 ROW PBBA BANK PBD t (Bank 0) RCD t RAS Figure ...
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Electrical Specifications Note: Operation at absolute maximum ratings could cause permanent damage to the device. DC Supply Voltage (Vcc) DC Input Voltage DC Output Voltage DC Supply Voltage to MII DC Input Voltage to MII DC Output Voltage to ...
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... AL116 Mechanical Data Figure 19 AL116 Mechanical Dimensions 5/00 Reference Only / Allayer Communications 76 ...
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Appendix I (VLAN Mapping Work Sheet) PORT 5/00 BIT Reference Only / Allayer Communications 77 ...
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Appendix II (Port to Trunk Port Assignment Work Sheet) TRUNK 1 BITS 3, 2 TRUNK 0 BITS 1, 0 5/00 TRUNK BIT/ / PORT VALUE ...
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... Note: This is only a partial list of memory components that can be used in Allayer devices. The AL116 uses Frame Buffer SGRAM chips that require 32-bit wide SGRAM or SDRAM, that is 75 MHz or faster with CAS Latency 2. The AL116 uses MAC Table Memory SSRAM chips that require Sync Burst pipelined SSRAM, 75 MHz or faster ...
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Revision History Rev. 1.4 (7/13/99) 1. Added memory information in appendix III. Rev. 1.4a (7/28/99) 1. Reformatted document. 2. Added new PHY management timing diagrams. 3. Added new RMII and MII timing diagrams. Rev. 1.5 (9/22/99) 1. Switched pin numbers ...
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... A Address Aging 27 Address Learning 26 AL116 EEPROM Mapping 45 AL116 Mechanical Data 76 AL116 Overview 5 AL116 Pin Diagram 6 Appendix I (VLAN Mapping Work Sheet) 77 Appendix II (Port to Trunk Port Assignment Work Sheet) 78 Appendix III (Suggested Memory Components Broadcast Storm Control 24 D Data Reception 22 DC Electrical Characteristics 75 ...
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System Configuration Register I (Register 00) 52 System Configuration Register II (Register 01) 54 System Configuration Register III (Register 02) 54 System Initialization 41 T Testing Register (Register 04) 55 Timing Requirements 66 Trunk Port Assignment 30 Trunk Port Numbering ...