W78C31BP-24 Winbond, W78C31BP-24 Datasheet
W78C31BP-24
Available stocks
Related parts for W78C31BP-24
W78C31BP-24 Summary of contents
Page 1
... Four 8-bit bidirectional ports Two 16-bit timer/counters One full duplex serial port Boolean processor -source, two-level interrupt capability Five Built-in power management Packages: DIP 40: W78C31B-16/24/40 PLCC 44: W78C31BP-16/24/40 QFP 44: W78C31BF-16/24/40 TQFP 44: W78C31BM-16/24/40 8-BIT MICROCONTROLLER Publication Release Date: October 1997 - 1 - W78C31B Revision A3 ...
Page 2
... PIN CONFIGURATIONS 40-Pin DIP (W78C31B) 44-Pin PLCC (W78C31BP P1.5 8 P1.6 9 P1.7 10 RST 11 RXD, P3 TXD, P3 INT0, P3.2 15 INT1, P3.3 16 T0, P3.4 17 T1, P3 ...
Page 3
PIN DESCRIPTION P0.0 P0.7 Port 0, Bits 0 through 7. Port bidirectional I/O port. This port also provides a multiplexed low order address/data bus during accesses to external memory. P1.0 P1.7 Port 1, Bits 0 through 7. ...
Page 4
PSEN Program Store Enable Output, active low. address/data bus during fetch and MOVC operations. weak pull-up. XTAL1 Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock. XTAL2 Crystal 2. This is the ...
Page 5
FUNCTION DESCRIPTION The W78C31B architecture consists of a core controller surrounded by various registers, four general purpose I/O ports, 128 bytes of RAM, two timer/counters, and a serial port. The processor supports 111 different instructions and references both a 64K ...
Page 6
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. ABSOLUTE MAXIMUM RATINGS ...
Page 7
DC Characteristics, continued PARAMETER SYMBOL Input Low Voltage P1, P3 Input Low Voltage (*3) XTAL1, RST Input High Voltage P1, P3 Input High Voltage (*3) XTAL1, RST Notes: *1. P0 and P2 are in external access mode. *2. RST pin ...
Page 8
Program Fetch Cycle PARAMETER Address Valid to ALE Low Address Hold after ALE Low ALE Low to PSEN Low PSEN Low to Data Valid Data Hold after PSEN High Data Float after PSEN High ALE Pulse Width PSEN Pulse Width ...
Page 9
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference. Publication Release Date: October 1997 - 9 - W78C31B Revision A3 ...
Page 10
TIMING WAVEFORMS Program Fetch Cycle S1 XTAL1 ALE PSEN PORT 2 T AAH PORT 0 Code Data Read Cycle S4 S5 XTAL1 ALE PSEN PORT 2 A0-A7 PORT ALW T ...
Page 11
Data Write Cycle S4 S5 XTAL1 ALE PSEN PORT 2 PORT 0 A0-A7 WR Port Access Cycle XTAL1 ALE T PDS PORT INPUT SAMPLE A8-A15 DATA OUT T T DWD DAD T T DAW DWR ...
Page 12
TYPICAL APPLICATION CIRCUIT Using External Program Memory and Crystal CRYSTAL 8 CRYSTAL 16 MHz 24 MHz ...
Page 13
Expanded External Data Memory and Oscillator OSCILLATOR 8 PACKAGE DIMENSIONS 40-pin DIP P0 AD0 AD0 D0 EA ...
Page 14
Package Dimensions, continued 44-pin PLCC Seating Plane 44-pin QFP ...
Page 15
See Detail F Seating Plane Package Dimensions, continued 44-pin TQFP See Detail F Seating Plane ...
Page 16
... No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 Note: All data and specifications are subject to change without notice. Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U ...