CXD3011R Sony, CXD3011R Datasheet
CXD3011R
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CXD3011R Summary of contents
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... CD Digital Signal Processor with Built-in Digital Servo and DAC Description The CXD3011R is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter and 1-bit DAC. Features • All digital signal processing during playback is performed with a single chip • ...
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... The Maximum Operating Speed graph shows the playback speed V The playback conditions are that the high-speed VCO1 selects No.4 and VCO2 selects high speed in CAV-W mode with DSPB = 1. However, the DA output for the 64-bit slot supports 16 speed. 3.2 3.3 3.4 3.5 3.6 [V] DD – 2 – +25°C +55°C +75°C 3.7 3.8 3.9 4.0 (min.) at various temperatures. CXD3011R ...
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... Digital out 100 Servo auto 102 103 104 105 DAC OpAmp FOCUS 113 TRACKING 112 SLED 111 78 85 110 114 CXD3011R 87 PWMLP 88 PWMLN PWMRP 79 PWMRN PSSL DA16 (48PCM) DA15 (48BCK) DA14 (64PCM) DA13 (64BCK) DA12 (64LRCK) DA11 DA1 63 MUTE 62 ...
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... RFDC 142 CE TE 143 NC 144 – 4 – CXD3011R XRST 70 SCSY 69 ...
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... DA13 output when PSSL = 1, 64-bit slot bit clock output when PSSL = 0. DA12 output when PSSL = 1, 64-bit slot LR clock output when PSSL = 0. DA11 output when PSSL = 1, GTOP output when PSSL = 0. DA10 output when PSSL = 1, XUGF output when PSSL = 0. DA09 output when PSSL = 1, XPLCK output when PSSL = 0. – 5 – Description , high = CXD3011R ...
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... Audio DAC sync window open input. Normally high, window open when low. Audio DAC right channel zero detection flag. Audio DAC left channel zero detection flag. Digital GND. Analog GND. Audio DAC PWM output. Right channel, reversed phase. – 6 – Description CXD3011R ...
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... Tracking filter DAC analog output. Focus filter DAC analog output. Constant current input for servo filter DAC analog output. Analog power supply. Spindle motor on/off control output. Spindle motor servo control output. Spindle motor servo control output. – 7 – Description CXD3011R ...
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... the CXD3011R, the following pins are NC. Pins 21, 36, 37 56, 72, 73 92, 108, 109, 125 to 128 and 144 Notes) • The 64-bit slot is a LSB first, two's complement output. The 48-bit slot is a MSB first, two's complement output. • ...
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... ( 0.36mA ( 5.5V – 0.25V (2) – 0.75V 3.6V – – 9 – CXD3011R Applicable Typ. Max. Unit pins ...
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... Input amplitude 3.3V ± 10 Min. Typ. Max. Unit 7 34 MHz = AV = 3.3V ± 10 Min. Typ. Max. Unit ns 13 500 ns 13 500 26 1000 ns V – 1.0 0 WLX V IHX V IHX IHX V ILX = AV = 3.3V ± 10 Min. Typ. Max. Unit + 0.3 Vp-p 2 – 10 – 0.9 /2 0.1 CXD3011R ...
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... CLOK DATA XLAT EXCK SQCK CNIN t WT 1/f SBSO SQSO 0V, Topr = –20 to +75° Min. Typ. Max 750 0.65 750 65 7 WCK – 11 – Unit MHz MHz ns kHz µs CXD3011R ...
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... SCLK MSB Min. Typ. Max 3.3V ± 10 Symbol Min. Typ COUT f 40 MIRR f 5 DFCTH B A – 12 – … … Unit MHz ns µ 0V, Topr = –20 to +75° Max. Unit Conditions kHz 1 kHz 2 kHz 3 CXD3011R LSB ...
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... Input LRCK hold time BCKI PCMDI LRCKI (V = 3.3V ± 10%, Topr = –20 to +75°C) DD Symbol Min. Typ. t BCK t 100 WIB t 10 IDS t 15 IDH t 10 ILRH t 15 ILRS t WIB t t IDS IDH t ILRH – 13 – Max. Unit MHz 4 WIB 50% t ILRS CXD3011R ...
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... V (rms) 0.81 dB 0.1 47k 100p 33k 100p 8.2k 33k 1000p 15k 39k 100p 15k PWMLP PWMLN CXD3011R PWMRP PWMRN – 14 – Remarks 8.2k 220p 8.2k 100 10µ 100k 15k 0.1µ 15k SHIBASOKU (AM51A) Analog 1ch Audio Circuit Audio Analyzer 2ch CXD3011R ...
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... Topr = –20 to +75° via a 33kΩ resistor.) DD Max. Unit Typ 0.97V 0.1V V 0.03V Typ. Max. Unit V 0.90V DD 0.03V 0. – 15 – Applicable pins FAO, TAO, SAO FAO, TAO, SAO Applicable pins FAO, TAO, SAO FAO, TAO, SAO CXD3011R ...
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... AVRG: Average AGCNTL: Auto gain control FCS: Focus TRK: Tracking SLD: Sled DFCT: Defect – 16 – CXD3011R ...
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... Total bit length for each register Register Total bit length 8 bits bits 3 16 bits bits 7 32 bits 8 32 bits 9 28 bits A 20 bits B 28 bits C 20 bits D 20 bits E D18 D19 D20 D21 D22 D23 – 17 – CXD3011R 750ns or more Valid ...
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... FOCUS GAIN DOWN PHASE COMPENSATE FILTER A K2B 44 FOCUS GAIN DOWN DEFECT HOLD GAIN K2C 4E FOCUS GAIN DOWN PHASE COMPENSATE FILTER B K2D 1B FOCUS GAIN DOWN OUTPUT GAIN K2E 00 NOT USED K2F 00 NOT USED Fix indicates that normal preset values should be used. CONTENTS – 32 – CXD3011R ...
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... K47 00 NOT USED K48 02 FOCUS HOLD FILTER INPUT GAIN K49 7F FOCUS HOLD FILTER A-H K4A 7F FOCUS HOLD FILTER A-L K4B 79 FOCUS HOLD FILTER B-H K4C 17 FOCUS HOLD FILTER B-L K4D 54 FOCUS HOLD FILTER OUTPUT GAIN K4E 00 NOT USED K4F 00 NOT USED CONTENTS – 33 – CXD3011R ...
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... FBIAS Count STOP SSTP TE Avrg Reg. FE Avrg Reg. VC Avrg Reg. TRVSC Reg. FB Reg. RFDC Avrg Reg. XBUSY FOK 0 GFS COMP COUT OV64 0 – 34 – CXD3011R Output data length — — — — — — — — 9 bits 9 bits 9 bits 9 bits 9 bits 8 bits — ...
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... High when Reg.B is latched, toggles each time the Reg.B number is input by CNIN. While $44 and $45 are being executed, toggles with each CNIN 8-count instead of the Reg.B number. Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing OV64 through the sync detection filter. – 35 – CXD3011R ...
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... TR2 0.18ms 0.09ms 0.36ms 0.18ms – 36 – Data 3 Timer range MT1 MT0 LSSL 0 AS1 RXF = 0 Forward RXF = 1 Reverse Timer range TR1 0.045ms 0.09ms CXD3011R 0 0 AS0 0 RXF 1 RXF RXF RXF RXF TR0 0.022ms 0.045ms ...
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... KF3 KF2 0.72ms 0.36ms Data 1 Data – 37 – KF1 KF0 SD2 SD1 11.6ms 5.8ms 5.8ms 2.9ms KF1 0.18ms Data CXD3011R SD0 2.9ms 1.45ms KF0 0.09ms Data ...
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... D1 D0 VCO SEL2 Processing DA output for DA output for 48-bit slot 64-bit slot 0dB OFF – ∞dB 0dB 0dB – ∞dB 0dB – ∞dB – ∞dB CXD3011R 0dB – ∞dB 0dB – ∞dB ...
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... Each output signal is output from the SQSO pin. Input the readout clock to SQCK (See Timing Chart 2-4.) The error rate is output from the SQSO pin. Input the readout clock to SQCK (See Timing Chart 2-6.) Application Anti-rolling is enhanced. Sync window protection is enhanced. Function Processing – 39 – CXD3011R —: Don't care ...
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... Output of wide-band PLL VCO2 selected by VCO2CS is 1/2 frequency-divided Output of wide-band PLL VCO2 selected by VCO2CS is 1/4 frequency-divided Output of wide-band PLL VCO2 selected by VCO2CS is 1/8 frequency-divided. Data VCO KSL3 KSL2 KSL1 SEL2 See the previous page. Processing Processing Processing Processing – 40 – KSL0 CXD3011R ...
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... Block Diagram of VCO Internal Path VCO1SEL No.1 VCO1 No.2 VCO1 No.3 VCO1 No.4 VCO1 VCO2SEL Low-speed VCO2 High-speed VCO2 1/1 1/2 1/4 1/8 VCO1CS1, 0 VCO1 internal path 1/1 1/2 1/4 1/8 VCO2CS VCO2 internal path – 41 – CXD3011R To DSP interior KSL3 DSP interior KSL1, 0 ...
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... No.3 (High-speed VCO for CXD3005R No.4 The CXD3011R has four multiplier PLL VCO1s, and this command selects one of these VCO1s. Four VCOs are No.3, No.4, No.2 and No.1 in order of the maximum frequency. Command bit VCO2 THRU = 0 V16M output is connected internally to VCKI. VCO2 THRU = 1 V16M output is not connected internally. Input the clock from VCKI. ...
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... Clock switching for servo block; externally input. FSTIN = 1 FSTIO pin serves as the input pin. The clock for servo block is input from FSTIO pin. Data SCSY SOCT1 0 0 Processing Processing Processing Processing – 43 – Data FSTIN 0 CXD3011R ...
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... Mute – 44 – Data BiliGL FLFC XWOC SUB Contents = 0 and 460Hz MDS = PWM polarity signal, carrier frequency of 132kHz MDP = PWM absolute value output (binary), carrier frequency of 132kHz MDS = Z MDP = ternary PWM output, carrier frequency of 132kHz = 1. B CXD3011R ...
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... SYCOF = 1 LRCK asynchronous mode. SYCOF = 0 Normal operation. Set SYCOF = 0 in advance in order to resynchronize the DAC using $9 command XWOC or the external pin XWO. DAC sync window is open. DAC sync window is not open. Data SYCOF 0 Processing Processing Processing – 45 – Processing CXD3011R ...
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... Left channel output Right channel output 0 Mute Mute Mute Mute – 46 – CXD3011R Remarks Mute Mute Mute Mute Mute Reverse Stereo Mono ...
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... Digital PLL master clock; conventional mode. (Preset) DIV4 = 1 Digital PLL master clock; 2/3 mode. Note) Do not set DIV4 to 1 when DSPB = 0. Data ZMUT ZDPL Processing Processing Processing Processing Data DIV4 Processing – 47 – CXD3011R Data ...
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... Data Mute ATT PCT1 Command bit PCM Gain ECC error correction ability 0dB C1: double; C2: quadruple 0dB C1: double; C2: quadruple Mute C1: double; C2: double 0dB C1: double; C2: double – 48 – Data PCT2 MCSL SOC2 Meaning ATT = 0 Attenuation off. ATT = 1 –12dB CXD3011R ...
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... When SOC2 = 0, SENS output is performed as usual. See "§ 1-4. Description of SENS Signals". When SOC2 = 1, the SQSO pin signal is output from the SENS pin. At this time, the readout clock is input to the SCLK pin. Note) SOC2 should be switched when SQCK = SCLK = high. Processing Processing – 49 – CXD3011R ...
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... Set DC offset to off when zero detection mute is on. Command bit FMUT = 1 Forced mute is on. FMUT = 0 Forced mute is off. Command bit BSBST = 1 Bass boost on. BSBST = 0 Bass boost off. Command bit BBSL = 1 Bass boost MAX. BBSL = 0 Bass boost MID. Data BSBST BBSL Processing Processing Processing Processing – 50 – CXD3011R ...
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... Audio output = 20log –0.017dB : –60.206dB – ∞ Data 1 Data – 51 – Data Attenuation data 1024 Data 3 Data CXD3011R [dB ...
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... When Gain CLVS = 0, GCLVS = –12dB. –12dB When Gain CLVS = 1, GCLVS = 0dB. –6dB –6dB 0dB 0dB +6dB Gain MDS1 Processing – 52 – Description D0 D1 PCC1 PCC0 Valid only when DCLV = 1. Valid when DCLV = Gain GMDS MDS0 0 –6dB 1 0dB 0 +6dB CXD3011R ...
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... The VPCO1 pin output is high and the VPCO2 pin is high impedance. The VPCO1 and 2 signals are output. The VPCO1 and 2 pin outputs are high impedance. The VPCO1 and 2 pin outputs are low. The VPCO1 and 2 pin outputs are high. Data Processing Processing – 53 – Processing D0 CXD3011R ...
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... The CXD3011R can serially output the 40 bits (10 BCD codes) of error rate data selected by EDC0 to 7 from the SQSO pin and monitor this data using a microcomputer. In order to output error rate data, set $C commands for C1 and C2 individually, and set SOCT0 and SOCT1 = command ...
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... Bottom hold at a cycle of RFCK/32 in CLVS and CLVH modes Bottom hold at a cycle of RFCK/16 in CLVS and CLVH modes Peak hold at a cycle of RFCK/4 in CLVS mode Peak hold at a cycle of RFCK/2 in CLVS mode Gain TP CLVS See "$CX commands". Description Description – 55 – CXD3011R ...
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... The rotational velocity R of the spindle can be expressed with the following equation. 256 – Relative velocity at normal speed = 1 n: VP0 to 7 setting value 1: Multiple set by VPCTL0, 1 Data VP5 VP4 VP3 VP2 Processing Processing – 56 – Data VP1 VP0 CTL1 CTL0 CXD3011R ...
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... Notes) 1. Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high. 2. Regarding the values in parentheses, the former ones are for when DSPB is 1 and VPCTL0 and the latter ones are for when DSPB is 1, VPCTL0 = 1 and VPCTL1 = 0. Description – 57 – CXD3011R ...
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... DSPB = 1 DSPB0 = VP0 to 7 setting value [HEX] DSPB = 1 DSPB = VP0 to 7 setting value [HEX] – 58 – CXD3011R When VPCTL0 = VPCTL1 = When VPCTL0 = 1, VPCTL1 = 0 ...
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... VC2C HIFC LPWR VPON Description Mode Description CLV-N Crystal reference CLV servo. Used for playback in CLV-W CLV-W 2 mode. CAV-W Spindle control with VP0 to 7. Spindle control with the external CAV-W PWM or with the external FG. 3 VCO-C VCO control CXD3011R D1 D0 ...
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... STOP 1-8 (c) KICK 1-9 (a) 0 BRAKE 1-9 (b) STOP 1-9 (c) KICK 1-10 (a) 1 BRAKE 1-10 (b) STOP 1-10 (c) KICK 1-11 (a) 0 BRAKE 1-11 (b) STOP 1-11 (c) KICK 1-12 (a) 1 BRAKE 1-12 (b) STOP 1-12 (c) Timing chart 0 1-13 0 1-14 0 1-15 1 1-16 0 1-17 (EPWM = 0, FGON = 0) 1 1-18 (EPWM = 0, FGON = 0) 0 1-19 (EPWM = 1, FGON = 0) 1 1-20 (EPWM = 1, FGON = 0) 0 1-21 (EPWM = 1, FGON = 1) 1 1-22 (EPWM = 1, FGON = 1) – 60 – CXD3011R ...
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... CAV0 • This sets the gain when controlling the spindle with VP7 Gain CAV-W mode. 0dB Note) Gain CAV1, 0 commands are not valid for spindle control –6dB with the external PWM or with the external FG. Processing – 61 – D0 INV VPCO CXD3011R ...
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... CLV-N mode DCLV = 1, DCLV PWM MD = LPWR = 0 KICK MDS Z H MDP Z FSW L H MON (a) KICK BRAKE MDS Z MDP L FSW L H MON (b) BRAKE BRAKE MDS Z Z MDP L FSW L H MON (b) BRAKE – 65 – CXD3011R STOP MDS Z MDP L FSW L MON L (c) STOP STOP MDS Z MDP Z FSW L MON L (c) STOP ...
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... FSW L H MON (b) BRAKE BRAKE MDS Z Z MDP L FSW L H MON (b) BRAKE Other than when following the velocity, the timing is the same as Timing Chart 1-6 (b). – 66 – CXD3011R STOP MDS MDP L FSW L MON L (c) STOP STOP MDS Z MDP Z FSW L MON L (c) STOP ...
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... CAV-W mode DCLV = 1, DCLV PWM MD = LPWR = 0 KICK MDS Z H MDP FSW L H MON (a) KICK BRAKE Z MDS MDP Z FSW L H MON (b) BRAKE BRAKE MDS Z MDP L FSW L H MON (b) BRAKE – 67 – CXD3011R STOP Z MDS MDP Z FSW L MON L (c) STOP STOP MDS Z MDP Z FSW L H MON (c) STOP ...
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... CLV-N mode DCLV PWM LPWR = 0 MDS MDP 132kHz 7.6µs BRAKE MDS Z MDP Z FSW L H MON (b) BRAKE Z n · 236 (ns Acceleration n · 236 (ns Output Waveforms with DCLV = 1 – 68 – CXD3011R STOP MDS Z MDP Z FSW L H MON (c) STOP Z Deceleration Deceleration ...
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... CAV-W mode EPWM = DCLV PWM MD = LPWR = 0 Acceleration MDP 264kHz 3.8µs Timing Chart 1-18 CAV-W mode EPWM = DCLV PWM LPWR=1 Acceleration MDP 264kHz 3.8µs Z Deceleration Z The BRAKE pulse is masked when LPWR = 1. Deceleration The BRAKE pulse is masked when LPWR = 1. – 69 – CXD3011R ...
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... CAV-W mode EPWM = 1, DCLV PWM LPWR = 1 H PWMI MDP Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin. Therefore, set DCLV PWM CLV-W and CAV-W modes. Acceleration Acceleration The BRAKE pulse is masked when LPWR = 1. – 70 – CXD3011R Deceleration ...
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... Internal FG reference clock H Z MDP Acceleration Note) CLV-W and CAV-W modes support control only by the ternary output of the MDP pin. Therefore, set DCLV PWM CLV-W and CAV-W modes Deceleration L The BRAKE pulse is masked when LPWR = 1. – 71 – CXD3011R ...
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... As a result, the 96-bit clock must be input in peak meter mode. • The absolute time after peak is stored in the memory in peak meter mode. (See Timing Chart 2-3.) • The high and low intervals for SQCK should be between 750ns and 120µs. – 72 – CXD3011R ...
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... Timing Chart 2-1 Internal PLL clock 4.3218 ± MHz WFCK SCOR EXCK SBSO WFCK SCOR EXCK SBSO S0• S0•S1 Same 750ns max S0 · Same Subcode P.Q.R.S.T.U.V.W Read Timing – 73 – CXD3011R ...
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... VF0 the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated from XTAL (XTLI, XTLO) (384Fs) is high. This value is 31 when the disc is rotating at normal speed and 63 when it is rotating at double speed (when DSPB is low). Load – 77 – CXD3011R m ...
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... Therefore, the cycles for the Fs system clock, PCM data and all other output signals from this LSI change according to the rotational velocity of the disc. Note) The capture range for this mode is theoretically up to the signal processing limit. Note) Set FLFC to 1 for this mode. – 79 – CXD3011R ...
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... V16M = 32 The VCO1 oscillation frequency is determined by V16M. The VCO1 frequency can be expressed by the following equation. • When DSPB = 0 49 VCO1 = V16M 24 • When DSPB = 1 49 VCO1 = V16M 16 n: VP0 to 7 setting value 1: VPCTL0, 1 setting value – 80 – CXD3011R ...
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... Fig. 3-1. Disc Stop to Regular Playback in CLV-W Mode CLV-W Mode CLV-W CLVP CLV-W MODE START KICK $E8000 Mute OFF $A00XXXX CAV-W $E665X (CLVA) NO ALOCK = H ? YES CLV-W $E6C00 (CLVA) (WFCK PLL) YES ALOCK = Fig. 3-2. CLV-W Mode Flow Chart – 81 – CXD3011R Operation mode Spindle mode Time ...
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... Switch to VCO control mode. $E00510 EPWM = SPDC = ICAP = SFSL = VC2C = LPWR = 0 HIFC = VPON = 1 Transfer Transfer VP0 $DX XX Track Jump Subroutine Transfer Switch to normal-speed playback mode. $E66500 EPWM = SFSL = VC2C = LPWR = 0 SPDC = ICAP = HIFC = VPON = 1 Access END – 82 – CXD3011R corresponds to VP0 to 7.) ...
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... EFM signal pulses. The block diagram of this PLL is shown in Fig. 4-1. The CXD3011R has a built-in three-stage PLL. • The first-stage PLL is a wide-band PLL. When using the internal VCO2, an external LPF is necessary; when not using the internal VCO2, external LPF and VCO are necessary. ...
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... MUX Digital PLL Spindle rotation information 1/2 1/32 1/2 1/l 1 256 (VPCTL0, 1) (VP7 to 0) 1/K (KSL1, 0) VPON 1/M 1/N 1/K (KSL3, 2) RFPLL – 84 – CXD3011R CLV-W CAV-W VPCO1 to 2 CLV-N CLV-W CAV-W /CLV-N LPF VCOSEL2 VCTL VCO2 V16M VCKI PCO FILI FILO CLTV VCO1 VCOSEL1 ...
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... For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5. • The CXD3011R uses refined super strategy to achieve double correction for C1 and quadruple correction for C2. • In addition, to prevent C2 miscorrection pointer is attached to data after C1 correction according to the C1 error status, the playback status of the EFM signal, and the operating status of the player. • ...
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... MNT2 MNT1 MNT0 § 4-4. DA Interface Output • The CXD3011R has two DA interface output modes. a) 48-bit slot interface output This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel. ...
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... There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD3011R supports type 2 form 1. This LSI supports 2 kinds of Digital Out generation methods; one is to generate the Digital Out using the PCM data read out from the disc and the other is to generate it using the DA interface input (PCMDI, LRCKI and BCKI) ...
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... Note) In this method, DOUT can be set to off by making the MD pin to 0 and $34A command DOUT CAT Table 4-6-2. – 90 – CXD3011R ...
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... WIN invalidate the automatic synchronization circuit. Clock System of DOUT Circuit For the DOUT block, the master clock is set using the clock control command MCSL ($A) employed by the DAC block. Set MCSL to 1 for 768fs and to 0 for 384fs. – 91 – CXD3011R ...
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... COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on. – 93 – CXD3011R ...
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... COUT or MIRR unlike for the other jumps. Transfer $25 from the microcomputer after the actuator has stabilized. 16 tracks. After kicking the actuator and sled, the traverse for the traverse monitor counter which is set with register B, and 16 tracks. Like the 2N-track jump, COUT is used for counting – 94 – CXD3011R 16 ...
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... Focus search up FOK = H NO YES FZC = H NO YES FZC = L NO YES Focus servo ON END Fig. 4-8-(a). Auto Focus Flow Chart Blind E Fig. 4-8-(b). Auto Focus Timing Chart – 95 – CXD3011R Check whether FZC is continuously high for the period of time E set with register 5. $08 ...
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... OFF WAIT (Blind A) COUT = NO YES Track REV kick WAIT (Brake B) Track, sled servo ON END Fig. 4-9-(a). 1-Track Jump Flow Chart $2C ($28) Fig. 4-9-(b). 1-Track Jump Timing Chart – 96 – (REV kick for REV jump) (FWD kick for REV jump) Brake B $25 CXD3011R ...
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... Track Track, sled FWD kick WAIT (Blind A) COUT = YES Track, REV kick C = Overflow ? NO YES Track, sled servo ON END Fig. 4-10-(a). 10-Track Jump Flow Chart COUT 5 count $2E ($2B) – 97 – (Counts COUT 5) Checks whether the COUT cycle is longer than overflow C. Overflow C CXD3011R $25 ...
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... COUT (MIRR YES Track REV kick C = Overflow NO YES Track servo ON WAIT (Kick D) Sled servo ON END Fig. 4-11-(a). 2N-Track Jump Flow Chart N count $2E ($2B) – 98 – Counts COUT for the first 16 times and MIRR for more times. Kick D Overflow C $25 $26 ($27) CXD3011R ...
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... Traverse Speed Ctrl (Overflow G) COUT = N? NO YES Track Servo ON Sled REV Kick WAIT (Kick D) Track Sled Servo ON END Fig. 4-12-(a). Fine Search Flow Chart Traverse Speed Control (Overflow G) & COUT N count Fig. 4-12-(b). Fine Search Timing Chart – 99 – CXD3011R Kick D $27 ($26) $25 ...
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... Command for servo $22 ($23) Fig. 4-13-(b). M-Track Move Timing Chart M Track Move Track Servo OFF Sled FWD Kick WAIT (Blind A) Counts COUT for M Counts MIRR for M COUT (MIRR YES Track, Sled Servo OFF END COUT (MIRR) M count – 100 – CXD3011R 16. 16. $20 ...
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... MDS MDP Up/down signal from CLVS servo Frequency error for CLVP servo Phase error for CLVP servo Spindle drive signal from the microcomputer for CAV servo Fig. 4-14. Block Diagram – 101 – CXD3011R MDP Error Measure Over Sampling Filter-1 Gain MDP ...
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... Playback Speed In the CXD3011R, the following playback modes can be selected through different combinations of XTLI, XTSL pin, double-speed command (DSPB), VCO1 selection command (VCOSEL1), VCO1 frequency division commands (KSL3, KSL2) and command transfer rate selector (ASHS) in CLV-N or CLV-W mode. XTSL Mode ...
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... DAC Block Input Timing The DAC input timing chart is shown below. Audio data is not transferred from the CD signal processor block to the DAC block inside the CXD3011R. This enables to send data to the DAC block via the external audio DSP, etc. When the data is input to the DAC block without using the audio DSP, the data must be connected outside the LSI ...
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... Y2. And, when the command X3 is sent before the audio output rteaches the figure), the audio output approaches Y3 from the value ( the figure) at that point. 0dB 400(H) Approx. 370ms when crystal = 16.9344MHz Approx. 185ms when crystal = 33.8688MHz 23.2 [ms] – 104 – CXD3011R – 000(H) ...
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... For resynchronization, set the $9X command XWOC the external pin XWO to low, wait for one LRCK cycle or more, and then set XWOC to 1 and XWO to high. When setting XWOC the external pin XWO to low, be sure to set the $9X command SYCOF to 0 beforehand. Soft mute on 23.2 [ms] – 105 – CXD3011R Soft mute off 23.2 [ms] ...
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... The bass boost is set using BSBST and BBSL of address A. See Graph 4-15 for the digital bass boost frequency response. 10.00 8.00 6.00 4.00 2.00 0.00 –2.00 –4.00 –6.00 –8.00 –10.00 –12.00 –14. 100 300 1k Digital bass boost frequency response [Hz] Graph 4-15. – 106 – CXD3011R Normal DBB MID DBB MAX 3k 10k 30k ...
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... Asymmetry Compensation Fig. 4-16 shows the block diagram and circuit example. ASYE R1 RFAC R1 BIAS Fig. 4-16. Asymmetry Compensation Application Circuit CXD3011R ASYO R1 R2 ASYI – 107 – CXD3011R ...
Page 108
... OSC 768fs XTLO XTSL To DAC block 1/2 2/3 To digital servo block 1/2 1/4 XT1D XT2D XT4D (Command $3E, $3F) – 108 – MCKO To exterior To CD signal processor block FSTIO FSTIN = 0: Output pin (Preset) Selector FSTIN = 1: Input pin FSTIN (Command $8X. "0" for preset; internally connected) CXD3011R ...
Page 109
... MCK = 128Fs) Input range: 1/4V Output format: 8-bit DAC Other: Sled move FOK, MIRR, DFCT signal generation RF signal sampling rate: 1.4MHz (when MCK = 128Fs) Input range: 1/4V Other: RF zero level automatic measurement – 109 – : Supply voltage) DD CXD3011R ...
Page 110
... XTSL XT4D XT2D XT1D Table 5-1. – 110 – CXD3011R Frequency division ratio MCK 1 256Fs 1/2 128Fs 1/2 128Fs 1 512Fs 1/2 256Fs 1/4 128Fs 1/4 128Fs Fs = 44.1kHz, : Don't care ...
Page 111
... DC Offset Cancel [AVRG (Average) Measurement and Compensation] (See Fig. 5-3.) The CXD3011R can measure the averages of RFDC, VC, FE and TE and compensate these signals using the measurement results to control the servo effectively. This AVRG measurement and compensation is necessary to initialize the CXD3011R, and is able to cancel the DC offset. ...
Page 112
... The number of steps by which the count value changes can be selected from steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to 1/512 A: Register mode B: Counter mode C: Counter mode (when stopped) – 112 – CXD3011R V /2. DD ...
Page 113
... TRVSC register TLC2 to FCS In register – + FBIAS register FBON to FZC register – register – RFLC to SLD In register – TLC2 · TLD2 to TRK In register – TRVSC register TLC2 to FCS In register – + FBIAS register FBON to FZC register – – 113 – CXD3011R ...
Page 114
... The default settings aim for 0dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary. Max. 11.4µs Timing Chart 5-4 – 114 – CXD3011R AGCNTL completion ...
Page 115
... AGCNTL coefficient reaches the appropriate value and stops changing, the CXD3011R confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self stop mode) This self-stop mode can be canceled by setting AGS to 0 ...
Page 116
... FOCUS SERVO OFF, 0V OUT 0 1 FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP Table 5-6. $02 $03 and performing only FCS search operation. $00 $02 $03 FCSDRV RF FOK FE 0 FZC – 116 – CXD3011R : Don't care $08 Fig. 5-8. ...
Page 117
... The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. The CXD3011R has 2 types of gain-up filter structures in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 5-17.) SLD Servo ...
Page 118
... Fig. 5-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B. RF Peak Hold1 Peak Hold2 Peak Hold2 –Peak Hold1 DFCT MIRR Comp (Mirror comparator level Fig. 5-11. SDF (Defect comparator level Fig. 5-12. – 118 – CXD3011R ...
Page 119
... When the upper 8 bits of the command register are $1, vibration detection can be monitored from the SENS pin. Anti Shock TE Filter TRK Gain Up Filter TRK Gain Normal Filter Hold Filter DFCT Servo Filter Fig. 5-13. ATSK Comparator TRK DAC Fig. 5-14. – 119 – CXD3011R Hold register EN SENS ...
Page 120
... ANTI SHOCK OFF 1 BRAKE ON 0 BRAKE OFF 0 TRACKING GAIN NORMAL TRACKING GAIN UP 1 TRACKING GAIN UP FILTER SELECT 1 1 TRACKING GAIN UP FILTER SELECT 2 0 Table 5-17. – 120 – Outer track Inner track REV FWD Servo ON JMP JMP Fig. 5-16. : Don't care CXD3011R ...
Page 121
... FCS AGCNTL coefficient result $3963: TRK AGCNTL coefficient result $391C: TRVSC adjustment result $391D: FBIAS register value t SPW … 1/f SCLK … MSB Fig. 5-18. Symbol Min. f SCLK t 31.3 SPW t 15 DLS Table 5-19. – 121 – LSB Unit Typ. Max. MHz 16 ns µs CXD3011R ...
Page 122
... The coefficient rewrite command is comprised of 24 bits, with D14 $34 as the address (D15 = 0) and data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is received. When rewriting multiple coefficients, be sure to wait 11.3µs (when MCK = 128Fs) before sending the next rewrite command. – 122 – CXD3011R ...
Page 123
... DD 0 Output value –B 64MCK 64MCK DD – 128 32MCK 32MCK 256 – 256 Timing Chart 5-22 Fig. 5-23. Drive Circuit – 123 – Output value 0 64MCK 32MCK 32MCK 32MCK – 256 DRV CXD3011R ...
Page 124
... When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control. – 124 – CXD3011R ...
Page 125
... No time limit 0 1 1.1ms 1 0 2.2ms 1 1 4.0ms D10 KA2 KA1 KA0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0 D10 Processing Processing – 125 – MRT2 MRT1 0 CXD3011R ...
Page 126
... Reference clock 10.8Hz 43.1Hz 86.1Hz 172.3Hz 344.5Hz 689.1Hz D10 COPY EMPH CAT DOUT DOUT DMUT Processing Processing Processing Processing – 126 – DOUT WIN DOUT 0 0 WOD EN MLSL CXD3011R ...
Page 127
... Digital Out is not generated from the DA interface input. DOUT EN2 = 0 Select when Digital Out is generated from the DA interface input. DOUT EN2 = 1 Note) In order to generate Digital Out from the DA interface, set DOUT and EN2 Preset Processing Processing Processing Processing Processing – 127 – CXD3011R ...
Page 128
... CXD3011R D. out DOUT output Mute F OFF — 0dB 0 The output from the PCM 1 data readout from a disc 0 1 – ∞dB 0 The output from the PCM 1 data readout from a disc ...
Page 129
... SFBK1: When 1, brake operation is performed by setting the LowBooster-1 input to 0. This is valid only when TLB1ON = 1. The preset is 0. SFBK2: When 1, brake operation is performed by setting the LowBooster-2 input to 0. This is valid only when TLB2ON = 1. The preset is 0. D10 – 129 – CXD3011R D0 0 ...
Page 130
... The sampling frequency is 88.2kHz (when MCK = 128Fs). Set SFJP ($36 TAOZ ($34D order to boost the low frequency for the TRK jump operation. Note 44.1kHz D10 FHB TLB1 FLB1 TLB2 – 130 – HBST1 HBST0 LB1S1 LB1S0 LB2S1 LB2S0 CXD3011R D0 ...
Page 131
... BK4 — –255/256 0 0 –511/512 –1023/1024 Table 5-25b. LowBooster-2 setting LB2S1 LB2S0 BK7 — –255/256 0 0 –511/512 1 1 –1023/1024 1 Table 5-25c. – 131 – CXD3011R BK2 BK3 96/128 2 112/128 2 120/128 2 BK5 BK6 1023/1024 1/4 2047/2048 1/4 4095/4096 1/4 BK8 BK9 1023/1024 1/4 2047/2048 1/4 4095/4096 1/4 ...
Page 132
... Fig. 5-26a. Servo HighBooster characteristics [FCS, TRK] (MCK = 128Fs) HBST1 = 0 HBST1 = 1, HBST0 = 100 1k Frequency [Hz 100 1k Frequency [Hz] HBST1 = 1, HBST0 = 1 3 – 132 – CXD3011R 10k 10k ...
Page 133
... Fig. 5-26b. Servo LowBooster1 characteristics [FCS, TRK] (MCK = 128Fs) LB1S1 = 0 LB1S1 = 1, LB1S0 = 100 Frequency [Hz] 1 100 Frequency [Hz] 3 – 133 – CXD3011R 1k 10k 1k 10k LB1S1 = 1, LB1S0 = 1 ...
Page 134
... Fig. 5-26c. Servo LowBooster2 characteristics [FCS, TRK] (MCK = 128Fs) LB2S1 = 0 LB2S1 = 1, LB2S0 = 100 Frequency [Hz] 1 100 Frequency [Hz] 3 – 134 – CXD3011R 1k 10k 1k 10k LB2S1 = 1, LB2S0 = 1 ...
Page 135
... When 1, the SLD drive DAC output is high impedance when the SLD servo is off. FGON: When 1, the phase comparison result is output to the MDP. (preset: 0) FGRS0: When 1, the frequency of the reference clock is multiplied by 1/64. (preset: 0) D10 FAOZ TAOZ SAOZ – 135 – FGON FGRS0 0 CXD3011R D0 0 ...
Page 136
... TV9 TV8 TV7 TV6 – 136 – FB5 FB4 FB3 FB2 FB1 V /4 respectively supply voltage TV5 TV4 TV3 TV2 TV1 V /4 respectively supply voltage CXD3011R D0 — D0 — TV0 ...
Page 137
... 0.769 preset PWM driver supply voltage supply voltage D10 TJ2 TJ1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0 supply voltage – 137 – CXD3011R D0 D0 ...
Page 138
... AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs) Default value: 0 (256ms) D10 / supply voltage); FE input conversion DD DD Slice level preset supply voltage FE/TE input conversion preset – 138 – CXD3011R D0 ...
Page 139
... Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off) Note) Commands marked with All commands are on when 1. D10 are accepted every 2.9ms. (when MCK = 128Fs) – 139 – CXD3011R D0 ...
Page 140
... FE AVRG register AVRG register input signal input signal input signal input signal – 140 – CXD3011R Readout data length 8 bits 16 bits 8 bits $399F $399E 8 bits $399D 9 bits 9 bits $399C $3993 8 bits ...
Page 141
... SJHD INBK MTI0 The counter changes once for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step 9 is approximately 1 supply voltage. DD TPS0 Relative gain 0 0dB +6dB 1 +12dB 0 +18dB 1 : preset CXD3011R D0 ...
Page 142
... DD DD SFO2 SFO1 Slice level 0 0 16/256 20/256 24/256 28/256 32/256 40/256 48/256 56/256 preset – 142 – CXD3011R D0 0 ...
Page 143
... DFCT maximum time No timer limit 2.00ms 2.36 2.72 : preset V V/ms, 44.1kHz) DD Count-down speed [V/ms] [kHz] 0.0431 V 22.05 DD 0.0861 V 44.1 DD 0.172 V 88.2 DD 0.344 V 176 preset supply voltage DD V V/ms, 352.8kHz) DD Count-down speed [V/ms] [kHz] 0.344 V 176.4 DD 0.688 V 352.8 DD 1.38 V 705.6 DD 2.75 V 1411 preset supply voltage DD – 143 – CXD3011R ...
Page 144
... COUT pin output STZC HPTZC COUT : preset, —: don't care Number of count-up steps per cycle – 144 – MRC1 MRC0 Setting time [µ 5.669 0 1 11.338 1 0 22.675 1 1 45.351 : preset (when MCK = 128Fs) CXD3011R D0 0 ...
Page 145
... SLD filter OFF OFF OFF Tracking zero level correction TRK filter SLD filter OFF OFF OFF VC level correction TRK filter SLD filter OFF OFF OFF : preset, —: don't care – 145 – CXD3011R D0 0 ...
Page 146
... Input coefficient sign inversion when SFID = 1 and THID = 1 The preset coefficients for the TRK filter are negative for input and positive for output. With this, CXD3011R outputs servo drives which are reversed phase of input errors. Negative input coefficient TE Negative input coefficient ...
Page 147
... D7 D6 MIRR, DFCT and FOK are all generated internally. MIRR only is input from an external source. MIRR, DFCT and FOK are all input from an external source. – 147 – LKIN COIN MDFI MIRI XT1D : preset, —: don't care CXD3011R D0 ...
Page 148
... XT4D Frequency division ratio 0 0 According to XTSL — — 1/1 1 — 1 1/4 – 148 – See $37 for AGGF and AGGT. The presets are AGG4 = 0, AGGF = 1 and AGGT = 1. : preset, —: don't care preset, —: don't care CXD3011R ...
Page 149
... Data Readout" on the following page.) AGHF: This halves the frequency of the internally generated sine wave during AGC. FTQ: The slope of the output during focus search is 1/4 of the conventional output slope. On when 1; default when 0 . SRO0 = 1 DA10 pin DA09 pin DA11 pin – 149 – CXD3011R ...
Page 150
... MSB LSB To the 7-segment LED • • • To the 7-segment LED MSB Data is connected to the 7-segment LED by 4bits at a time. This enables Hex display using four 7-segment LEDs oscilloscope, etc. Offset adjustment, gain adjustment CXD3011R LSB ...
Page 151
... FOCUS GAIN DOWN PHASE COMPENSATE FILTER A K2B 44 FOCUS GAIN DOWN DEFECT HOLD GAIN K2C 4E FOCUS GAIN DOWN PHASE COMPENSATE FILTER B K2D 1B FOCUS GAIN DOWN OUTPUT GAIN K2E 00 NOT USED K2F 00 NOT USED Fix indicates that normal preset values should be used. CONTENTS – 151 – CXD3011R ...
Page 152
... NOT USED K48 02 FOCUS HOLD FILTER INPUT GAIN K49 7F FOCUS HOLD FILTER A-H K4A 7F FOCUS HOLD FILTER A-L K4B 79 FOCUS HOLD FILTER B-H K4C 17 FOCUS HOLD FILTER B-L K4D 54 FOCUS HOLD FILTER OUTPUT GAIN K4E 00 NOT USED K4F 00 NOT USED CONTENTS – 152 – CXD3011R ...
Page 153
... CXD3011R ...
Page 154
... CXD3011R ...
Page 155
... CXD3011R ...
Page 156
... CXD3011R ...
Page 157
... Note) Set the MSB bit of the K02 and K04 coefficients to 0. M08 M09 – 1 – K14 K15 – 157 – TRK AUTO Gain – M01 M02 K05 K07 – SLD MOV K03 K04 Slice TZC Reg M0A Slice – K17 CXD3011R DAC AUTO Gain Reg ...
Page 158
... Note) Set the MSB bit of the K4A and K4C coefficients to 0. – 158 – M0A Comp K35 – K33 – K34 AVRG Reg M19 TRK K45 Hold Reg – K43 – K44 M11 FCS K4D Hold Reg 2 – K4B K4C CXD3011R Anti Shock Reg ...
Page 159
... When using the preset coefficients with the boost function off. FOCUS frequency response NORMAL GAINDOWN 10 100 1k f – Frequency [Hz] When using the preset coefficients with the boost function off. – 159 – CXD3011R 180° 90° G 0° –90° –180° 20k 180° 90° ...
Page 160
... ATSK DATA XLAT CLOK COUT COUT MIRR MIRR DFCT DFCT FOK TESO FSW FSW NC Circuit Driver Circuit Driver – 160 – CXD3011R NC XOLT DA12 SOCK DA13 SOUT DA14 BCKI DA15 PCMDI DA16 LRCKI LRCK WDCK WDCK PSSL ASYE ...
Page 161
... SONY CODE EIAJ CODE JEDEC CODE 144PIN LQFP(PLASTIC) 22.0 ± 0.2 20.0 ± 0 0.22 ± 0.05 0 0.22 ± 0.05 (0.2) DETAIL B PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LQFP-144P-L021 LQFP144-P-2020 LEAD MATERIAL PACKAGE MASS – 161 – CXD3011R 1.7 MAX EPOXY RESIN SOLDER PLATING COPPER ALLOY 1.3g ...