SY100EL14VZCTR Micrel Semiconductor, SY100EL14VZCTR Datasheet

SY100EL14VZCTR

Manufacturer Part Number

SY100EL14VZCTR

Description

SY100EL14VZCTR5V/3.3V 1:5 CLOCK DISTRIBUTION

Manufacturer

Micrel Semiconductor

Datasheet

1.SY100EL14VZCTR.pdf (4 pages)

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FEATURES

PIN CONFIGURATION/BLOCK DIAGRAM

PIN NAMES

3.3V and 5V power supply options

Typical 30ps output-to-output skew

Max. 50ps output-to-output skew

Synchronous enable/disable

Multiplexed clock input

75K internal input pull-down resistors

Available in 20-pin SOIC package

查询SY100EL14V供应商

CLK

SCLK

SEL

0-4

EN VCC NC SCLK CLK CLK V

Differential Clock Inputs

Scan Clock Input

Synchronous Enable

Clock Select Input

Reference Output

Differential Clock Outputs

TOP VIEW

SOIC

Function

SEL V

5V/3.3V 1:5 CLOCK

DISTRIBUTION

chip designed explicitly for low skew clock distribution

applications. The device can be driven by either a

differential or single-ended ECL or, if positive power

supplies are used, PECL input signal. The EL14V is

suitable for operation in systems operating from 3.3V to

5.0V supplies. If a single-ended input is to be used the

bypassed to ground via a 0.01 F capacitor. The V

output is designed to act as the switching reference for

the input of the EL14V under single-ended input

conditions, as a result this pin can only source/sink up to

0.5mA of current.

for the distribution of a lower speed scan or test clock

along with the high speed system clock. When LOW (or

left open and pulled LOW by the input pull-down resistor)

the SEL pin will select the differential clock input.

outputs will only be enabled/disabled when they are

already in the LOW state. This avoids any chance of

generating a runt clock pulse when the device is enabled/

disabled as can happen with an asynchronous control.

The internal flip flop is clocked on the falling edge of the

input clock, therefore all associated specification limits

are referenced to the negative edge of the clock input.

will pull down to V

* On next negative transition of CLK or SCLK

DESCRIPTION

TRUTH TABLE

The SY100EL14V is a low skew 1:5 clock distribution

The EL14V features a multiplexed clock input to allow

The common enable (EN) is synchronous so that the

When both differential inputs are left open, CLK input

CLK

/2.

output should be connected to the CLK input and

SCLK

and CLK input will bias around

SEL

ClockWorks™

SY100EL14V

Rev.: A

Issue Date: October 1999

Amendment: /0

Related parts for SY100EL14VZCTR

SY100EL14VZCTR Summary of contents

Page 1

FEATURES 3.3V and 5V power supply options Typical 30ps output-to-output skew Max. 50ps output-to-output skew Synchronous enable/disable Multiplexed clock input 75K internal input pull-down resistors Available in 20-pin SOIC package PIN CONFIGURATION/BLOCK DIAGRAM V EN VCC NC SCLK CLK ...

Page 2

Micrel ABSOLUTE MAXIMUM RATINGS Symbol V Power Supply ( (3) V Input Voltage ( Output Current OUT - Continuous - Surge T Operating Temperature Range A (1),(2) V Operating Range EE NOTES: 1. Absolute maximum ...

Page 3

... Normal operation is obtained if the HIGH level falls within the specified CMR range and the peak-to-peak voltage lies between V table assume a nominal V = -3.3V. For PECL operation, the V EE PRODUCT ORDERING CODE Ordering Package Code Type SY100EL14VZC Z20-1 SY100EL14VZCTR Z20-1 = GND T = – Min. Max. Min. Max. ...

Page 4

Micrel 20 LEAD SOIC .300" WIDE (Z20-1) MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 TEL This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use ...

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