LT6552CS8#TR Linear Technology, LT6552CS8#TR Datasheet - Page 6

• Manufacturer Part Number: LT6552CS8#TR
• Description: IC OPAMP VID DIFF SGL 3.3V 8SOIC
• Manufacturer: Linear Technology

Specifications of LT6552CS8#TR

• Applications: Differential
• Number Of Circuits: 1
• -3db Bandwidth: 75MHz
• Slew Rate: 600 V/µs
• Current - Supply: 14mA
• Current - Output / Channel: 70mA
• Voltage - Supply, Single/dual (±): 3 V ~ 12.6 V, ±1.5 V ~ 6.3 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

LT6552
SYMBOL
t
t
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The inputs are protected from ESD with diodes to the supplies.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum.
Note 4: The LT6552C/LT6552I are guaranteed functional over the
temperature range of –40 C to 85 C.
Note 5: The LT6552C is guaranteed to meet specified performance from
0 C to 70 C and is designed, characterized and expected to meet specified
performance from –40 C to 85 C, but is not tested or QA sampled at these
temperatures. The LT6552I is guaranteed to meet specified performance
from – 40 C to 85 C.
temperature range, otherwise specifications are at T
V
6
ON
OFF
DIFF
5V ELECTRICAL CHARACTERISTICS
V
REF
= 0V, V
+
–
SHDN
– +
+
–
Figure 1. 3.3V, 5V DC Test Circuit
V
V
DIFF
= V
CM
PARAMETER
Shutdown Pin Current
Turn-On Time
Turn-Off Time
Shutdown Output Leakage Current
+
, unless otherwise noted. R
REF
–IN
+IN
V
–
100
0.1%
R
G
SHDN
V
OUT
SHDN
FB
V
+
+
–
+
–
V
+
1 F
L
= R
F
A
CONDITIONS
V
V
V
V
V
R
900
0.1%
R
+ R
6552 F01
SHDN
SHDN
SHDN
SHDN
SHDN
F
L
= 25 C. V
G
= –4.5V
= 4.7V
from – 4.5V to 4.7V
from 4.7V to –4.5V
= –4.5V, V
= 1k. (Note 6)
The denotes the specifications which apply over the full operating
S
Note 6: When R
R
value is added to the output.
Note 7: V
input pairs and is input referred.
Note 8: Minimum supply is guaranteed by the PSRR test.
Note 9: Full power bandwidth is calculated from the slew rate.
Note 10: V
V
= 5V. Figure 2 shows the DC test circuit, V
L
S
–
= 150 or R
= 5V and 5V tests.
FPBW = SR/2 Vp
V
OUT
OS
S
–
+
+
–
measured at the output (Pin 6) is the contribution from both
= 3.3V, t
V
V
V
CM
+
DIFF
L
L
= 75 is specified, then an additional resistor of that
= 1k is specified, the load resistor is R
–
+
V
Figure 2. 5V DC Test Circuit
r
–
and t
f
limits are guaranteed by correlation to
1 F
REF
–IN
+IN
V
–
100
0.1%
R
G
MIN
SHDN
V
OUT
SHDN
FB
V
+
+
–
0.25
TYP
200
400
85
3
+
–
REF
V
F
+
+ R
1 F
MAX
250
10
= V
G
, but when
CM
R
900
0.1%
R
6552 F02
= 0V,
F
L
UNITS
6552f
ns
ns
A
A
A