LT6553IGN#TR Linear Technology, LT6553IGN#TR Datasheet - Page 9

• Manufacturer Part Number: LT6553IGN#TR
• Description: IC AMP VIDEO TRIPLE GAIN2 16SSOP
• Manufacturer: Linear Technology

Specifications of LT6553IGN#TR

• Applications: General Purpose
• Number Of Circuits: 3
• -3db Bandwidth: 650MHz
• Slew Rate: 2500 V/µs
• Current - Supply: 8mA
• Current - Output / Channel: 70mA
• Voltage - Supply, Single/dual (±): 4.5 V ~ 12 V, ±2.25 V ~ 6 V
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIO S I FOR ATIO
If the AGND pins are not connected directly to a low
impedance ground plane, they must be carefully bypassed
to maintain minimal impedance over frequency. Pin 6 is a
shared connection of the gain resistors of both channel G
and channel B, and any resistance external to this node can
significantly decrease the isolation between those chan-
nels. Although crosstalk will be very dependent on the
board layout, a recommended starting point for bypass
capacitors would be 470pF as close as possible to each
AGND pin with one 4700pF capacitor in parallel.
To maintain the LT6553’s channel isolation, it is beneficial
to shield parallel input and output traces using a ground
TYPICAL APPLICATIO
RGB Buffer Demo Board
The DC714 Demo Board illustrates optimal routing,
bypassing and termination using the LT6553 as an
RGB video buffer. The schematic is shown in Figure 1. All
inputs and outputs are routed to have a characteristic
impedance of 75 and 75 input shunt and output series
CAL
INR
ING
INB
AGND
5
4
3
2
5
4
3
2
5
4
3
2
5
4
3
2
EN
50 BNC
5 4 3 2
BANANA
BNC 3
JACK
BNC
1
J1
J5
J6
J7
J3
J8
1
1
1
1
U
AGND
Z = 75
Z = 75
Z = 75
E3
AGND
1 2
SINGLE
DGND
JP2
1
SUPPLY
U
FLOAT
R4
75
JP3
3
2
DUAL
3
R5
75
DGND
EN
E1
E2
U
ENABLE
W
1 2
R6
75
CONTROL
C5
470pF
JP1
EXT
Figure 1. DC714 Demo Board Schematic
3
C6
1000pF
U
1
2
3
4
5
6
7
8
EN
DGND
INR
AGND
ING
AGND
INB
V
–
C7
470pF
LT6553
OUTR
OUTG
OUTB
V
V
V
V
V
C8
4700pF
+
+
–
+
–
plane or power supply traces. Vias between topside and
backside metal may be required to maintain a low
inductance ground near the part where numerous traces
converge.
ESD Protection
The LT6553 has reverse-biased ESD protection diodes on
all pins. If any pins are forced a diode drop above the
positive supply or a diode drop below the negative supply,
large currents may flow through these diodes. If the
current is kept below 10mA, no damage to the devices will
occur.
terminations are connected as close to the part as pos-
sible. For ideal operation, a 75 load termination should
be connected at the output. The LT6553’s gain of 2 will
compensate for the resulting divider between the series
and load termination resistors.
16
15
14
13
12
11
10
9
C9
10 F, 16V
1210
C1
4700pF
75
75
75
R1
R2
R3
C2
470pF
Z = 75
Z = 75
Z = 75
Z = 75
C3
4700pF
C4
10 F, 16V
1210
V
V
BANANA JACK
+
–
BANANA
1
1
1
1
NOTE 5
BNC x3
JACK
BNC
J10
J11
J12
J2
J9
J4
V
V
+
–
LT6553
5
4
3
2
5
4
3
2
5
4
3
2
5
4
3
2
6553 F01
OUTR
OUTG
OUTB
CAL
9
6553f