TDA9115 SGS-Thomson-Microelectronics, TDA9115 Datasheet
TDA9115
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TDA9115 Summary of contents
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... External sawtooth configuration Synchronization on hor. frequency with phase selection Selectable polarity of drive signal DESCRIPTION The TDA9115 is a monolithic integrated circuit as- sembled in a 32-pin shrink dual-in-line plastic package. This IC controls all the functions related to horizontal and vertical deflection in multimode or multi-frequency computer display monitors. ...
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CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... BRegIn BISense 1 32 VDyCor VSyn 2 31 SDA 3 30 SCL HOscF 29 Vcc 4 28 BOut GND HGND 26 7 HOut RO 25 XRay EWOut HPosF 10 23 VOut HMoiré VCap HFly 21 VGND 12 RefOut 13 20 VAGCCap VOscF VEHTIn HEHTIn TDA9115 3/45 ...
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... VDyCor amplitude V-ramp control Tracking EHT Vertical size Vertical position Vertical moiré VDyCor VOut VEHTIn HEHTIn H-drive HOut 26 buffer Safety XRay 25 processor 28 BOut B+ 16 BISense DC/DC converter BRegIn 15 controller BComp 14 HMoiré generator H size EWOut 24 Pin cushion Keystone TDA9115 ...
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... EWOut E/W Output 25 XRay X-Ray protection input 26 HOut Horizontal drive Output 27 GND Main GrouND 28 BOut B+ DC/DC converter controller Output 29 Vcc Supply voltage 2 30 SCL I C bus Serial CLock Input 2 31 SDA I C bus Serial DAta input/output 32 VDyCor Vertical Dynamic Correction output TDA9115 Function 5/45 ...
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... TDA9115 4 - QUICK REFERENCE DATA Characteristic General Package Supply voltage Supply current Application category Means of control/Maximum clock frequency EW drive DC/DC convertor controller Horizontal section Frequency range Autosync frequency ratio (can be enlarged in application) Positive/Negative polarity of horizontal sync signal/Automatic adaptation Duty cycle of the drive signal ...
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... Pins HLckVBk, CO, RO, HPLL1F, HPosF, HMoiré, BRegIn, BI- V (pin) Sense, VAGCCap, VCap, VDyCor, HOscF, VOscF Pin HPLL2C Pin HFly ESD susceptibility V ESD (human body model: discharge of 100pF through 1. Storage temperature stg T Junction temperature j Parameter TDA9115 Value Unit Min Max -0.4 13 -0.4 5.5 V -0.4 V ...
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... TDA9115 6 - ELECTRICAL PARAMETERS AND OPERATING CONDITIONS 2 Medium (middle) value Bus control or adjustment register composed of bits D0, D1,...,Dn is the one having Dn at ”1” and all other bits at ”0”. Minimum value is the one with all bits at 0, maximum value is the one with all at ” ...
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... V >V (HFly) ThrHFly At top of H flyback pulse No PLL2 phase modula- (6) tion (5) (5) Null asym. correction Null asym. correction Output driven LOW Soft-start/Soft-stop value HPOS (Sad01): 11111111b 00000000b TDA9115 Value Units Min. Typ. Max. 1.5 mA 390 pF 150 kHz 27 28.5 29.9 kHz 29 122 kHz -150 ppm ...
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... TDA9115 Symbol Parameter Contribution of pin cushion asymmetry t /T correction to phase of H-drive vs. static PCAC H phase (via PLL2), measured in corners Contribution of parallelogram correction phase of H-drive vs. static phase (via ParalC H PLL2), measured in corners Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must always be higher than the free-running frequency ...
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... VOCapt VO VOCapt = 8V RefO VPOS (Sad08): x0000000b x1000000b x1111111b VSIZE (Sad07): x0000000b x1000000b x1111111b 2 Cbit VOutEn VEHT RefO (min) VEHT VEHT RefO TDA9115 Value Units Min. Typ. Max 1.8 1 100 Hz 50 185 Hz 0 ...
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... TDA9115 Note 11: The threshold for V is generated internally and routed to VOscF pin. Any DC current on this pin will VOB influence the value VOB Note 12: Maximum of deviation from an ideally linear sawtooth ramp at null CCOR (Sad0A at x1000000b). The same rate applies to V-drive signal on VOut pin. ...
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... minus (voltage versus parabola component voltage (contribution of PCC and keystone correction). EW-DC V [fmax] is the value at condition TDA9115 Value Units Min. Typ. Max. 0 %/V 20 %/V 0 %/V 1.75 %/ >V . HOThrfr 13/45 ...
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... TDA9115 6.7 DYNAMIC CORRECTION OUTPUTS SECTION V = 12V amb Symbol Parameter Vertical Dynamic Correction output VDyCor I Current sunk from VDyCor output VDyCor DC component of the drive signal V VD-DC on VDyCor output Amplitude of V-parabola on VDy (21) VD-V Cor output Tracking of V-parabola on VDyCor VD V – ...
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... Test Condit ions input BRegIn (18) Low frequency (18) HBOutEn = ”Enable” HBOutEn = ”Disable” I =10mA BOut V =8V RefO BOutPh = ”0” The same values to be found on pin BRegIn, while regulation loop is TDA9115 Value Units Min. Typ. Max 100 dB 6 MHz -0.2 A -0.5 2.0 mA (32) 0 ...
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... TDA9115 6.9 MISCELLANEOUS V = 12V amb Symbol Parameter Vertical blanking and horizon tal lock indication composite outpu t HLckVBk I Sink current to HLckVBk pin SinkLckBk V Output voltage on HLckVBk output OLckBk Horizontal moiré canceller V H-moiré pulse amplitude on HMoiré pin AC-HMoiré ...
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... C-correction 0A VOut x1111111 Byte Waveform V amp(min) V mid(VOut) V amp(max) V mid(VOut) 3.5V V mid(VOut) 3.5V V mid(VOut) V mid(VOut) 3.5V V VOamp Null V VOS-cor V VOamp Max. 1 VOamp V VOC-cor 0 1 VOamp Null V VOamp V VOC-cor 0 1 TDA9115 Effect on Screen 17/45 ...
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... TDA9115 Function Sad Pin x0000000: Vertical moiré 0B VOut amplitude x1111111: 00000000 Horizontal size 10h EWOut 11111111 x0000000 Keystone 0D EWOut correction x1111111 x0000000 Pin cushion 0C EWOut correction x1111111 x0000000 Parallelogram 12h correction x1111111 x0000000 Pin cushion asymmetry 11h correction x1111111 18/45 Byte ...
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... H asymmetry, displayed in the table, weight of the other relevant components is nullified (minimum for parabola, S-correction, medium for keystone, all corner corrections, C-correction, parallelogram, parabola asymmetry correction, written in corresponding registers). Byte Waveform VDyCorPo V VD-V(max) V VD- VD-V(max) V VD- TDA9115 Effect on Screen t VR Application dependent t VR 19/45 ...
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... TDA9115 BUS CONTROL REGISTER MAP The device slave address write mode and 8D in read mode. Bold weight denotes default value at Power-On-Reset Bus data in the adjustment register is buffered and internally applied with discharge of the vertical os- cillator . In order to ensure compatibility with future devices, all “Reserved” bits should be set to 0. ...
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... Reset with automatic return of the bit to 0 This bit is not latched, it will return itself. Sad17/D0 - BlankMode Blanking operation Mode 0: Blanking pulse starting with detection of vertical synchronization pulse and ending with end of vertical oscillator discharge TDA9115 PLL1InhEn HLockEn ...
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... TDA9115 (start of vertical sawtooth ramp on the VOut pin) 1: Permanent blanking - high blanking level in composite signal on pin HLckVBk is per- manent Sad17/D1 - VOutEn Vertical Output Enable 0: Disabled VOut pin (see 6.5 offVOut Vertical section) 1: Enabled, vertical ramp with vertical position offset on VOut pin ...
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... The device is equipped with an au- tomatic mode (switched on or off by VSyncAuto bus bit) that uses the detection information. TDA9115 2 C bus 2 C bus slave, compatible with 2 C bus sub- ...
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... TDA9115 Figure 2. Horizontal sync signal Positive T H Negative Figure 3. Extraction of V-sync signal from H/V-sync signal H/V-sync PulseHsyn Internal Integration Extracted V-sync 9.2.2 Automatic sync. selection mode bus bit VSyncAuto is set this mode, the 2 device itself controls the I C bus bits switching the polarity inverters and the vertical sync ...
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... High INHIBITION CHARGE PUMP HPosF Low 10 PLL1Pump SHAPER HOscF HOThrHi + HOThrLo HOThrHi V HOThrLo TDA9115 can be disabled through V-sync (extracted) HPLL1F R0 C0 HOscF VCO HOSC HPOS Flip-Flop VCO discharge control 25/45 ...
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... TDA9115 9.3.3 Voltage controlled oscillator The VCO makes part of both PLL1 and PLL2 loops, being an “output” to PLL1 and “input” to PLL2. It delivers a linear sawtooth. Figure 6 ex- plains its principle of operation. The linears are ob- tained by charging and discharging an external ca- pacitor on pin CO, with currents proportional to the ...
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... HMoiré bus bit. This bit kept at 0 for common architecture (B+ and EHT common regulation) and at 1 for separated architecture (B+ and EHT each regulated separately). TDA9115 26 HOut int. ext bus bit to protect external (“ ...
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... TDA9115 Figure 10. Control of HOut and BOut at start/stop at nominal V V (HPosF) V HPosMax V HBNorm V BOn V Soft start HOn Start Start HOut BOut HOut H-duty cycle BOut (positive) B-duty cycle 9.4 VERTICAL SECTION 9.4.1 General The goal of the vertical section is to drive vertical deflection output stage. It delivers a sawtooth ...
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... EW tom limitation seems to be critical for maximum horizontal size (minimum DC). Actually it is not critical since the parabola component must always be applied. As all the components of the resulting correction waveform are generated from the out- TDA9115 V value (and so RefO 2 C bus control,. Transconductance amplifier ...
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... TDA9115 put vertical deflection drive waveform, they all track with real vertical amplitude and position (in- cluding breathing compensation), thus being fixed vertically on the screen. They are also affected by C- and S-corrections. The sum of components oth- er than DC is affected by value in HSIZE I control in reversed sense. Refer to electrical spec- ifications for value ...
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... BOutPol I bit. A NPN transistor open-collector is routed out to the BOut pin. During the operation, a sawtooth found on pin BISense, generated externally by the applica- tion. According to BOutPh I flop is set either at H-drive signal edge (rising or falling, depending on BOHEdge I TDA9115 V (max HSIZE ( ...
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... TDA9115 certain delay ( after middle of H-fly- BTrigDel H back. The output is set On at the end of a short pulse generated by the monostable trigger. Timing of reset of the R-S flip-flop affects duty cy- cle of the output square signal and so the energy transferred from DC/DC converter input to its out- put ...
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... HOut and BOut outputs are inhibited (switched off) after a 2-horizontal deflection line delay provided to avoid erratic excessive X-ray condition detec- tion at short parasitic spikes. This protection is latched; it may be reset either drop bus bit XRayReset (see chap ter I C BUS CONTROL REGISTER MAP on page 20). TDA9115 33/45 ...
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... TDA9115 Figure 15. Safety functions - block diagram HBOutEn supervision V CC CCEn + V CCDis _ 29 Vcc XRayReset XRay ThrXRay H-VCO HFly discharge 12 + control _ V ThrHFly VOutEn BlankMode HlockEn H-lock detector R Q V-sawtooth discharge S V-sync 34/45 HPosF ...
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... V thresholds), if the X-ray protection is ac- CCDis tive or if the V-drive signal is disabled by VOutEn bus bit blank/blank level L2 - H-lock/unlock level L1 (H) L1 +L2 (L) (H) L1 +L2 (H) (L) No Yes Yes No TDA9115 2 C bus bit, when 2 C bus bit, is also V CCEn +L2 (H) Yes No 35/45 ...
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... TDA9115 Figure 17. Ground layout recommendations 36/ TDA9115 General Ground ...
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... INTERNAL SCHEMATICS Figure 18. 5V Pins 1-2 200 H/HVSyn VSyn Figure 19. 12V 13 RefOut HLckVBk l 3 Figure 20. 12V Pin 13 HOSCF Pin 4 Figure 21. RefOut 12V 13 5 HPLL2C Figure 22. 12V RefOut Figure 23. 12V RefOut TDA9115 37/45 ...
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... TDA9115 Figure 24. HPLL1F 9 Figure 25. RefOut 12V HPosF 10 Figure 26. 12V 5V HMoiré 11 38/45 Figure 27. 12V HFly 12 Figure 28. BComp 14 Figure 29. 5V BRegIn 12V 15 ...
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... Figure 30. 12V BISense 16 Figure 31. 12V 18 VEHTIn 17 HEHTIn Figure 32. 12V Pin 13 VOSCF 19 Figure 33. 12V VAGCCap 20 Figure 34. 12V 22 VCap Figure 35. 12V VOut 23 TDA9115 39/45 ...
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... TDA9115 Figure 36. 12V 24 EWOut 32 VDyCor Figure 37. 12V XRay 25 Figure 38. 12V 26 HOut 28 BOut 40/45 Figure 39. 30 SCL 31SDA ...
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... TDA9115 Inches Typ. Max. 0.148 0.200 0.140 0.180 0.018 0.023 0.040 0.055 0.010 0.014 1.100 1.120 0.410 0.435 0.350 0.370 ...
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... TDA9115 12 - GLOSSARY AC Alternate Current ACK ACKnowledge bit of I AGC Automatic Gain Control COMP COMParator CRT Cathode Ray Tube DC Direct Current EHT Extra High Voltage EW East-West H/W HardWare HOT Horizontal Output Transistor Inter-Integrated Circuit IIC Inter-Integrated Circuit MCU Micro-Controller Unit NAND Negated AND (logic operation) ...
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PRODUCT PREVIEW June 2000 version 2.0 Document created (issued from TDA9112) Work on figures and text; version finalized and displayed on Intranet. July 2000 version 2.1 Sentence modified in first page : The internal sync processor.;.” replaced by :”the device ...
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Section 6.8 addition of min and max values for V for V BOSat Section 6.9 addition of min and max values for V Section 9.4 “stabilizing time” changed to “stabilization time” (twice) Section 6.9 : max values for vertical moiré ...
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... C system is granted provided that the system conforms to the I STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S. Patent. Rights to use these 2 C Standard Specification as defined by Philips. http:// www.st.com TDA9115 45/45 ...