TDA9203A SGS-Thomson-Microelectronics, TDA9203A Datasheet
TDA9203A
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TDA9203A Summary of contents
Page 1
... RGB signals is performed thanks to a flexible integrated system. The white balance adjustment is effective on brightness, video and OSD signals. The TDA9203A works for application using coupled CRT driver. The ABL input provides a 12dB Max. attenuation on the current contrast value according average beam limitation voltage ...
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... Serial Clock Line BLOCK DIAGRAM BLK 14 CLAMP V REF IN1 1 AGND 6 BLUE CHANNEL IN2 4 GREEN CHANNEL IN3 7 ABL 9 BPCP LGND 10 LATCHES BUS DECODER TDA9203A HSYNC SDA SCL 2/13 Name Pin Type FBLK 13 I BLK 14 I PGND3 15 I/O OUT3 CC3 PGND2 18 I/O OUT2 ...
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... Figure 4). The DC output level during the blanking pulse, is forced to ”INFRA-BLACK” level (V Drive Adjustment ( bits order to adjust the white balance, the TDA9203A offers the possibility to adjust separatelythe overall gain of each complete video channel. The gain of each channel is controlled by I The very large drive adjustment range(48dB) allows different standard or custom color temperature ...
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... Data Transfer Output The host MCU can write data into the TDA9203A registers. Read mode is not available. Video To write data into the TDA9203A, after a start, the OSD (1) MCU must send (see Figure 6) : Video 2 - The I C addressslave byte with a low level for the OSD R/W bit ...
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... OSD min. = 360mV OUT1 OUT2 OUT3 V OSD BRT Two exemples of drive adjustment ( CONT BRT Register Address ACK TDA9203A CONT BRT 0.4V fixed = 0. CONT and V . OSD and V . BLACK Data Byte ACK Stop ...
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... TDA9203A QUICK REFERENCE DATA Symbol Signal Bandwidth (4V /12pF load) PP Rise and Fall Time (4V /12pF load) PP Drive Adjustment Range on the 3 Channels separately Maximum Output Voltage (V Output Voltage Range (AC + DC) ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage (Pins 3-9-17-20-23 Voltage at any Input Pins (except SDA & SCL & Logical Inputs) ...
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... V = 5.3V Typical ABL V = 2.8V Typical ABL V = 5.3V ABL See Figure 12V, unless otherwise specified) amb CC Test Conditions On Pins SDA, SCL 0.4V < V < 4.5V IN SDA Pin when ACK Sink Current = 6mA TDA9203A Min. Typ. Max. Unit 0 MHz PP 0 5 ...
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... TDA9203A INTERFACE TIMINGS REQUIREMENTS (see Figure 7) Symbol t Time the bus must be free between 2 access BUF t Hold Time for Start Condition HDS t Set-up Time for Stop Condition SUP t The Low Period of Clock LOW t The High Period of Clock HIGH t Hold Time Data ...
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... BRT ( 0.010 0.020 0.040 0.080 0.160 0.320 0.640 1. 1 2.56 TDA9203A POR Value (dB) POR Value - -30 -24 -18 - POR Value X 9/13 ...
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... TDA9203A REGISTER DESCRIPTION (continued) Drive Registers (R3, R4, R5) (Video IN = 0.5V Hex ...
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... LGND 10 LGND AGND Figure HSYNC 24 AGND LGND Figure BLK - FBLK P ins 2-5-8-13-14 AGND Figure 11 Internal 10k ABL 9 AGND Figure ins 11-12 (10V) AGND Figure ins 17-20- AGND P GND P ins 15-18-21 TDA9203A AGND LGND OUT Pins 16-19-22 11/13 ...
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... TDA9203A APPLICATION DIAGRAM 100nF 47 B GND B 75 100nF 47 R GND R 75 100nF 47 G GND ABL GND FBLK TEST VSYNC HSYNC + PXCK GND CKOUT 2 RESET XTAL OUT SDA 10 8MHz XTAL IN ...
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... Max. Min. 5.08 0.020 4.57 0.120 0.56 0.0142 0.0181 1.14 0.030 0.38 0.0090 0.0098 23.11 0.890 8.64 0.30 6.86 0.240 10.92 1.52 3.81 0. system, is granted provided that the system conforms to TDA9203A .015 0,38 Gage Plane Typ. Max. 0.20 0.130 0.180 0.0220 0.040 0.045 0.0150 0.90 0.910 0.340 0.252 0270 0.070 0.30 0.430 0.060 0.130 ...