TDA9113 SGS-Thomson-Microelectronics, TDA9113 Datasheet
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TDA9113
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TDA9113 Summary of contents
Page 1
... Bus-controlled output voltage Synchronization on hor. frequency with phase selection Selectable polarity of drive signal DESCRIPTION The TDA9113 is a monolithic integrated circuit as- sembled in a 32-pin shrink dual-in-line plastic package. This IC controls all the functions related to horizontal and vertical deflection in multimode or multi-frequency computer display monitors. ...
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CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... TDA9113 1 - PIN CONFIGURATION H/HVSyn HLckVBk HPLL2C HPLL1F HDyCor BComp BRegIn BISense 4/ VDyCor VSyn 2 31 SDA 3 30 SCL HOscF 29 Vcc 4 28 BOut GND HGND 7 26 HOut RO 25 XRay EWOut HPosF 10 23 VOut 11 22 VCap HFly 21 VGND 12 RefOut 13 20 ...
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... Vertical moiré VDyCor VOut VEHTIn HEHTIn H-drive HOut 26 buffer Safety 25 XRay processor 28 BOut B+ 16 BISense DC/DC converter BRegIn 15 controller B+ ref. BComp 14 H-dynamic correction (focus,brightness) HDyCor 11 HDyCor amplitude HDyCor symmetry EW generator H size Pin cushion EWOut 24 Keystone Top corners Bottom corners TDA9113 ...
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... TDA9113 3 - PIN FUNCTION REFERENCE Pin Name 1 H/HVSyn TTL compatible Horizontal / Horizontal and Vertical Sync. input 2 VSyn TTL compatible Vertical Sync. input 3 HLckVBk Horizontal PLL1 Lock detection and Vertical early Blanking composite output 4 HOscF High Horizontal Oscillator sawtooth threshold level Filter input ...
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... Tracking of horizontal waveform component with Horizontal size/EHT Tracking of vertical waveforms (component) with V. size & position DC/DC controller section Step-up/Step-down conversion mode Internal/External sawtooth configuration Bus-controlled output voltage Soft start/Soft stop feature Positive(N-MOS)/Negative(P-MOS) polarity of BOut signal TDA9113 Value Unit SDIP ...
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... TDA9113 5 - ABSOLUTE MAXIMUM RATINGS All voltages are given with respect to ground. Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed positive. Symbol V Supply voltage (pin Vcc) CC Pins HEHTIn, VEHTIn, XRay, HOut, BOut Pins H/HVSyn, VSyn, SCL, SDA ...
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... Parameter Min. 0 Test Condit ions V = 12V 12V -2mA CC RefO Test Condit ions Pin H/HVSyn Pins H/HVSyn, VSyn Pins H/HVSyn, VSyn Pin H/HVSyn, cap. on pin CO = 820pF Pin H/HVSyn TDA9113 Value Unit Typ. Max C/W Value Units Min. Typ. Max. 10 ...
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... TDA9113 6.4 - HORIZONTAL SECTION Vcc = 12V amb Symbol Parameter PLL1 I Current load on RO pin RO C Capacitance on CO pin CO f Frequency of hor. oscillator HO f Free-running frequency of hor. oscill. HO(0) f Hor. PLL1 capture frequency HOCapt f Temperature drift of free-running freq ---------------------------- - Average horizontal oscillator sensitivity ...
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... VSIZE at maximum PARAL (Sad12h) full span (9) VPOS at medium VSIZE at minimum VSIZE at medium VSIZE at maximum VPOS at max. or min. VSIZE at minimum positions always meet this condition. The formula to calculate CO =0.12125/( HO( TDA9113 Value Units Min. Typ. Max. 1.0 % 1.8 % 2.8 % 1.75 % 2.2 % 2.8 % 1.75 % HOut pin with V TopHPLL2 C V ...
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... TDA9113 6.5 - VERTICAL SECTION V = 12V amb Symbol Parameter AGC-controlled vertical oscillator sawtooth; Ext. load resistance on R (10) L(VAGCCap) VAGCCap pin Sawtooth bottom voltage on V (11) VOB VCap pin Sawtooth top voltage on VCap V VOT pin t Sawtooth Discharge time VODis f Free-running frequency VO(0) f AGC loop capture frequency ...
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... HEHT HEHT (18)(19)(21)(23)(30) (15 (19)(20)(21)(23)(24)(25)(26)(30) VSIZE at maximum PCC (Sad0C): x0000000b x1000000b x1111111b Tracking with VSIZE : PCC at x1000000b VSIZE (Sad07): x0000000b x1000000b (19)(20)(21)(24)(27)(29)(30) PCC at x1111111b VPOS (Sad08): x0000000b x1111111b TDA9113 Value Units Typ. Max. 6 RefO 2 V 3. V/V V/V 100 ppm 0.7 V 1.5 V 0.25 V 0.5 V ...
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... TDA9113 Symbol Parameter Keystone correction component V of the EW-drive signal on EW-Key EWOut pin Top corner correction compo- V nent of the EW-drive signal on EW-TCor EWOut pin Bottom corner correction compo- V nent of the EW-drive signal on EW-BCor EWOut pin Tracking of EW-drive signal with V EW horizontal frequency ...
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... HO R =10k L(VDyCor) (23) at medium VSIZE VDC-AMP (Sad15h): x0000000b x1000000b x1111111b VDC-AMP at maximum VSIZE (Sad07): x0000000b x1111111b VDC-AMP at maximum VPOS (Sad08): (37) x0000000b x1111111b TDA9113 Value Units Min. Typ. Max 2.1 V 200 ppm/ C 3.7 V 1 (1.34 (1.07) +24 -24.5 ...
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... TDA9113 HDyCorTr Note 35: Ratio of the amplitude at register map” quadratic function of horizontal size adjustment. HDyCorTr Note 36: Ratio of the amplitude at register map” quadratic function of V Note 37: Ratio of parabola voltage Note 38: Refer to Figure 14. Note 39: Taken for reference at given position of Note 40: Unsigned value ...
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... HBOutEn = ”Enable” HBOutEn = ”Disable” I =10mA BOut V =8V RefO BREF (Sad03): x0000000b x1000000b x1111111b BOutPh = ”0” The same values to be found on pin BRegIn, while regulation loop is TDA9113 Value Units Min. Typ. Max 100 dB 6 MHz -0.2 A -0.5 2.0 mA (41) 0 ...
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... TDA9113 6.9 - MISCELLANEOUS V = 12V amb Symbol Parameter Vertical blanking and horizontal lock indication composite output HLckVBk I Sink current to HLckVBk pin SinkLckBk V Output voltage on HLckVBk output OLckBk Horizont al moiré canceller moi re – -------------------------------------- - Modulation moiré function Vertical moiré ...
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... C-correction 0A VOut x1111111 Byte Waveform V amp(min) V mid(VOut) V amp(max) V mid(VOut) 3.5V V mid(VOut) 3.5V V mid(VOut) V mid(VOut) 3.5V V VOamp Null V VOS-cor V VOamp Max. 1 VOamp V VOC-cor 0 1 VOamp Null V VOamp V VOC-cor 0 1 TDA9113 Effect on Screen 19/50 ...
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... TDA9113 Function Sad Pin x0000000: Vertical moiré 0B VOut amplitude x1111111: 00000000 Horizontal size 10h EWOut 11111111 x0000000 Keystone 0D EWOut correction x1111111 x0000000 Pin cushion 0C EWOut correction x1111111 x1111111 Top corner 0E EWOut correction x0000000 x1111111 Bottom corner 0F EWOut correction x0000000 20/50 Byte ...
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... H-phase 0 1 PCAC(max) static H-phase 0 1 VDyCorP V VD-V(max) V VD- VD-V(max) V VD- VDyCorP V VD-V(max) V VD- See Figure 14 on page 36 TDA9113 Effect on Screen Application dependent Application dependent 21/50 ...
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... TDA9113 BUS CONTROL REGISTER MAP The device slave address write mode and 8D in read mode. Bold weight denotes default value at Power-On-Reset Bus data in the adjustment register is buffered and internally applied with discharge of the vertical os- (49) cillator . In order to ensure compatibility with future devices, all “ ...
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... Start of the flyback 1: Middle of the flyback Sad06/D7 - BOutPol Polarity of B+ drive signal on 0: adapted to N type of power MOS - high level to make it conductive 1: adapted to P type of power MOS - low level to make it conductive TDA9113 ...
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... TDA9113 Sad07/D7 - BOutPh Phase of start of B+ drive signal on 0: Just after horizontal flyback pulse 1: With one of edges of line drive signal on HOut pin, selected by BOHEdge Sad08/D7 - EWTrHFr Tracking of all corrections contained in wave- form on pin EWOut with Horizontal Frequency 0: Not active 1: Active Sad15/D7 - ...
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... Not locked (amplitude non-stabilized) pin. Once the SadXX/D7 - HLock Status of Locking of Horizontal PLL1 0: Locked 1: Not locked Bus bit). This taken into account by application S way SDetReset bit and validation of information provided in the flag after read- TDA9113 (52) pin H/HVSyn pin with respect 25/50 ...
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... TDA9113 9 - OPERATING DESCRIPTION 9.1 - SUPPLY AND CONTROL 9.1.1 - Power supply and voltage references The device is designed for a typical value of power supply voltage order to avoid erratic operation of the circuit at power supply ramp-up or ramp-down, the value monitored. See Figure 1 and electrical CC specifications. At switch-on, the device enters a “ ...
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... HPosF pin. The loop is independent of the trailing edge of sync. signal and only locks to its leading edge. By design, the PLL1 does not suffer from any dead TDA9113 2 C bus bit, the reset action 2 C bus transfer to ...
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... TDA9113 band even while locked. The speed of the PLL1 depends on the current value provided by the charge pump. While not locked, the current is very low, to slow down the changes of VCO frequency and thus protect the external power components at sync. signal change. In locked state, the cur- ...
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... As they are summed, their ef- fect on the phase tends to reach maximum span at top and bottom of the picture. As all the compo- nents of the resulting correction waveform (linear for parallelogram correction and parabola of 2nd order for Pin cushion asymmetry correction) are TDA9113 RS Flip-Flop VCO discharge control V ...
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... TDA9113 generated from the output vertical deflection drive waveform, they both track with real vertical ampli- tude and position (including breathing compensa- tion), thus being fixed on the screen. Refer to I BUS CONTROL REGISTER MAP on page 22 for 2 details bus controls. Figure 7. Horizontal timing diagram ...
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... When the synchronization pulse is not present, the charging current is fixed consequence, the free-running frequency value of the capacitor on pin VCap. It can be roughly calculated using the following formula 150nF f = VO(0) C (VCap) TDA9113 minimum value 2 HPOS (I C) range maximum value Soft stop Stop Stop BOut ...
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... TDA9113 The frequency range in which the AGC loop can regulate the amplitude also depends on this ca- pacitor. The C- and S-corrections of shape serve to com- pensate for the vertical deflection system non-line- arity. They are controlled via CCOR and SCOR bus controls. Shape-corrected sawtooth with regulated ampli- tude is lead to amplitude control stage ...
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... It can be switched off by EWTrHFr I by default). The EW waveform signal is buffered by an NPN emitter follower, the emitter of which is directly routed to EWOut output, with no internal resistor to ground biased externally bus TDA9113 2 C bus controls through bus bit (off 33/50 ...
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... TDA9113 Figure 12. Geometric corrections’ schematic diagram Controls: one-quadrant 2 HDC-AMP (I two-quadrant 2 HDC-SYM (I V mid(VOut) 2 VOut 23 Top parabola generator Vertical ramp 2 2 Bottom parabola generator 34/50 2 VDC-AMP (I C) Tracking C) VDyCorPol (I HEHTIn/HSize C) 2 HDyCorTr (I C) H-dynamic correction 2 2 PCC (I C) TCC (I C) Tracking HEHTIn/HSize ...
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... VDyCorPol I C bus bit. It tracks with real verti- cal amplitude and position (including breathing compensation also affected by C- and S-cor bus bit to rections. The use of both correction waveforms the application (e.g. dynamic focus). TDA9113 V (max HSIZE ( (min) EW ...
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... TDA9113 Figure 14. HDyCor output horizontal component waveform t HVD-Hflat 1 Shaped H-flyback 0 9.7 - DC/DC CONTROLLER SECTION The section is designed to control a switch-mode DC/DC converter. A switch-mode DC/DC conver- tor generates a DC voltage from a DC voltage of different value (higher or lower) with little power losses. The DC/DC controller is synchronized to horizontal deflection frequency to minimize poten- tial interference into the picture ...
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... D7) D3) 0 don’t care Middle of H-flyback plus Monostable ~500ns HBOutEn XRayAlarm TDA9113 Timing of Off-to-O n transition on BOut outpu t BTrigDel Falling edge of H-drive signal Rising edge of H-drive signal type BOut I3 P type BOutPol 37/50 ...
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... TDA9113 9.8 - MISCELLANEOUS 9.8.1 - Safety functions The safety functions comprise supply voltage monitoring with appropriate actions, soft start and soft stop features on H-drive and B-drive signals on HOut and BOut outputs and X-ray protection. For supply voltage supervision, refer to paragraph Power supply and voltage references on page 26 and Figure 1 ...
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... V-sawtooth discharge S V-sync HPosF (timing) SOFT START & STOP Out :2 B-drive inhibit H-drive inhibit L1=No blank/blank level L2=H-lock/unlock level 2 2 Int. signal bit/flag TDA9113 XRayAlarm H-drive inhibition (overrule) V-drive inhibition B-drive inhibition HLckVbk 3 L3=L1+L2 HLock Pin 39/50 ...
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... TDA9113 9.8.4 - Composite output HLckVBk The composite output HLckVBk provides, at the same time, information about lock state of PLL1 and early vertical blanking pulse. As both signals have two logical levels, a four level signal is used to define the combination of the two. Schematic di- agram putting together all safety functions and ...
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... Figure 18. Ground layout recommendations TDA9113 TDA9113 General Ground 41/50 ...
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... TDA9113 10 - INTERNAL SCHEMATICS Figure 19. 5V Pins 1-2 200 H/HVSyn VSyn Figure 20. 12V 13 RefOut HLckVBk l 3 Figure 21. 12V Pin 13 HOSCF Pin 4 42/50 Figure 22. RefOut 12V 13 5 HPLL2C Figure 23. 12V RefOut Figure 24. 12V RefOut ...
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... Figure 25. HPLL1F 9 Figure 26. RefOut 12V HPosF 10 Figure 27. 12V 12V HDyCor 11 Figure 28. 12V HFly 12 Figure 29. BComp 14 Figure 30. 12V 15 BRegIn TDA9113 43/50 ...
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... TDA9113 Figure 31. 12V BISense 16 Figure 32. 12V 18 VEHTIn 17 HEHTIn Figure 33. 12V Pin 13 VOSCF 19 44/50 Figure 34. 12V VAGCCap 20 Figure 35. 12V 22 VCap Figure 36. 12V VOut 23 ...
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... Figure 37. 12V 24 EWOut 32 VDyCor Figure 38. 12V XRay 25 Figure 39. 12V 26 HOut 28 BOut Figure 40. 30 SCL 31SDA TDA9113 45/50 ...
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... TDA9113 11 - PACKAGE MECHANICAL DATA 32 PINS - PLASTIC SHRINK Millimeters Dimensions Min. A 3.556 A1 0.508 A2 3.048 B 0.356 B1 0.762 C .203 D 27.43 E 9.906 E1 7.620 2.540 46/50 Stand-off Typ. Max. Min. 3.759 5.080 0.140 0.020 3.556 4.572 0.120 0.457 0.584 0.014 1.016 1.397 ...
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... HOT Horizontal Output Transistor Inter-Integrated Circuit IIC Inter-Integrated Circuit MCU Micro-Controller Unit NAND Negated AND (logic operation) NPN Negative-Positive-Negative OSC OSCillator PLL Phase-Locked Loop PNP Positive-Negative-Positive REF REFerence RS, R-S Reset-Set S/W SoftWare TTL Transistor Transistor Logic VCO Voltage-Controlled Oscillator 2 C-bus transfer TDA9113 47/50 ...
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... TDA9113 PRELIMINARY DATA 06/ 2000 version 3.1 Document creation 07/2000 version 3.2 BLOCK DIAGRAM : QUICK REFERENCE DATA : addition of parrallelogram BUS CONTROL REGISTER MAP : subaddress 08 - 0:no tracking Few corrections in text 08/ 2000 version 3.4 Figure 16 and Figure 17: corrections ABSOLUTE MAXIMUM RATINGS : definition of VESD Miscellaneous : X-ray detection instead of protection Horizontal moiré ...
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... TDA9113 Note 32: added: “VEW[fmax] is the value at condition VHO>VHOThrfr”. page 31 Section 9.4 - “stabilizing time” replaced by “stabilization time” (twice) page 18 Section 6.9 - vertical moiré canceller: max. values moved to typ.values October 2001 version 4.3 page 35 Section 9.5 - correction of figure 13 “EWOut output waveform” ...
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... TDA9113 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no respon- sibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics ...